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Reel/Frame:047243/0001   Pages: 959
Recorded: 08/23/2018
Attorney Dkt #:4816.238
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 17987
Page 177 of 180
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
1
Patent #:
9729131
Issue Dt:
08/08/2017
Application #:
14866250
Filing Dt:
09/25/2015
Publication #:
US20170093386
Pub Dt:
03/30/2017
Title:
SYSTEM AND METHOD FOR DUTY CYCLE CORRECTION
2
Patent #:
10352775
Issue Dt:
07/16/2019
Application #:
14866371
Filing Dt:
09/25/2015
Publication #:
US20170089766
Pub Dt:
03/30/2017
Title:
SYSTEMS AND METHODS FOR REDUCING TEMPERATURE SENSOR READING VARIATION DUE TO DEVICE MISMATCH
3
Patent #:
9696910
Issue Dt:
07/04/2017
Application #:
14867139
Filing Dt:
09/28/2015
Publication #:
US20160018993
Pub Dt:
01/21/2016
Title:
DATA COMPRESSION AND MANAGEMENT
4
Patent #:
9640588
Issue Dt:
05/02/2017
Application #:
14867185
Filing Dt:
09/28/2015
Publication #:
US20160020256
Pub Dt:
01/21/2016
Title:
MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS
5
Patent #:
9865611
Issue Dt:
01/09/2018
Application #:
14867914
Filing Dt:
09/28/2015
Publication #:
US20160020218
Pub Dt:
01/21/2016
Title:
MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS
6
Patent #:
9734915
Issue Dt:
08/15/2017
Application #:
14867948
Filing Dt:
09/28/2015
Publication #:
US20160019970
Pub Dt:
01/21/2016
Title:
SHIELDED VERTICALLY STACKED DATA LINE ARCHITECTURE FOR MEMORY
7
Patent #:
10109357
Issue Dt:
10/23/2018
Application #:
14867985
Filing Dt:
09/28/2015
Publication #:
US20160019974
Pub Dt:
01/21/2016
Title:
MEMORY REFRESH METHODS AND APPARATUSES
8
Patent #:
9792097
Issue Dt:
10/17/2017
Application #:
14868047
Filing Dt:
09/28/2015
Publication #:
US20160019034
Pub Dt:
01/21/2016
Title:
METHOD AND APPARATUS FOR COMPILING REGULAR EXPRESSIONS
9
Patent #:
9607692
Issue Dt:
03/28/2017
Application #:
14868604
Filing Dt:
09/29/2015
Publication #:
US20160099048
Pub Dt:
04/07/2016
Title:
THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
10
Patent #:
9552876
Issue Dt:
01/24/2017
Application #:
14868896
Filing Dt:
09/29/2015
Publication #:
US20160019958
Pub Dt:
01/21/2016
Title:
DESCENDING SET VERIFY FOR PHASE CHANGE MEMORY
11
Patent #:
9379241
Issue Dt:
06/28/2016
Application #:
14869546
Filing Dt:
09/29/2015
Publication #:
US20160020322
Pub Dt:
01/21/2016
Title:
SEMICONDUCTOR DEVICE WITH STRAINED CHANNELS
12
Patent #:
9437263
Issue Dt:
09/06/2016
Application #:
14871723
Filing Dt:
09/30/2015
Publication #:
US20160027486
Pub Dt:
01/28/2016
Title:
APPARATUSES AND METHODS FOR PROVIDING STROBE SIGNALS TO MEMORIES
13
Patent #:
9405679
Issue Dt:
08/02/2016
Application #:
14872455
Filing Dt:
10/01/2015
Publication #:
US20160026564
Pub Dt:
01/28/2016
Title:
DETERMINING A LOCATION OF A MEMORY DEVICE IN A SOLID STATE DEVICE
14
Patent #:
9418848
Issue Dt:
08/16/2016
Application #:
14873089
Filing Dt:
10/01/2015
Publication #:
US20160027638
Pub Dt:
01/28/2016
Title:
METHODS OF FORMING PATTERNS WITH A MASK FORMED UTILIZING A BRUSH LAYER
15
Patent #:
9722014
Issue Dt:
08/01/2017
Application #:
14873893
Filing Dt:
10/02/2015
Publication #:
US20160027865
Pub Dt:
01/28/2016
Title:
MEMORY DEVICES INCLUDING CAPACITOR STRUCTURES HAVING IMPROVED AREA EFFICIENCY
16
Patent #:
10177122
Issue Dt:
01/08/2019
Application #:
14874064
Filing Dt:
10/02/2015
Publication #:
US20160049387
Pub Dt:
02/18/2016
Title:
HIGH VOLTAGE SOLID-STATE TRANSDUCERS AND SOLID-STATE TRANSDUCER ARRAYS HAVING ELECTRICAL CROSS-CONNECTIONS AND ASSOCIATED SYSTEMS AND METHODS
17
Patent #:
9836218
Issue Dt:
12/05/2017
Application #:
14874068
Filing Dt:
10/02/2015
Publication #:
US20160098208
Pub Dt:
04/07/2016
Title:
COMPUTING REDUCTION AND PREFIX SUM OPERATIONS IN MEMORY
18
Patent #:
9940026
Issue Dt:
04/10/2018
Application #:
14874151
Filing Dt:
10/02/2015
Publication #:
US20160098209
Pub Dt:
04/07/2016
Title:
MULTIDIMENSIONAL CONTIGUOUS MEMORY ALLOCATION
19
Patent #:
9601384
Issue Dt:
03/21/2017
Application #:
14874652
Filing Dt:
10/05/2015
Publication #:
US20160027701
Pub Dt:
01/28/2016
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE COMPRISING FIRST AND SECOND NITRIDE LAYERS
20
Patent #:
11385797
Issue Dt:
07/12/2022
Application #:
14874841
Filing Dt:
10/05/2015
Publication #:
US20170097781
Pub Dt:
04/06/2017
Title:
SOLID STATE STORAGE DEVICE WITH VARIABLE LOGICAL CAPACITY BASED ON MEMORY LIFECYCLE
21
Patent #:
11355607
Issue Dt:
06/07/2022
Application #:
14875493
Filing Dt:
10/05/2015
Publication #:
US20160027882
Pub Dt:
01/28/2016
Title:
SEMICONDUCTOR DEVICE STRUCTURES WITH LINERS
22
Patent #:
9590014
Issue Dt:
03/07/2017
Application #:
14877006
Filing Dt:
10/07/2015
Publication #:
US20160035791
Pub Dt:
02/04/2016
Title:
RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS
23
Patent #:
NONE
Issue Dt:
Application #:
14877212
Filing Dt:
10/07/2015
Publication #:
US20160043089
Pub Dt:
02/11/2016
Title:
MEMORY CELL SUPPORT LATTICE
24
Patent #:
9929064
Issue Dt:
03/27/2018
Application #:
14877360
Filing Dt:
10/07/2015
Publication #:
US20160027706
Pub Dt:
01/28/2016
Title:
THROUGH-SUBSTRATE VIA (TSV) TESTING
25
Patent #:
9659950
Issue Dt:
05/23/2017
Application #:
14877997
Filing Dt:
10/08/2015
Publication #:
US20160027793
Pub Dt:
01/28/2016
Title:
SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED METHODS
26
Patent #:
9741409
Issue Dt:
08/22/2017
Application #:
14878354
Filing Dt:
10/08/2015
Publication #:
US20160027531
Pub Dt:
01/28/2016
Title:
APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY
27
Patent #:
9472265
Issue Dt:
10/18/2016
Application #:
14878452
Filing Dt:
10/08/2015
Publication #:
US20160027497
Pub Dt:
01/28/2016
Title:
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
28
Patent #:
9768123
Issue Dt:
09/19/2017
Application #:
14879363
Filing Dt:
10/09/2015
Publication #:
US20160035681
Pub Dt:
02/04/2016
Title:
SEMICONDUCTOR DEVICE STRUCTURES INLCUDING A DISTRIBUTED BRAGG REFLECTOR
29
Patent #:
9831002
Issue Dt:
11/28/2017
Application #:
14880504
Filing Dt:
10/12/2015
Publication #:
US20160035436
Pub Dt:
02/04/2016
Title:
APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE
30
Patent #:
9595672
Issue Dt:
03/14/2017
Application #:
14881630
Filing Dt:
10/13/2015
Publication #:
US20160035977
Pub Dt:
02/04/2016
Title:
MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME
31
Patent #:
9653444
Issue Dt:
05/16/2017
Application #:
14882088
Filing Dt:
10/13/2015
Publication #:
US20160099237
Pub Dt:
04/07/2016
Title:
MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS
32
Patent #:
9665462
Issue Dt:
05/30/2017
Application #:
14883377
Filing Dt:
10/14/2015
Publication #:
US20170109249
Pub Dt:
04/20/2017
Title:
APPARATUSES AND METHODS FOR ARBITRATING A SHARED TERMINAL FOR CALIBRATION OF AN IMPEDANCE TERMINATION
33
Patent #:
9766831
Issue Dt:
09/19/2017
Application #:
14883454
Filing Dt:
10/14/2015
Publication #:
US20170109091
Pub Dt:
04/20/2017
Title:
APPARATUSES AND METHODS FOR ARBITRATING A SHARED TERMINAL FOR CALIBRATION OF AN IMPEDANCE TERMINATION
34
Patent #:
9385317
Issue Dt:
07/05/2016
Application #:
14884035
Filing Dt:
10/15/2015
Publication #:
US20160035974
Pub Dt:
02/04/2016
Title:
Memory Cells and Methods of Forming Memory Cells
35
Patent #:
9734900
Issue Dt:
08/15/2017
Application #:
14885230
Filing Dt:
10/16/2015
Publication #:
US20160035418
Pub Dt:
02/04/2016
Title:
MEMORY DEVICE ARCHITECTURE
36
Patent #:
10163467
Issue Dt:
12/25/2018
Application #:
14885546
Filing Dt:
10/16/2015
Publication #:
US20160110135
Pub Dt:
04/21/2016
Title:
MULTIPLE ENDIANNESS COMPATIBILITY
37
Patent #:
9299449
Issue Dt:
03/29/2016
Application #:
14886536
Filing Dt:
10/19/2015
Publication #:
US20160042799
Pub Dt:
02/11/2016
Title:
METHODS AND APPARATUS FOR SENSING A MEMORY CELL
38
Patent #:
9858079
Issue Dt:
01/02/2018
Application #:
14887033
Filing Dt:
10/19/2015
Publication #:
US20160041828
Pub Dt:
02/11/2016
Title:
METHOD AND SYSTEM FOR GENERATING OBJECT CODE TO FACILITATE PREDICTIVE MEMORY RETRIEVAL
39
Patent #:
9671294
Issue Dt:
06/06/2017
Application #:
14887138
Filing Dt:
10/19/2015
Publication #:
US20160041042
Pub Dt:
02/11/2016
Title:
SEMICONDUCTOR DEVICE INCLUDING A TEMPERATURE SENSOR CIRCUIT
40
Patent #:
9865324
Issue Dt:
01/09/2018
Application #:
14887217
Filing Dt:
10/19/2015
Publication #:
US20170110173
Pub Dt:
04/20/2017
Title:
METHOD AND APPARATUS FOR DECODING COMMANDS
41
Patent #:
9972532
Issue Dt:
05/15/2018
Application #:
14887359
Filing Dt:
10/20/2015
Publication #:
US20160042995
Pub Dt:
02/11/2016
Title:
INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS AND THEIR FORMATION
42
Patent #:
10162526
Issue Dt:
12/25/2018
Application #:
14887951
Filing Dt:
10/20/2015
Publication #:
US20170109084
Pub Dt:
04/20/2017
Title:
LOGICAL ADDRESS HISTORY MANAGEMENT IN MEMORY DEVICE
43
Patent #:
9478270
Issue Dt:
10/25/2016
Application #:
14918249
Filing Dt:
10/20/2015
Publication #:
US20160042777
Pub Dt:
02/11/2016
Title:
DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA
44
Patent #:
9509535
Issue Dt:
11/29/2016
Application #:
14918346
Filing Dt:
10/20/2015
Publication #:
US20160043885
Pub Dt:
02/11/2016
Title:
MULTI-LEVEL SIGNALING
45
Patent #:
9524117
Issue Dt:
12/20/2016
Application #:
14918364
Filing Dt:
10/20/2015
Publication #:
US20160041785
Pub Dt:
02/11/2016
Title:
CONTROL OF PAGE ACCESS IN MEMORY
46
Patent #:
10049874
Issue Dt:
08/14/2018
Application #:
14920018
Filing Dt:
10/22/2015
Publication #:
US20160042941
Pub Dt:
02/11/2016
Title:
SELF-ASSEMBLED NANOSTRUCTURES INCLUDING METAL OXIDES AND SEMICONDUCTOR STRUCTURES COMPRISED THEREOF
47
Patent #:
10068875
Issue Dt:
09/04/2018
Application #:
14920394
Filing Dt:
10/22/2015
Publication #:
US20170117254
Pub Dt:
04/27/2017
Title:
APPARATUSES AND METHODS FOR HEAT TRANSFER FROM PACKAGED SEMICONDUCTOR DIE
48
Patent #:
10147480
Issue Dt:
12/04/2018
Application #:
14920537
Filing Dt:
10/22/2015
Publication #:
US20160188250
Pub Dt:
06/30/2016
Title:
SORT OPERATION IN MEMORY
49
Patent #:
9779784
Issue Dt:
10/03/2017
Application #:
14921509
Filing Dt:
10/23/2015
Publication #:
US20160125919
Pub Dt:
05/05/2016
Title:
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
50
Patent #:
10082976
Issue Dt:
09/25/2018
Application #:
14921877
Filing Dt:
10/23/2015
Publication #:
US20160103627
Pub Dt:
04/14/2016
Title:
METHOD AND APPARATUS FOR CONFIGURING WRITE PERFORMANCE FOR ELECTRICALLY WRITABLE MEMORY DEVICES
51
Patent #:
10467155
Issue Dt:
11/05/2019
Application #:
14923269
Filing Dt:
10/26/2015
Publication #:
US20170116139
Pub Dt:
04/27/2017
Title:
COMMAND PACKETS FOR THE DIRECT CONTROL OF NON-VOLATILE MEMORY CHANNELS WITHIN A SOLID STATE DRIVE
52
Patent #:
9793282
Issue Dt:
10/17/2017
Application #:
14925589
Filing Dt:
10/28/2015
Publication #:
US20160049417
Pub Dt:
02/18/2016
Title:
FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY
53
Patent #:
9601675
Issue Dt:
03/21/2017
Application #:
14926276
Filing Dt:
10/29/2015
Publication #:
US20160049565
Pub Dt:
02/18/2016
Title:
VERTICAL SOLID-STATE TRANSDUCERS HAVING BACKSIDE TERMINALS AND ASSOCIATED SYSTEMS AND METHODS
54
Patent #:
10452596
Issue Dt:
10/22/2019
Application #:
14927061
Filing Dt:
10/29/2015
Publication #:
US20170123707
Pub Dt:
05/04/2017
Title:
MEMORY CELLS CONFIGURED IN MULTIPLE CONFIGURATION MODES
55
Patent #:
10256098
Issue Dt:
04/09/2019
Application #:
14927217
Filing Dt:
10/29/2015
Publication #:
US20170125426
Pub Dt:
05/04/2017
Title:
Integrated Assemblies Containing Germanium
56
Patent #:
9548447
Issue Dt:
01/17/2017
Application #:
14927316
Filing Dt:
10/29/2015
Publication #:
US20160064658
Pub Dt:
03/03/2016
Title:
Integrated Memory and Methods of Forming Repeating Structures
57
Patent #:
10643700
Issue Dt:
05/05/2020
Application #:
14927329
Filing Dt:
10/29/2015
Publication #:
US20170125099
Pub Dt:
05/04/2017
Title:
APPARATUSES AND METHODS FOR ADJUSTING WRITE PARAMETERS BASED ON A WRITE COUNT
58
Patent #:
10347637
Issue Dt:
07/09/2019
Application #:
14927721
Filing Dt:
10/30/2015
Publication #:
US20160049406
Pub Dt:
02/18/2016
Title:
SEMICONDUCTOR DEVICES AND SYSTEMS INCLUDING MEMORY CELLS AND RELATED METHODS OF FABRICATION
59
Patent #:
9465287
Issue Dt:
10/11/2016
Application #:
14928159
Filing Dt:
10/30/2015
Publication #:
US20160048074
Pub Dt:
02/18/2016
Title:
METHODS OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE STRUCTURES
60
Patent #:
10162558
Issue Dt:
12/25/2018
Application #:
14928988
Filing Dt:
10/30/2015
Publication #:
US20170123715
Pub Dt:
05/04/2017
Title:
DATA TRANSFER TECHNIQUES FOR MULTIPLE DEVICES ON A SHARED BUS
61
Patent #:
10008381
Issue Dt:
06/26/2018
Application #:
14929070
Filing Dt:
10/30/2015
Publication #:
US20160056038
Pub Dt:
02/25/2016
Title:
Constructions Comprising Rutile-Type Titanium Oxide; And Methods of Forming And Utilizing Rutile-Type Titanium Oxide
62
Patent #:
9391092
Issue Dt:
07/12/2016
Application #:
14929853
Filing Dt:
11/02/2015
Publication #:
US20160056175
Pub Dt:
02/25/2016
Title:
Circuit Structures, Memory Circuitry, and Methods
63
Patent #:
9373636
Issue Dt:
06/21/2016
Application #:
14930504
Filing Dt:
11/02/2015
Publication #:
US20160071878
Pub Dt:
03/10/2016
Title:
Methods of Forming Semiconductor Constructions
64
Patent #:
10121697
Issue Dt:
11/06/2018
Application #:
14930524
Filing Dt:
11/02/2015
Publication #:
US20160056073
Pub Dt:
02/25/2016
Title:
Semiconductor Constructions; and Methods for Providing Electrically Conductive Material Within Openings
65
Patent #:
9799658
Issue Dt:
10/24/2017
Application #:
14931073
Filing Dt:
11/03/2015
Publication #:
US20160055973
Pub Dt:
02/25/2016
Title:
Methods Of Forming Capacitors
66
Patent #:
9646875
Issue Dt:
05/09/2017
Application #:
14931152
Filing Dt:
11/03/2015
Publication #:
US20160056069
Pub Dt:
02/25/2016
Title:
Methods of Forming Memory Arrays
67
Patent #:
9529736
Issue Dt:
12/27/2016
Application #:
14932503
Filing Dt:
11/04/2015
Publication #:
US20160055103
Pub Dt:
02/25/2016
Title:
APPARATUS, ELECTRONIC DEVICES AND METHODS ASSOCIATED WITH AN OPERATIVE TRANSITION FROM A FIRST INTERFACE TO A SECOND INTERFACE
68
Patent #:
9978810
Issue Dt:
05/22/2018
Application #:
14932707
Filing Dt:
11/04/2015
Publication #:
US20170125484
Pub Dt:
05/04/2017
Title:
THREE-DIMENSIONAL MEMORY APPARATUSES AND METHODS OF USE
69
Patent #:
10134470
Issue Dt:
11/20/2018
Application #:
14932746
Filing Dt:
11/04/2015
Publication #:
US20170125097
Pub Dt:
05/04/2017
Title:
APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME
70
Patent #:
9910594
Issue Dt:
03/06/2018
Application #:
14933874
Filing Dt:
11/05/2015
Publication #:
US20170131904
Pub Dt:
05/11/2017
Title:
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY PLANES OF A MEMORY DURING A MEMORY ACCESS OPERATION
71
Patent #:
9871044
Issue Dt:
01/16/2018
Application #:
14934659
Filing Dt:
11/06/2015
Publication #:
US20170133383
Pub Dt:
05/11/2017
Title:
ENHANCED CHARGE STORAGE MATERIALS, RELATED SEMICONDUCTOR MEMORY CELLS AND SEMICONDUCTOR DEVICES, AND RELATED SYSTEMS AND METHODS
72
Patent #:
NONE
Issue Dt:
Application #:
14935049
Filing Dt:
11/06/2015
Publication #:
US20160064480
Pub Dt:
03/03/2016
Title:
A SEMICONDUCTOR CONSTRUCTION COMPRISING ELECTRICALLY INSULATIVE MATERIAL FILLING A TRENCH HAVING AN UPPER WIDE PORTION OVER AND JOINING A NORROW BOTTOM PORTION
73
Patent #:
9553263
Issue Dt:
01/24/2017
Application #:
14935196
Filing Dt:
11/06/2015
Title:
RESISTIVE MEMORY ELEMENTS INCLUDING BUFFER MATERIALS, AND RELATED MEMORY CELLS, MEMORY DEVICES, ELECTRONIC SYSTEMS
74
Patent #:
10153047
Issue Dt:
12/11/2018
Application #:
14935744
Filing Dt:
11/09/2015
Publication #:
US20160064094
Pub Dt:
03/03/2016
Title:
NONCONSECUTIVE SENSING OF MULTILEVEL MEMORY CELLS
75
Patent #:
9698343
Issue Dt:
07/04/2017
Application #:
14936013
Filing Dt:
11/09/2015
Publication #:
US20160064655
Pub Dt:
03/03/2016
Title:
SEMICONDUCTOR DEVICE STRUCTURES INCLUDING FERROELECTRIC MEMORY CELLS
76
Patent #:
9530497
Issue Dt:
12/27/2016
Application #:
14936186
Filing Dt:
11/09/2015
Publication #:
US20160064078
Pub Dt:
03/03/2016
Title:
SYSTEMS, METHODS AND DEVICES FOR PROGRAMMING A MULTILEVEL RESISTIVE MEMORY CELL
77
Patent #:
10061709
Issue Dt:
08/28/2018
Application #:
14936209
Filing Dt:
11/09/2015
Publication #:
US20160062909
Pub Dt:
03/03/2016
Title:
SYSTEMS AND METHODS FOR ACCESSING MEMORY
78
Patent #:
9941238
Issue Dt:
04/10/2018
Application #:
14936542
Filing Dt:
11/09/2015
Publication #:
US20170133385
Pub Dt:
05/11/2017
Title:
WIRING WITH EXTERNAL TERMINAL
79
Patent #:
9564227
Issue Dt:
02/07/2017
Application #:
14936719
Filing Dt:
11/10/2015
Publication #:
US20160064085
Pub Dt:
03/03/2016
Title:
MEMORY DEVICE HAVING A DIFFERENT SOURCE LINE COUPLED TO EACH OF A PLURALITY OF LAYERS OF MEMORY CELL ARRAYS
80
Patent #:
9754643
Issue Dt:
09/05/2017
Application #:
14938193
Filing Dt:
11/11/2015
Publication #:
US20160064048
Pub Dt:
03/03/2016
Title:
ASYNCHRONOUS/SYNCHRONOUS INTERFACE
81
Patent #:
10048882
Issue Dt:
08/14/2018
Application #:
14939076
Filing Dt:
11/12/2015
Publication #:
US20160062695
Pub Dt:
03/03/2016
Title:
NON-VOLATILE MEMORY WITH LPDRAM
82
Patent #:
9696937
Issue Dt:
07/04/2017
Application #:
14940248
Filing Dt:
11/13/2015
Publication #:
US20160070508
Pub Dt:
03/10/2016
Title:
MEMORY SYSTEM DATA MANAGEMENT
83
Patent #:
9779839
Issue Dt:
10/03/2017
Application #:
14940327
Filing Dt:
11/13/2015
Publication #:
US20160071619
Pub Dt:
03/10/2016
Title:
METHODS FOR PROVIDING REDUNDANCY IN A MEMORY ARRAY COMPRISING MAPPING PORTIONS OF DATA ASSOCIATED WITH A DEFECTIVE ADDRESS
84
Patent #:
9412472
Issue Dt:
08/09/2016
Application #:
14940935
Filing Dt:
11/13/2015
Publication #:
US20160071618
Pub Dt:
03/10/2016
Title:
DETERMINING SOFT DATA FROM A HARD READ
85
Patent #:
9564576
Issue Dt:
02/07/2017
Application #:
14941088
Filing Dt:
11/13/2015
Publication #:
US20160072044
Pub Dt:
03/10/2016
Title:
MULTI-BIT FERROELECTRIC MEMORY DEVICE AND METHODS OF FORMING THE SAME
86
Patent #:
NONE
Issue Dt:
Application #:
14941288
Filing Dt:
11/13/2015
Publication #:
US20160118340
Pub Dt:
04/28/2016
Title:
Low-Resistance Interconnects and Methods of Making Same
87
Patent #:
9711214
Issue Dt:
07/18/2017
Application #:
14941365
Filing Dt:
11/13/2015
Publication #:
US20160172030
Pub Dt:
06/16/2016
Title:
METHODS, ARTICLES AND DEVICES FOR PULSE ADJUSTMENTS TO PROGRAM A MEMORY CELL
88
Patent #:
9691785
Issue Dt:
06/27/2017
Application #:
14942533
Filing Dt:
11/16/2015
Publication #:
US20160071880
Pub Dt:
03/10/2016
Title:
THREE-DIMENSIONAL STRUCTURED MEMORY DEVICES
89
Patent #:
9728548
Issue Dt:
08/08/2017
Application #:
14942573
Filing Dt:
11/16/2015
Publication #:
US20170141121
Pub Dt:
05/18/2017
Title:
VERTICAL MEMORY BLOCKS AND RELATED DEVICES AND METHODS
90
Patent #:
9852953
Issue Dt:
12/26/2017
Application #:
14942693
Filing Dt:
11/16/2015
Publication #:
US20160071775
Pub Dt:
03/10/2016
Title:
CMOS FABRICATION
91
Patent #:
9710182
Issue Dt:
07/18/2017
Application #:
14942701
Filing Dt:
11/16/2015
Publication #:
US20160070504
Pub Dt:
03/10/2016
Title:
APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN INTERFACE MEMORY
92
Patent #:
9780103
Issue Dt:
10/03/2017
Application #:
14942823
Filing Dt:
11/16/2015
Publication #:
US20170141119
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING INTEGRATED STRUCTURES
93
Patent #:
9465539
Issue Dt:
10/11/2016
Application #:
14943113
Filing Dt:
11/17/2015
Publication #:
US20160070476
Pub Dt:
03/10/2016
Title:
OPERATION MANAGEMENT IN A MEMORY DEVICE
94
Patent #:
9779829
Issue Dt:
10/03/2017
Application #:
14943541
Filing Dt:
11/17/2015
Publication #:
US20170140833
Pub Dt:
05/18/2017
Title:
ERASING MEMORY SEGMENTS IN A MEMORY BLOCK OF MEMORY CELLS USING SELECT GATE CONTROL LINE VOLTAGES
95
Patent #:
10153007
Issue Dt:
12/11/2018
Application #:
14944622
Filing Dt:
11/18/2015
Publication #:
US20160071556
Pub Dt:
03/10/2016
Title:
APPARATUSES INCLUDING A MEMORY ARRAY WITH SEPARATE GLOBAL READ AND WRITE LINES AND/OR SENSE AMPLIFIER REGION COLUMN SELECT LINE AND RELATED METHODS
96
Patent #:
9817392
Issue Dt:
11/14/2017
Application #:
14946486
Filing Dt:
11/19/2015
Publication #:
US20160077521
Pub Dt:
03/17/2016
Title:
PHOTOLITHOGRAPHY SYSTEMS AND ASSOCIATED METHODS OF OVERLAY ERROR CORRECTION
97
Patent #:
NONE
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Application #:
14947122
Filing Dt:
11/20/2015
Publication #:
US20170148495
Pub Dt:
05/25/2017
Title:
INPUT RECEIVER CIRCUIT
98
Patent #:
9502650
Issue Dt:
11/22/2016
Application #:
14947455
Filing Dt:
11/20/2015
Publication #:
US20160087200
Pub Dt:
03/24/2016
Title:
MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL
99
Patent #:
9552858
Issue Dt:
01/24/2017
Application #:
14947978
Filing Dt:
11/20/2015
Publication #:
US20160078912
Pub Dt:
03/17/2016
Title:
STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL
100
Patent #:
10163655
Issue Dt:
12/25/2018
Application #:
14948074
Filing Dt:
11/20/2015
Publication #:
US20170148674
Pub Dt:
05/25/2017
Title:
THROUGH SUBSTRATE VIA LINER DENSIFICATION
Assignor
1
U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Exec Dt:
06/29/2018
Assignee
1
MICRON TECHNOLOGY, INC.
8000 S. FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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