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01/30/2001
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09/26/2000
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12/10/1998
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01/30/2001
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12/10/1998
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04/25/2000
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03/20/2001
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10/31/2000
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12/11/1998
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12/19/2000
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12/11/1998
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07/04/2000
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12/15/1998
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08/14/2001
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12/16/1998
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07/03/2001
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12/17/1998
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12/13/2001
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12/17/1998
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03/13/2001
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12/17/1998
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12/11/2001
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12/18/1998
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01/02/2001
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12/18/1998
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06/12/2001
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12/21/1998
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07/17/2001
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12/21/1998
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07/09/2002
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12/21/1998
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09/12/2000
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12/21/1998
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07/04/2000
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12/21/1998
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08/08/2000
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12/21/1998
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02/06/2001
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12/22/1998
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04/03/2001
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12/22/1998
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06/05/2001
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12/21/1998
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09/04/2001
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12/23/1998
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09/05/2000
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12/28/1998
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08/01/2000
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12/28/1998
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08/21/2001
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12/28/1998
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11/13/2007
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12/24/1998
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08/08/2002
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05/14/2002
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12/23/1998
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01/10/2002
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05/09/2000
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12/23/1998
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QUANTUM MAGNETIC MEMORY
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05/13/2003
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12/23/1998
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01/03/2002
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05/23/2000
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12/28/1998
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COMBINED CACHE TAG AND DATA MEMORY ARCHITECTURE
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06/25/2002
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12/28/1998
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03/20/2001
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12/29/1998
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NUCLEATION AND DEPOSITION OF PT FILMS USING ULTRAVIOLET IRRADIATION
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05/30/2000
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12/29/1998
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05/22/2001
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12/29/1998
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METHOD AND A RELATED CIRCUIT FOR ADJUSTING THE DURATION OF A SYNCHRONIZATION SIGNAL ATD FOR TIMING THE ACCESS TO A NON-VOLATILE MEMORY
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09/05/2000
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12/29/1998
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08/22/2000
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12/29/1998
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03/27/2001
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12/28/1998
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METHOD AND APPARATUS FOR STOPPING MECHANICAL AND CHEMICAL MECHANICAL PLANARIZATION OF SUBTRATES AT DESIRED ENDPOINTS
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12/12/2000
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12/29/1998
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08/15/2000
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12/30/1998
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09/24/2002
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12/30/1998
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METHOD OF FABRICATING TAPE ATTACHMENT CHIP-ON-BOARD ASSEMBLIES
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07/24/2001
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12/30/1998
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12/19/2000
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12/31/1998
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HOT PLUG STRUCTURE AND METHOD FOR ENGAGING/DISENGAGING PCI COMPLIANT CARD
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08/07/2001
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12/31/1998
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ARRANGEMENT AND METHOD FOR PROVIDING FLEXIBLE MANAGEMENT OF A NETWORK
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02/22/2000
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12/31/1998
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HIGH VOLTAGE DRIVER CIRCUIT FOR A DECODING CIRCUIT IN MULTILEVEL NON-VOLATILE MEMORY DEVICES
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07/17/2001
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01/04/1999
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INTERCONNECT WITH PRESSURE SENSING MECHANISM FOR TESTING SEMICONDUCTOR WAFERS
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04/25/2000
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01/04/1999
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11/30/1999
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01/05/1999
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05/09/2000
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01/06/1999
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10/03/2000
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01/05/1999
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06/18/2002
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01/04/1999
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01/31/2002
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12/19/2000
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01/05/1999
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MEMORY CARD WHICH IS THERMALLY CONTROLLED
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07/04/2000
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01/06/1999
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02/29/2000
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01/06/1999
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SYNCHRONOUS MEMORY WITH PROGRAMMABLE READ LATENCY
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05/15/2001
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01/05/1999
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INTERCONNECT HAVING RECESSED CONTACT MEMBERS WITH PENETRATING BLADES FOR TESTING SEMICONDUCTOR DICE AND PACKAGES WITH CONTACT BUMPS
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03/20/2001
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01/05/1999
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METHOD OF DEPOSITING A SMOOTH CONFORMAL ALUMINUM FILM ON A REFRACTORY METAL NITRIDE LAYER
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04/09/2002
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01/06/1999
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01/09/2001
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01/06/1999
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UNIVERSAL PULSE SYNCHRONIZER
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12/12/2000
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01/05/1999
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USE OF PALLADIUM IN IC MANUFACTURING
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11/30/1999
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01/08/1999
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SEMICONDUCTOR PROCESSING METHODS OF FORMING A CONTACT OPENING TO A SEMICONDUCTOR SUBSTRATE
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09/12/2000
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01/07/1999
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02/27/2001
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01/08/1999
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METHOD FOR IMPROVING THE SIDEWALL STOICHIOMETRY OF THIN FILM CAPACITORS
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08/10/1999
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01/11/1999
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03/07/2000
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01/11/1999
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MEMORY WITH VARIABLE WRITE DRIVER OPERATION
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03/06/2001
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09228595
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01/12/1999
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METHOD OF MANUFACTURING A SINGLE DEPOSITION LAYER METAL DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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09228725
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Filing Dt:
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01/12/1999
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Title:
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FACET ETCH FOR IMPROVED STEP COVERAGE OF INTEGRATED CIRCUIT CONTACTS
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09229373
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Filing Dt:
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01/13/1999
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Title:
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UTILIZATION OF DIE REPATTERN LAYERS FOR DIE INTERNAL CONNECTIONS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09229474
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Filing Dt:
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01/13/1999
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Title:
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OPERATING VOLTAGE SELECTION CIRCUIT FOR NON-VOLATILE SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09229476
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Filing Dt:
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01/13/1999
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Title:
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POLISHING PAD WITH INCOMPRESSIBLE HIGHL SOLUBLE PARTICLES FOR CHEMICAL-MECHANICAL PLANARIZATION OF SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09229487
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Filing Dt:
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01/13/1999
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Title:
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APPARATUS AND METHODS FOR CONDITIONING POLISHING PADS IN MECHANICAL AND/OR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC-DEVICE SUBSTRATE ASSEMBLIES
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09229518
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Filing Dt:
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01/13/1999
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Title:
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SEMICONDUCTOR CIRCUIT COMPONENTS AND CAPACITORS
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Patent #:
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Issue Dt:
|
04/11/2000
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Application #:
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09229891
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Filing Dt:
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01/14/1999
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Title:
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LARGE GRAIN SINGLE CRYSTAL VERTICAL THIN FILM POLYSILICON MOSFETS
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Patent #:
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Issue Dt:
|
06/05/2001
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Application #:
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09231129
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Filing Dt:
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12/30/1998
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Title:
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METHOD AND A CIRCUIT FOR IMPROVING THE EFFECTIVENESS OF ESD PROTECTION IN CIRCUIT STRUCTURES FORMED IN A SEMICONDUCTOR
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09231137
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Filing Dt:
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01/15/1999
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Title:
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WELL RESISTOR FOR ESD PROTECTION OF CMOS CIRCUITS
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Patent #:
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Issue Dt:
|
08/27/2002
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Application #:
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09231158
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Filing Dt:
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01/15/1999
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Title:
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METHOD AND SYSTEM FOR CENTRALIZED STORAGE AND MANAGEMENT OF ELECTRONIC MESSAGES
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Patent #:
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Issue Dt:
|
01/23/2001
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Application #:
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09231176
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Filing Dt:
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01/14/1999
|
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Title:
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A METHOD FOR MAKING A TRENCH ISOLATION FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
02/13/2001
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Application #:
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09231306
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Filing Dt:
|
01/13/1999
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Title:
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CIRCUIT BOARD GROUNDING AND SUPPORT STRUCTURE APPARATUS AND METHOD
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Patent #:
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Issue Dt:
|
09/19/2000
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Application #:
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09231346
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Filing Dt:
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01/13/1999
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Title:
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SEMICONDUCTOR DEVICE HAVING A SUBSTRATE, AN UNDOPED SILICON OXIDE STRUCTURE, AND AN OVERLYING DOPED SILICON OXIDE STRUCTURE WITH A SIDE WALL TERMINATING AT THE UNDOPED SILICON OXIDE STRUCTURE
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Patent #:
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Issue Dt:
|
06/13/2000
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Application #:
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09231725
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Filing Dt:
|
01/15/1999
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Title:
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SIGNAL TRANSITION DETECTOR FOR ASYNCHRONOUS CIRCUITS
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Patent #:
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Issue Dt:
|
12/07/1999
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Application #:
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09231853
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Filing Dt:
|
01/14/1999
|
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Title:
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LOW-TO-HIGH VOLTAGE CMOS DRIVER CIRCUIT FOR DRIVING CAPACTIVE LOADS
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Patent #:
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Issue Dt:
|
04/24/2001
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Application #:
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09232442
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Filing Dt:
|
01/15/1999
|
|
Title:
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METHOD AND SYSTEM FOR ATTACHING SEMICONDUCTOR DICE TO SUBSTRATES
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|
|
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Patent #:
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Issue Dt:
|
02/05/2002
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Application #:
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09233299
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Filing Dt:
|
01/19/1999
|
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Title:
|
TRI-STATING ADDRESS INPUT CIRCUIT
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Patent #:
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Issue Dt:
|
04/09/2002
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Application #:
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09233313
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Filing Dt:
|
01/19/1999
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Publication #:
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Pub Dt:
|
01/17/2002
| | | | |
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Title:
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METHOD AND COMPOSITE FOR DECREASING CHARGE LEAKAGE
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Patent #:
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Issue Dt:
|
06/04/2002
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Application #:
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09233358
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Filing Dt:
|
01/19/1999
|
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Title:
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METHOD AND APPARATUS FOR PACKAGING FLIP CHIP BARE DIE ON PRINTED CIRCUIT BOARDS
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Patent #:
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Issue Dt:
|
01/11/2005
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Application #:
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09233377
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Filing Dt:
|
01/18/1999
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|
Publication #:
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Pub Dt:
|
03/07/2002
| | | | |
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Title:
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METHOD OF FORMING A REFRACTORY METAL SILICIDE
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Patent #:
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Issue Dt:
|
09/11/2001
|
Application #:
|
09233774
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Filing Dt:
|
01/19/1999
|
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Title:
|
INTEGRATED CIRCUIT HAVING AN ON-BOARD REFERENCE GENERATOR
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|
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Patent #:
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Issue Dt:
|
12/26/2000
|
Application #:
|
09233871
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Filing Dt:
|
01/20/1999
|
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Title:
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LATERAL BIPOLAR TRANSISTORS AND SYSTEMS USING SUCH
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|
|
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Patent #:
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|
Issue Dt:
|
10/24/2000
|
Application #:
|
09233930
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Filing Dt:
|
01/20/1999
|
|
Title:
|
METHOD OF PATTERNING SUBSTRATES USING MULTILAYER RESIST PROCESSING
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|
|
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Patent #:
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Issue Dt:
|
07/25/2000
|
Application #:
|
09233938
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Filing Dt:
|
01/20/1999
|
|
Title:
|
EQUILIBRATE CIRCUIT FOR DYNAMIC PLATE SENSING MEMORIES
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/18/2000
|
Application #:
|
09233997
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
METHOD OF CONSTRUCTING STACKED PACKAGES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/30/2000
|
Application #:
|
09234003
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
FACEPLATES HAVING BLACK MATRIX MATERIAL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09234016
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
DRIVING CIRCUIT WITH THREE OUTPUT LEVELS, ONE OUTPUT LEVEL BEING A BOOSTED LEVEL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09234194
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
DEVICE FOR DEMODULATING A BINARY PHASE-SHIFT KEYED SIGNAL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
09234233
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
SEMICONDUCTOR PROCESSING METHODS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09234242
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
TEST INTERPROSER FOR USE WITH BALL GRID ARRAY PACKAGES ASSEMBLIES AND BALL GRID ARRAY PACKAGES INCLUDING SAME AND METHODS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09234282
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
SPACER PATTERNED, HIGH DIELECTRIC CONSTANT CAPACITOR
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|
