|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13344009
|
Filing Dt:
|
01/05/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
Interlevel Dielectric Stack for Interconnect Structures
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13344352
|
Filing Dt:
|
01/05/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
13344517
|
Filing Dt:
|
01/05/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
NANOWIRE FLOATING GATE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13344806
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13344885
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13344955
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
05/03/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13345120
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
THICK ON-CHIP HIGH-PERFORMANCE WIRING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13345233
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
FINFET WITH FULLY SILICIDED GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
13345252
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
05/03/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13345266
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13345388
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
13345619
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13345629
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13345636
|
Filing Dt:
|
01/06/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13345879
|
Filing Dt:
|
01/09/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
Methods of Forming a Replacement Gate Electrode With a Reentrant Profile
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13345881
|
Filing Dt:
|
01/09/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
ISOLATED ZENER DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
13347014
|
Filing Dt:
|
01/10/2012
|
Publication #:
|
|
Pub Dt:
|
05/03/2012
| | | | |
Title:
|
THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13347435
|
Filing Dt:
|
01/10/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
TRANSISTOR WITH STRESS ENHANCED CHANNEL AND METHODS FOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13347571
|
Filing Dt:
|
01/10/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
INDUCTOR WITH LAMINATED YOKE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13348018
|
Filing Dt:
|
01/11/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13348142
|
Filing Dt:
|
01/11/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13348188
|
Filing Dt:
|
01/11/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13348256
|
Filing Dt:
|
01/11/2012
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13348771
|
Filing Dt:
|
01/12/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13349158
|
Filing Dt:
|
01/12/2012
|
Publication #:
|
|
Pub Dt:
|
05/03/2012
| | | | |
Title:
|
EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2016
|
Application #:
|
13349203
|
Filing Dt:
|
01/12/2012
|
Publication #:
|
|
Pub Dt:
|
05/03/2012
| | | | |
Title:
|
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13349942
|
Filing Dt:
|
01/13/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON STRAINED ISOLATION MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
13350817
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13350891
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
METHODS OF REDUCING GATE LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
13350908
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
METHODS OF FORMING A DIELECTRIC CAP LAYER ON A METAL GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13350981
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13351012
|
Filing Dt:
|
01/16/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
TRENCH-GENERATED TRANSISTOR STRUCTURES, DEVICE STRUCTURES, AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13351294
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13351370
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD FOR FABRICATING AIR GAP INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13351398
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
13351402
|
Filing Dt:
|
01/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13352737
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13352775
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13352851
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13353118
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13353162
|
Filing Dt:
|
01/18/2012
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13353708
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13353925
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
13354070
|
Filing Dt:
|
01/19/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13354363
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13354705
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13354739
|
Filing Dt:
|
01/20/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHOD OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13356013
|
Filing Dt:
|
01/23/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13357285
|
Filing Dt:
|
01/24/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13358101
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
SOPHISTICATED GATE ELECTRODE STRUCTURES FORMED BY CAP LAYER REMOVAL WITH REDUCED LOSS OF EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13358172
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHOD OF MANUFACTURING SWITCHING FILTERS AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13358180
|
Filing Dt:
|
01/25/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13358963
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
3D OPTOELECTRONIC PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13359100
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
3D OPTOELECTRONIC PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13359107
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
CELL ARRAY AND DENSITY FEATURES WITH DECOUPLING CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13359197
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Methods of Forming SRAM Devices Using Sidewall Image Transfer Techniques
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13359242
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13359454
|
Filing Dt:
|
01/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13359634
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13359729
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
ELECTRON BEAM SCULPTING OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13359858
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Mosfet Structures Having Compressively Strained Silicon Channel
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13360055
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13360083
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360203
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360248
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360270
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13360277
|
Filing Dt:
|
01/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13361004
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13361051
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13361595
|
Filing Dt:
|
01/30/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
METHODS FOR QUANTITATIVELY EVALUATING THE QUALITY OF DOUBLE PATTERNING TECHNOLOGY-COMPLIANT LAYOUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13362366
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SUPERCONDUCTING QUANTUM CIRCUIT HAVING A RESONANT CAVITY THERMALIZED WITH METAL COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13362398
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
METHODS OF EPITAXIAL FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13362763
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13362862
|
Filing Dt:
|
01/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13363995
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13364002
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
3D INTEGRATED CIRCUITS STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13364153
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13364171
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
GRID-LINE-FREE CONTACT FOR A PHOTOVOLTAIC CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13364273
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
LOCAL BOTTOM GATES FOR GRAPHENE AND CARBON NANOTUBE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13364311
|
Filing Dt:
|
02/01/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13364346
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
IMPLEMENTING MULTIPLE DIFFERENT TYPES OF DIES FOR MEMORY STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
13364494
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
TUNNEL JUNCTION VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13364569
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
DESIGN STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13364976
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13365030
|
Filing Dt:
|
02/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT CONTACT STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13365505
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
13365764
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13365961
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
ESTIMATING POWER CONSUMPTION OF AN ELECTRONIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13365989
|
Filing Dt:
|
02/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
GATE CONFIGURATION DETERMINATION AND SELECTION FROM STANDARD CELL LIBRARY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13368750
|
Filing Dt:
|
02/08/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
Interface Engineering to Optimize Metal-III-V Contacts
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13368901
|
Filing Dt:
|
02/08/2012
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
Method of Fabricating Self-Aligned Nanotube Field Effect Transistor
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13369246
|
Filing Dt:
|
02/08/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13369261
|
Filing Dt:
|
02/08/2012
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
SOI BIPOLAR JUNCTION TRANSISTOR WITH SUBSTRATE BIAS VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
13369273
|
Filing Dt:
|
02/08/2012
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13369382
|
Filing Dt:
|
02/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
JUNCTION BUTTING ON SOI BY RAISED EPITAXIAL STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13369872
|
Filing Dt:
|
02/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
INTEGRATED TRANSFORMERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13369938
|
Filing Dt:
|
02/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
METHODS FOR ANALYZING DESIGN RULES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13370144
|
Filing Dt:
|
02/09/2012
|
Title:
|
LOW-SWING SIGNALING SCHEME FOR DATA COMMUNICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13370722
|
Filing Dt:
|
02/10/2012
|
Title:
|
Methods of FinFET Height Control
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13370944
|
Filing Dt:
|
02/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
COMPLEMENTARY TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EPITAXIALLY FORMED SEMICONDUCTOR MATERIALS IN THE DRAIN AND SOURCE AREAS
|
|