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Patent Assignment Details
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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 41 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
Issue Dt:
07/16/2013
Application #:
13430177
Filing Dt:
03/26/2012
Publication #:
Pub Dt:
07/19/2012
Title:
PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL
2
Patent #:
Issue Dt:
07/16/2013
Application #:
13430179
Filing Dt:
03/26/2012
Publication #:
Pub Dt:
07/19/2012
Title:
PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL
3
Patent #:
Issue Dt:
06/17/2014
Application #:
13431368
Filing Dt:
03/27/2012
Publication #:
Pub Dt:
10/03/2013
Title:
RELATIVE ORDERING CIRCUIT SYNTHESIS
4
Patent #:
Issue Dt:
04/08/2014
Application #:
13431456
Filing Dt:
03/27/2012
Publication #:
Pub Dt:
10/03/2013
Title:
PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES
5
Patent #:
Issue Dt:
09/16/2014
Application #:
13431539
Filing Dt:
03/27/2012
Publication #:
Pub Dt:
07/26/2012
Title:
ELECTRIC VEHICLE CHARGING TRANSACTION INTERFACE FOR MANAGING ELECTRIC VEHICLE CHARGING TRANSACTIONS
6
Patent #:
Issue Dt:
11/04/2014
Application #:
13431770
Filing Dt:
03/27/2012
Publication #:
Pub Dt:
07/26/2012
Title:
METHODS OF MANUFACTURING FINFET DEVICES
7
Patent #:
Issue Dt:
06/17/2014
Application #:
13432421
Filing Dt:
03/28/2012
Publication #:
Pub Dt:
07/26/2012
Title:
DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
8
Patent #:
Issue Dt:
05/07/2013
Application #:
13432440
Filing Dt:
03/28/2012
Publication #:
Pub Dt:
07/19/2012
Title:
PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK
9
Patent #:
Issue Dt:
01/14/2014
Application #:
13433401
Filing Dt:
03/29/2012
Publication #:
Pub Dt:
07/26/2012
Title:
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME
10
Patent #:
Issue Dt:
01/14/2014
Application #:
13433423
Filing Dt:
03/29/2012
Publication #:
Pub Dt:
07/19/2012
Title:
PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE
11
Patent #:
Issue Dt:
12/17/2013
Application #:
13434964
Filing Dt:
03/30/2012
Publication #:
Pub Dt:
10/03/2013
Title:
NON-PLANAR CAPACITOR AND METHOD OF FORMING THE NON-PLANAR CAPACITOR
12
Patent #:
Issue Dt:
09/02/2014
Application #:
13435828
Filing Dt:
03/30/2012
Publication #:
Pub Dt:
10/03/2013
Title:
SINGLE CYCLE DATA COPY FOR TWO-PORT SRAM
13
Patent #:
Issue Dt:
12/10/2013
Application #:
13436045
Filing Dt:
03/30/2012
Publication #:
Pub Dt:
10/03/2013
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE
14
Patent #:
Issue Dt:
12/17/2013
Application #:
13436323
Filing Dt:
03/30/2012
Publication #:
Pub Dt:
10/03/2013
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS
15
Patent #:
Issue Dt:
05/20/2014
Application #:
13437273
Filing Dt:
04/02/2012
Publication #:
Pub Dt:
10/03/2013
Title:
DISCONTINUOUS GUARD RING
16
Patent #:
Issue Dt:
04/01/2014
Application #:
13437309
Filing Dt:
04/02/2012
Publication #:
Pub Dt:
10/03/2013
Title:
STRESS REDUCTION MEANS FOR WARP CONTROL OF SUBSTRATES THROUGH CLAMPING
17
Patent #:
Issue Dt:
01/07/2014
Application #:
13437506
Filing Dt:
04/02/2012
Publication #:
Pub Dt:
10/03/2013
Title:
IDENTIFICATION OF LOCALIZABLE FUNCTION CALLS
18
Patent #:
Issue Dt:
09/17/2013
Application #:
13438394
Filing Dt:
04/03/2012
Publication #:
Pub Dt:
10/03/2013
Title:
TECHNIQUES FOR USING MATERIAL SUBSTITUTION PROCESSES TO FORM REPLACEMENT METAL GATE ELECTRODES OF SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS
19
Patent #:
Issue Dt:
01/21/2014
Application #:
13438508
Filing Dt:
04/03/2012
Publication #:
Pub Dt:
07/26/2012
Title:
HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE
20
Patent #:
Issue Dt:
02/25/2014
Application #:
13439016
Filing Dt:
04/04/2012
Publication #:
Pub Dt:
10/10/2013
Title:
PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION
21
Patent #:
Issue Dt:
11/19/2013
Application #:
13439885
Filing Dt:
04/05/2012
Publication #:
Pub Dt:
10/10/2013
Title:
AUTOMATIC PARITY CHECKING IDENTIFICATION
22
Patent #:
Issue Dt:
08/13/2013
Application #:
13441245
Filing Dt:
04/06/2012
Publication #:
Pub Dt:
08/02/2012
Title:
ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
23
Patent #:
Issue Dt:
02/04/2014
Application #:
13442683
Filing Dt:
04/09/2012
Publication #:
Pub Dt:
10/10/2013
Title:
PROCESSES FOR PREPARING STRESSED SEMICONDUCTOR WAFERS AND FOR PREPARING DEVICES INCLUDING THE STRESSED SEMICONDUCTOR WAFERS
24
Patent #:
Issue Dt:
05/10/2016
Application #:
13443003
Filing Dt:
04/10/2012
Publication #:
Pub Dt:
08/02/2012
Title:
GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER
25
Patent #:
Issue Dt:
12/31/2013
Application #:
13443418
Filing Dt:
04/10/2012
Publication #:
Pub Dt:
11/21/2013
Title:
BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED
26
Patent #:
Issue Dt:
01/14/2014
Application #:
13443426
Filing Dt:
04/10/2012
Publication #:
Pub Dt:
10/10/2013
Title:
VIA SELECTION IN INTEGRATED CIRCUIT DESIGN
27
Patent #:
Issue Dt:
03/04/2014
Application #:
13444415
Filing Dt:
04/11/2012
Publication #:
Pub Dt:
08/09/2012
Title:
ADVANCED LOW K CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES
28
Patent #:
Issue Dt:
02/03/2015
Application #:
13444447
Filing Dt:
04/11/2012
Publication #:
Pub Dt:
10/17/2013
Title:
REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING
29
Patent #:
Issue Dt:
12/16/2014
Application #:
13444647
Filing Dt:
04/11/2012
Publication #:
Pub Dt:
10/17/2013
Title:
INTEGRATED CIRCUIT INCLUDING THERMAL GATE, RELATED METHOD AND DESIGN STRUCTURE
30
Patent #:
Issue Dt:
06/17/2014
Application #:
13445101
Filing Dt:
04/12/2012
Publication #:
Pub Dt:
08/02/2012
Title:
Nano/Microwire Solar Cell Fabricated by Nano/Microsphere Lithography
31
Patent #:
Issue Dt:
12/03/2013
Application #:
13445128
Filing Dt:
04/12/2012
Publication #:
Pub Dt:
10/17/2013
Title:
SOLVING CONGESTION USING NET GROUPING
32
Patent #:
Issue Dt:
03/26/2013
Application #:
13445172
Filing Dt:
04/12/2012
Publication #:
Pub Dt:
08/09/2012
Title:
WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES
33
Patent #:
Issue Dt:
07/29/2014
Application #:
13445475
Filing Dt:
04/12/2012
Publication #:
Pub Dt:
10/17/2013
Title:
WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE
34
Patent #:
Issue Dt:
01/28/2014
Application #:
13445641
Filing Dt:
04/12/2012
Publication #:
Pub Dt:
08/09/2012
Title:
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
35
Patent #:
Issue Dt:
10/08/2013
Application #:
13445719
Filing Dt:
04/12/2012
Publication #:
Pub Dt:
10/17/2013
Title:
INTEGRATED CIRCUITS HAVING IMPROVED METAL GATE STRUCTURES AND METHODS FOR FABRICATING SAME
36
Patent #:
Issue Dt:
06/18/2013
Application #:
13446115
Filing Dt:
04/13/2012
Publication #:
Pub Dt:
05/30/2013
Title:
SWITCH WITH REDUCED INSERTION LOSS
37
Patent #:
Issue Dt:
05/13/2014
Application #:
13446369
Filing Dt:
04/13/2012
Publication #:
Pub Dt:
10/17/2013
Title:
MITIGATION OF MASK DEFECTS BY PATTERN SHIFTING
38
Patent #:
Issue Dt:
04/01/2014
Application #:
13446418
Filing Dt:
04/13/2012
Publication #:
Pub Dt:
10/17/2013
Title:
PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS
39
Patent #:
Issue Dt:
03/26/2013
Application #:
13446602
Filing Dt:
04/13/2012
Publication #:
Pub Dt:
08/02/2012
Title:
DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE
40
Patent #:
Issue Dt:
12/31/2013
Application #:
13447019
Filing Dt:
04/13/2012
Publication #:
Pub Dt:
08/09/2012
Title:
FINFET STRUCTURES AND METHODS FOR FABRICATING THE SAME
41
Patent #:
Issue Dt:
03/12/2013
Application #:
13447221
Filing Dt:
04/15/2012
Publication #:
Pub Dt:
08/02/2012
Title:
PROOF BASED BOUNDED MODEL CHECKING
42
Patent #:
Issue Dt:
02/18/2014
Application #:
13448749
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
10/17/2013
Title:
SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES
43
Patent #:
Issue Dt:
10/15/2013
Application #:
13449378
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/09/2012
Title:
POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM
44
Patent #:
Issue Dt:
07/23/2013
Application #:
13449419
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/09/2012
Title:
LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE
45
Patent #:
Issue Dt:
02/04/2014
Application #:
13449732
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/09/2012
Title:
NOISE COUPLING REDUCTION AND IMPEDANCE DISCONTINUITY CONTROL IN HIGH-SPEED CERAMIC MODULES
46
Patent #:
Issue Dt:
12/03/2013
Application #:
13451087
Filing Dt:
04/19/2012
Publication #:
Pub Dt:
08/16/2012
Title:
SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO
47
Patent #:
Issue Dt:
11/19/2013
Application #:
13451382
Filing Dt:
04/19/2012
Publication #:
Pub Dt:
10/24/2013
Title:
DATAPATH PLACEMENT USING TIERED ASSIGNMENT
48
Patent #:
Issue Dt:
09/16/2014
Application #:
13451902
Filing Dt:
04/20/2012
Publication #:
Pub Dt:
10/24/2013
Title:
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
49
Patent #:
Issue Dt:
06/16/2015
Application #:
13451947
Filing Dt:
04/20/2012
Publication #:
Pub Dt:
10/24/2013
Title:
COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP
50
Patent #:
Issue Dt:
10/01/2013
Application #:
13453027
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
09/26/2013
Title:
FLEXIBLE FIBER TO WAFER INTERFACE
51
Patent #:
Issue Dt:
01/28/2014
Application #:
13453043
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
10/24/2013
Title:
3D INTEGRATED CIRCUIT SYSTEM WITH CONNECTING VIA STRUCTURE AND METHOD FOR FORMING THE SAME
52
Patent #:
Issue Dt:
10/29/2013
Application #:
13453215
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/09/2012
Title:
CMOS STRUCTURE INCLUDING NON-PLANAR HYBRID ORIENTATION SUBSTRATE WITH PLANAR GATE ELECTRODES & METHOD FOR FABRICATION
53
Patent #:
Issue Dt:
07/16/2013
Application #:
13453426
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/16/2012
Title:
STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS
54
Patent #:
Issue Dt:
05/28/2013
Application #:
13453508
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/16/2012
Title:
STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES
55
Patent #:
Issue Dt:
11/12/2013
Application #:
13453740
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
10/24/2013
Title:
SILICIDATION AND/OR GERMANIDATION ON SIGE OR GE BY COSPUTTERING NI AND GE AND USING AN INTRALAYER FOR THERMAL STABILITY
56
Patent #:
Issue Dt:
12/16/2014
Application #:
13454433
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
10/24/2013
Title:
INTEGRATED CIRCUITS HAVING PROTRUDING SOURCE AND DRAIN REGIONS AND METHODS FOR FORMING INTEGRATED CIRCUITS
57
Patent #:
Issue Dt:
04/01/2014
Application #:
13454709
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
08/16/2012
Title:
SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE
58
Patent #:
Issue Dt:
10/14/2014
Application #:
13454928
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
10/24/2013
Title:
SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE
59
Patent #:
Issue Dt:
01/08/2013
Application #:
13455174
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/16/2012
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SOI STRUCTURE USING A BULK SEMICONDUCTOR STARTING WAFER
60
Patent #:
Issue Dt:
03/25/2014
Application #:
13455177
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/23/2012
Title:
TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE
61
Patent #:
Issue Dt:
11/26/2013
Application #:
13455394
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS
62
Patent #:
Issue Dt:
05/27/2014
Application #:
13455489
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
CET AND GATE CURRENT LEAKAGE REDUCTION IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY HEAT TREATMENT AFTER DIFFUSION LAYER REMOVAL
63
Patent #:
Issue Dt:
06/03/2014
Application #:
13455579
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE
64
Patent #:
Issue Dt:
03/25/2014
Application #:
13455653
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
DIODE-TRIGGERED SILICON CONTROLLED RECTIFIER WITH AN INTEGRATED DIODE
65
Patent #:
Issue Dt:
05/07/2013
Application #:
13455725
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/23/2012
Title:
METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER
66
Patent #:
Issue Dt:
06/24/2014
Application #:
13455732
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES
67
Patent #:
Issue Dt:
03/04/2014
Application #:
13456456
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
10/31/2013
Title:
NON-VOLATILE MEMORY DEVICE FORMED BY DUAL FLOATING GATE DEPOSIT
68
Patent #:
Issue Dt:
09/02/2014
Application #:
13456596
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
12/27/2012
Title:
ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
69
Patent #:
Issue Dt:
03/10/2015
Application #:
13457692
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE
70
Patent #:
Issue Dt:
09/30/2014
Application #:
13457735
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
PHOTORESIST COMPOSITION CONTAINING A PROTECTED HYDROXYL GROUP FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
71
Patent #:
Issue Dt:
06/14/2016
Application #:
13459460
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
10/31/2013
Title:
Assembly of Electronic and Optical Devices
72
Patent #:
Issue Dt:
06/24/2014
Application #:
13459785
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
10/31/2013
Title:
ELONGATED VIA STRUCTURES
73
Patent #:
Issue Dt:
02/18/2014
Application #:
13461912
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
STRUCTURE FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS
74
Patent #:
Issue Dt:
08/12/2014
Application #:
13461935
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
DOPED CORE TRIGATE FET STRUCTURE AND METHOD
75
Patent #:
Issue Dt:
09/30/2014
Application #:
13461960
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
08/23/2012
Title:
PHOTORESIST COMPOSITIONS
76
Patent #:
Issue Dt:
12/02/2014
Application #:
13462185
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES
77
Patent #:
Issue Dt:
05/30/2017
Application #:
13462619
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
78
Patent #:
Issue Dt:
05/20/2014
Application #:
13463283
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
08/23/2012
Title:
METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)
79
Patent #:
Issue Dt:
04/08/2014
Application #:
13463592
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
11/07/2013
Title:
FINFET COMPATIBLE PC-BOUNDED ESD DIODE
80
Patent #:
Issue Dt:
06/03/2014
Application #:
13465129
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
LAYOUT DESIGNS WITH VIA ROUTING STRUCTURES
81
Patent #:
Issue Dt:
03/25/2014
Application #:
13465134
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES
82
Patent #:
Issue Dt:
10/08/2013
Application #:
13465486
Filing Dt:
05/07/2012
Title:
METHODS OF FORMING CMOS SEMICONDUCTOR DEVICES
83
Patent #:
Issue Dt:
08/19/2014
Application #:
13465633
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME
84
Patent #:
Issue Dt:
12/25/2012
Application #:
13467385
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
08/30/2012
Title:
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
85
Patent #:
Issue Dt:
12/24/2013
Application #:
13468281
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
08/30/2012
Title:
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
86
Patent #:
Issue Dt:
09/03/2013
Application #:
13468307
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
09/06/2012
Title:
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
87
Patent #:
Issue Dt:
03/24/2015
Application #:
13471711
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
09/06/2012
Title:
HIGH DENSITY LOW POWER NANOWIRE PHASE CHANGE MATERIAL MEMORY DEVICE
88
Patent #:
Issue Dt:
02/11/2014
Application #:
13471736
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
SUB-CIRCUIT MODELS WITH CORNER INSTANCES FOR VLSI DESIGNS
89
Patent #:
Issue Dt:
01/14/2014
Application #:
13471852
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES
90
Patent #:
Issue Dt:
04/22/2014
Application #:
13471955
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
MOS CAPACITORS WITH A FINFET PROCESS
91
Patent #:
Issue Dt:
09/03/2013
Application #:
13472044
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
12/20/2012
Title:
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
92
Patent #:
Issue Dt:
02/25/2014
Application #:
13472584
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
11/21/2013
Title:
SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR
93
Patent #:
Issue Dt:
08/26/2014
Application #:
13472605
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHOD AND STRUCTURE FOR FORMING FIN RESISTORS
94
Patent #:
Issue Dt:
12/30/2014
Application #:
13472674
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
11/21/2013
Title:
ELECTRICALLY CONTROLLED OPTICAL FUSE AND METHOD OF FABRICATION
95
Patent #:
Issue Dt:
09/10/2013
Application #:
13472680
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
03/14/2013
Title:
CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES
96
Patent #:
Issue Dt:
02/04/2014
Application #:
13474304
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
09/13/2012
Title:
ANALYZING ANTICIPATED VALUE AND EFFORT IN USING CLOUD COMPUTING TO PROCESS A SPECIFIED WORKLOAD
97
Patent #:
Issue Dt:
04/09/2013
Application #:
13474349
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
09/13/2012
Title:
SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME
98
Patent #:
Issue Dt:
12/10/2013
Application #:
13474443
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES
99
Patent #:
Issue Dt:
12/17/2013
Application #:
13474916
Filing Dt:
05/18/2012
Publication #:
Pub Dt:
09/13/2012
Title:
METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE
100
Patent #:
Issue Dt:
01/06/2015
Application #:
13474949
Filing Dt:
05/18/2012
Publication #:
Pub Dt:
11/14/2013
Title:
BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
Assignor
1
Exec Dt:
10/22/2020
Assignee
1
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SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
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