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|
Patent #:
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|
Issue Dt:
|
03/31/2015
|
Application #:
|
13782452
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Filing Dt:
|
03/01/2013
|
Publication #:
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|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN AN ELECTRIC MOTOR
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Patent #:
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Issue Dt:
|
05/05/2015
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Application #:
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13782467
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Filing Dt:
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03/01/2013
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Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
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Patent #:
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Issue Dt:
|
03/24/2015
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Application #:
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13782537
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Filing Dt:
|
03/01/2013
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Publication #:
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|
Pub Dt:
|
09/04/2014
| | | | |
Title:
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SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
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Patent #:
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Issue Dt:
|
05/27/2014
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Application #:
|
13782826
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Filing Dt:
|
03/01/2013
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Title:
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METHODS OF MODIFYING A PHYSICAL DESIGN OF AN ELECTRICAL CIRCUIT USED IN THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
02/18/2014
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Application #:
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13783388
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Filing Dt:
|
03/03/2013
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Title:
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SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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13783438
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Filing Dt:
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03/04/2013
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
|
12/16/2014
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Application #:
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13783562
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Filing Dt:
|
03/04/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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DEFECT REMOVAL PROCESS
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Patent #:
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Issue Dt:
|
03/31/2015
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Application #:
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13783729
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Filing Dt:
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03/04/2013
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Publication #:
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Pub Dt:
|
07/03/2014
| | | | |
Title:
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HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13784220
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Filing Dt:
|
03/04/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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CONTACT POWER RAIL
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Patent #:
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Issue Dt:
|
03/04/2014
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Application #:
|
13785109
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Filing Dt:
|
03/05/2013
|
Title:
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TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
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Patent #:
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Issue Dt:
|
01/27/2015
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Application #:
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13785403
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Filing Dt:
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03/05/2013
|
Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
|
03/18/2014
|
Application #:
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13785438
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Filing Dt:
|
03/05/2013
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
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Patent #:
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Issue Dt:
|
02/03/2015
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Application #:
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13785468
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Filing Dt:
|
03/05/2013
|
Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
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Patent #:
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|
Issue Dt:
|
09/02/2014
|
Application #:
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13785602
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Filing Dt:
|
03/05/2013
|
Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
|
MEMORY STATE SENSING BASED ON CELL CAPACITANCE
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Patent #:
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Issue Dt:
|
09/02/2014
|
Application #:
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13785816
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Filing Dt:
|
03/05/2013
|
Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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FRONT SIDE WAFER ID PROCESSING
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Patent #:
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Issue Dt:
|
03/17/2015
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Application #:
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13786627
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Filing Dt:
|
03/06/2013
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Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
BARRIER LAYER CONFORMALITY IN COPPER INTERCONNECTS
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|
Patent #:
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Issue Dt:
|
10/25/2016
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Application #:
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13787090
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Filing Dt:
|
03/06/2013
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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MULTILAYER PATTERN TRANSFER FOR CHEMICAL GUIDES
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Patent #:
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Issue Dt:
|
12/17/2013
|
Application #:
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13787384
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Filing Dt:
|
03/06/2013
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Title:
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METHODS OF SELECTIVELY FORMING RUTHENIUM LINER LAYER
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Patent #:
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Issue Dt:
|
07/21/2015
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Application #:
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13788406
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Filing Dt:
|
03/07/2013
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Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
|
High Density Memory Cells Using Lateral Epitaxy
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|
Patent #:
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|
Issue Dt:
|
03/04/2014
|
Application #:
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13788980
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Filing Dt:
|
03/07/2013
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
|
HIGH CAPACITANCE TRENCH CAPACITOR
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|
Patent #:
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|
Issue Dt:
|
12/16/2014
|
Application #:
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13789018
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Filing Dt:
|
03/07/2013
|
Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
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REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13789966
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Filing Dt:
|
03/08/2013
|
Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
METHODS OF REPAIRING DAMAGED INSULATING MATERIALS BY INTRODUCING CARBON INTO THE LAYER OF INSULATING MATERIAL
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Patent #:
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Issue Dt:
|
03/29/2016
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Application #:
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13790727
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Filing Dt:
|
03/08/2013
|
Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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SCATTERING ENHANCED THIN ABSORBER FOR EUV RETICLE AND A METHOD OF MAKING
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|
Patent #:
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Issue Dt:
|
06/16/2015
|
Application #:
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13791520
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Filing Dt:
|
03/08/2013
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
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SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
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|
Patent #:
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Issue Dt:
|
11/18/2014
|
Application #:
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13791545
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Filing Dt:
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03/08/2013
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
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STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
08/09/2016
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Application #:
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13792730
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Filing Dt:
|
03/11/2013
|
Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH
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Patent #:
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Issue Dt:
|
07/01/2014
|
Application #:
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13792933
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Filing Dt:
|
03/11/2013
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
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Patent #:
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Issue Dt:
|
04/14/2015
|
Application #:
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13792950
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Filing Dt:
|
03/11/2013
|
Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
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TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS
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|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
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13793082
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Filing Dt:
|
03/11/2013
|
Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
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METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING AN IMPLANTATION OF IONS INTO A LAYER OF SPACER MATERIAL
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|
Patent #:
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Issue Dt:
|
07/08/2014
|
Application #:
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13793363
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Filing Dt:
|
03/11/2013
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
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|
Patent #:
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Issue Dt:
|
09/09/2014
|
Application #:
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13795030
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Filing Dt:
|
03/12/2013
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Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
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FLUID DISTRIBUTION METHOD FACILITATING COOLING OF ELECTRONICS RACK(S) AND SIMULATING HEATED AIRFLOW EXHAUST OF ELECTRONICS RACK(S)
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|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13795198
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Filing Dt:
|
03/12/2013
|
Title:
|
HIERARCHICAL LAYOUT VERSUS SCHEMATIC (LVS) COMPARISON WITH EXTRANEOUS DEVICE ELIMINATION
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|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
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13796154
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Filing Dt:
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03/12/2013
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
|
09/09/2014
|
Application #:
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13796259
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Filing Dt:
|
03/12/2013
|
Publication #:
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|
Pub Dt:
|
07/25/2013
| | | | |
Title:
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DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
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13796278
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Filing Dt:
|
03/12/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
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NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS
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|
Patent #:
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|
Issue Dt:
|
07/15/2014
|
Application #:
|
13796418
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Filing Dt:
|
03/12/2013
|
Title:
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NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH EPITIXIALLY GROWN SOURCE AND DRAIN
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Patent #:
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Issue Dt:
|
09/23/2014
|
Application #:
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13797001
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Filing Dt:
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03/12/2013
|
Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
|
01/20/2015
|
Application #:
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13797117
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Filing Dt:
|
03/12/2013
|
Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF FORMING FINFET DEVICES WITH A SHARED GATE STRUCTURE
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|
Patent #:
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Issue Dt:
|
07/21/2015
|
Application #:
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13798446
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Filing Dt:
|
03/13/2013
|
Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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HIGH DENSITY MULTI-ELECTRODE ARRAY
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13798503
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Filing Dt:
|
03/13/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES BY FORMING A REGION THAT INCLUDES A SCHOTTKY BARRIER LOWERING MATERIAL
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Patent #:
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Issue Dt:
|
10/07/2014
|
Application #:
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13798616
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Filing Dt:
|
03/13/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL STRUCTURE BY PERFORMING AN ANNEAL PROCESS
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Patent #:
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Issue Dt:
|
08/19/2014
|
Application #:
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13799148
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Filing Dt:
|
03/13/2013
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Title:
|
THERMALLY ASSISTED MRAM WITH MULTILAYER STRAP AND TOP CONTACT FOR LOW THERMAL CONDUCTIVITY
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Patent #:
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Issue Dt:
|
02/24/2015
|
Application #:
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13799539
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Filing Dt:
|
03/13/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
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INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT)
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|
Patent #:
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Issue Dt:
|
02/10/2015
|
Application #:
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13799741
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Filing Dt:
|
03/13/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
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TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES BASED ON AN AMORPHIZATION PROCESS AND A HEAT TREATMENT
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|
Patent #:
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|
Issue Dt:
|
09/30/2014
|
Application #:
|
13799814
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Filing Dt:
|
03/13/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING CONTROLLED FINAL METAL CRITICAL DIMENSION
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|
Patent #:
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|
Issue Dt:
|
12/22/2015
|
Application #:
|
13800091
|
Filing Dt:
|
03/13/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FABRICATING BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE
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Patent #:
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Issue Dt:
|
09/16/2014
|
Application #:
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13800966
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Filing Dt:
|
03/13/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS
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|
Patent #:
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|
Issue Dt:
|
12/23/2014
|
Application #:
|
13803048
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Filing Dt:
|
03/14/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
STITCH INSERTION FOR REDUCING COLOR DENSITY DIFFERENCES IN DOUBLE PATTERNING TECHNOLOGY (DPT)
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|
Patent #:
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|
Issue Dt:
|
01/13/2015
|
Application #:
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13803281
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Filing Dt:
|
03/14/2013
|
Publication #:
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Pub Dt:
|
08/08/2013
| | | | |
Title:
|
HIGHLY SCALABLE TRENCH CAPACITOR
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|
Patent #:
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|
Issue Dt:
|
10/01/2013
|
Application #:
|
13826830
|
Filing Dt:
|
03/14/2013
|
Publication #:
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|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING
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|
Patent #:
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|
Issue Dt:
|
02/25/2014
|
Application #:
|
13826874
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Filing Dt:
|
03/14/2013
|
Publication #:
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|
Pub Dt:
|
08/08/2013
| | | | |
Title:
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METHOD FOR FORMING SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP
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|
Patent #:
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|
Issue Dt:
|
03/03/2015
|
Application #:
|
13827786
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Filing Dt:
|
03/14/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A METAL-INSULATOR-METAL CAPACITOR
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|
Patent #:
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|
Issue Dt:
|
08/05/2014
|
Application #:
|
13828276
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Filing Dt:
|
03/14/2013
|
Title:
|
DOPING OF FINFET STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
04/21/2015
|
Application #:
|
13832442
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METAL LAYER ENABLING DIRECTED SELF-ASSEMBLY SEMICONDUCTOR LAYOUT DESIGNS
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|
Patent #:
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|
Issue Dt:
|
05/13/2014
|
Application #:
|
13832929
|
Filing Dt:
|
03/15/2013
|
Publication #:
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|
Pub Dt:
|
08/22/2013
| | | | |
Title:
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LOW HARMONIC RF SWITCH IN SOI
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|
|
Patent #:
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|
Issue Dt:
|
08/05/2014
|
Application #:
|
13833713
|
Filing Dt:
|
03/15/2013
|
Title:
|
FACILITATING THE DESIGN OF A CLOCK GRID IN AN INTEGRATED CIRCUIT
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|
|
Patent #:
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|
Issue Dt:
|
02/17/2015
|
Application #:
|
13834058
|
Filing Dt:
|
03/15/2013
|
Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
06/17/2014
|
Application #:
|
13834410
|
Filing Dt:
|
03/15/2013
|
Title:
|
METHODS OF FORMING ISOLATION STRUCTURES AND FINS ON A FINFET SEMICONDUCTOR DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
03/01/2016
|
Application #:
|
13834608
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK
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|
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13834946
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Filing Dt:
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03/15/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF FORMING TRENCH/HOLE TYPE FEATURES IN A LAYER OF MATERIAL OF AN INTEGRATED CIRCUIT PRODUCT
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Patent #:
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Issue Dt:
|
12/02/2014
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Application #:
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13836057
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Filing Dt:
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03/15/2013
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
Title:
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PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN
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Patent #:
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Issue Dt:
|
07/29/2014
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Application #:
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13837624
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Filing Dt:
|
03/15/2013
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Title:
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VIA NON-STANDARD LIMITING PARAMETERS
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Patent #:
|
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Issue Dt:
|
06/17/2014
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Application #:
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13837810
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Filing Dt:
|
03/15/2013
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Title:
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SELF ALIGNED CAPACITOR FABRICATION
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|
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Patent #:
|
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Issue Dt:
|
09/23/2014
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Application #:
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13838378
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Filing Dt:
|
03/15/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
|
VIA INSERTION IN INTEGRATED CIRCUIT (IC) DESIGNS
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Patent #:
|
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Issue Dt:
|
06/23/2015
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Application #:
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13839100
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Filing Dt:
|
03/15/2013
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Publication #:
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Pub Dt:
|
11/28/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
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|
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Patent #:
|
|
Issue Dt:
|
11/18/2014
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Application #:
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13839275
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Filing Dt:
|
03/15/2013
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Publication #:
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Pub Dt:
|
11/28/2013
| | | | |
Title:
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HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS
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|
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Patent #:
|
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Issue Dt:
|
12/09/2014
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Application #:
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13839284
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Filing Dt:
|
03/15/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE USING A PROCESS THAT INCLUDES A MASKING LAYER FORMED BY A DIRECTED SELF-ASSEMBLY PROCESS
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|
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Patent #:
|
|
Issue Dt:
|
10/28/2014
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Application #:
|
13839626
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Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
12/09/2014
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Application #:
|
13839802
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Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
01/05/2016
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Application #:
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13840132
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Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
CAPACITOR USING BARRIER LAYER METALLURGY
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|
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Patent #:
|
|
Issue Dt:
|
12/09/2014
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Application #:
|
13840692
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Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
WRAP AROUND STRESSOR FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13841694
|
Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FORMATION OF CHEMICAL GUIDE PATTERNS FOR DIRECTED SELF-ASSEMBLY LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13842217
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13842564
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13845506
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13846044
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
FREQUENCY QUADRUPLERS AT MILLIMETER-WAVE FREQUENCIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13847695
|
Filing Dt:
|
03/20/2013
|
Publication #:
|
|
Pub Dt:
|
09/25/2014
| | | | |
Title:
|
SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13849764
|
Filing Dt:
|
03/25/2013
|
Title:
|
GENERATION OF DESIGN SHAPES FOR CONFINING STITCH-INDUCED VIA STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13851333
|
Filing Dt:
|
03/27/2013
|
Title:
|
COMPUTATIONAL THERMAL ANALYSIS DURING MICROCHIP DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13851810
|
Filing Dt:
|
03/27/2013
|
Title:
|
INTEGRATED CIRCUITS HAVING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13852084
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
METHODS OF FORMING A BARRIER SYSTEM CONTAINING AN ALLOY OF METALS INTRODUCED INTO THE BARRIER SYSTEM, AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH A BARRIER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13852086
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
FET SEMICONDUCTOR DEVICE WITH LOW RESISTANCE AND ENHANCED METAL FILL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13852103
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13852428
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13852496
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
DOUBLE PATTERNING VIA TRIANGULAR SHAPED SIDEWALL SPACERS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13853088
|
Filing Dt:
|
03/29/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
ANGLED GAS CLUSTER ION BEAM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13853178
|
Filing Dt:
|
03/29/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
THROUGH-SILICON VIA WITH SIDEWALL AIR GAP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13853301
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Filing Dt:
|
03/29/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH METAL LINES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13856542
|
Filing Dt:
|
04/04/2013
|
Publication #:
|
|
Pub Dt:
|
10/09/2014
| | | | |
Title:
|
LOCAL INTERCONNECT TO A PROTECTION DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13859738
|
Filing Dt:
|
04/10/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
METHOD AND SYSTEM FOR DESIGN AND MODELING OF VERTICAL INTERCONNECTS FOR 3DI APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13860603
|
Filing Dt:
|
04/11/2013
|
Title:
|
METHOD OF FORMING A LOW-K DIELECTRIC FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13860753
|
Filing Dt:
|
04/11/2013
|
Publication #:
|
|
Pub Dt:
|
10/16/2014
| | | | |
Title:
|
RELIABLE BACK-SIDE-METAL STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13862901
|
Filing Dt:
|
04/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13863044
|
Filing Dt:
|
04/15/2013
|
Title:
|
METHODS OF REMOVING DUMMY FIN STRUCTURES WHEN FORMING FINFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13863591
|
Filing Dt:
|
04/16/2013
|
Title:
|
VARIABLE POWER RAIL DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13864760
|
Filing Dt:
|
04/17/2013
|
Publication #:
|
|
Pub Dt:
|
10/23/2014
| | | | |
Title:
|
SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13865093
|
Filing Dt:
|
04/17/2013
|
Publication #:
|
|
Pub Dt:
|
10/23/2014
| | | | |
Title:
|
MOBILE DEVICE TRANSACTION METHOD AND SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13865306
|
Filing Dt:
|
04/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2016
|
Application #:
|
13865740
|
Filing Dt:
|
04/18/2013
|
Publication #:
|
|
Pub Dt:
|
10/23/2014
| | | | |
Title:
|
THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13866669
|
Filing Dt:
|
04/19/2013
|
Publication #:
|
|
Pub Dt:
|
10/23/2014
| | | | |
Title:
|
CRACK CONTROL FOR SUBSTRATE SEPARATION
|
|