skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 49 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
Issue Dt:
03/31/2015
Application #:
13782452
Filing Dt:
03/01/2013
Publication #:
Pub Dt:
09/05/2013
Title:
SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN AN ELECTRIC MOTOR
2
Patent #:
Issue Dt:
05/05/2015
Application #:
13782467
Filing Dt:
03/01/2013
Publication #:
Pub Dt:
07/11/2013
Title:
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
3
Patent #:
Issue Dt:
03/24/2015
Application #:
13782537
Filing Dt:
03/01/2013
Publication #:
Pub Dt:
09/04/2014
Title:
SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
4
Patent #:
Issue Dt:
05/27/2014
Application #:
13782826
Filing Dt:
03/01/2013
Title:
METHODS OF MODIFYING A PHYSICAL DESIGN OF AN ELECTRICAL CIRCUIT USED IN THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
5
Patent #:
Issue Dt:
02/18/2014
Application #:
13783388
Filing Dt:
03/03/2013
Title:
SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES
6
Patent #:
Issue Dt:
04/01/2014
Application #:
13783438
Filing Dt:
03/04/2013
Publication #:
Pub Dt:
07/11/2013
Title:
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
7
Patent #:
Issue Dt:
12/16/2014
Application #:
13783562
Filing Dt:
03/04/2013
Publication #:
Pub Dt:
09/04/2014
Title:
DEFECT REMOVAL PROCESS
8
Patent #:
Issue Dt:
03/31/2015
Application #:
13783729
Filing Dt:
03/04/2013
Publication #:
Pub Dt:
07/03/2014
Title:
HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR
9
Patent #:
Issue Dt:
02/03/2015
Application #:
13784220
Filing Dt:
03/04/2013
Publication #:
Pub Dt:
09/04/2014
Title:
CONTACT POWER RAIL
10
Patent #:
Issue Dt:
03/04/2014
Application #:
13785109
Filing Dt:
03/05/2013
Title:
TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
11
Patent #:
Issue Dt:
01/27/2015
Application #:
13785403
Filing Dt:
03/05/2013
Publication #:
Pub Dt:
09/11/2014
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
12
Patent #:
Issue Dt:
03/18/2014
Application #:
13785438
Filing Dt:
03/05/2013
Publication #:
Pub Dt:
07/18/2013
Title:
TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
13
Patent #:
Issue Dt:
02/03/2015
Application #:
13785468
Filing Dt:
03/05/2013
Publication #:
Pub Dt:
09/11/2014
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
14
Patent #:
Issue Dt:
09/02/2014
Application #:
13785602
Filing Dt:
03/05/2013
Publication #:
Pub Dt:
09/11/2014
Title:
MEMORY STATE SENSING BASED ON CELL CAPACITANCE
15
Patent #:
Issue Dt:
09/02/2014
Application #:
13785816
Filing Dt:
03/05/2013
Publication #:
Pub Dt:
09/11/2014
Title:
FRONT SIDE WAFER ID PROCESSING
16
Patent #:
Issue Dt:
03/17/2015
Application #:
13786627
Filing Dt:
03/06/2013
Publication #:
Pub Dt:
09/11/2014
Title:
BARRIER LAYER CONFORMALITY IN COPPER INTERCONNECTS
17
Patent #:
Issue Dt:
10/25/2016
Application #:
13787090
Filing Dt:
03/06/2013
Publication #:
Pub Dt:
09/11/2014
Title:
MULTILAYER PATTERN TRANSFER FOR CHEMICAL GUIDES
18
Patent #:
Issue Dt:
12/17/2013
Application #:
13787384
Filing Dt:
03/06/2013
Title:
METHODS OF SELECTIVELY FORMING RUTHENIUM LINER LAYER
19
Patent #:
Issue Dt:
07/21/2015
Application #:
13788406
Filing Dt:
03/07/2013
Publication #:
Pub Dt:
07/18/2013
Title:
High Density Memory Cells Using Lateral Epitaxy
20
Patent #:
Issue Dt:
03/04/2014
Application #:
13788980
Filing Dt:
03/07/2013
Publication #:
Pub Dt:
07/18/2013
Title:
HIGH CAPACITANCE TRENCH CAPACITOR
21
Patent #:
Issue Dt:
12/16/2014
Application #:
13789018
Filing Dt:
03/07/2013
Publication #:
Pub Dt:
08/01/2013
Title:
REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
22
Patent #:
NONE
Issue Dt:
Application #:
13789966
Filing Dt:
03/08/2013
Publication #:
Pub Dt:
09/11/2014
Title:
METHODS OF REPAIRING DAMAGED INSULATING MATERIALS BY INTRODUCING CARBON INTO THE LAYER OF INSULATING MATERIAL
23
Patent #:
Issue Dt:
03/29/2016
Application #:
13790727
Filing Dt:
03/08/2013
Publication #:
Pub Dt:
09/11/2014
Title:
SCATTERING ENHANCED THIN ABSORBER FOR EUV RETICLE AND A METHOD OF MAKING
24
Patent #:
Issue Dt:
06/16/2015
Application #:
13791520
Filing Dt:
03/08/2013
Publication #:
Pub Dt:
07/25/2013
Title:
SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
25
Patent #:
Issue Dt:
11/18/2014
Application #:
13791545
Filing Dt:
03/08/2013
Publication #:
Pub Dt:
07/25/2013
Title:
STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES
26
Patent #:
Issue Dt:
08/09/2016
Application #:
13792730
Filing Dt:
03/11/2013
Publication #:
Pub Dt:
09/11/2014
Title:
CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH
27
Patent #:
Issue Dt:
07/01/2014
Application #:
13792933
Filing Dt:
03/11/2013
Publication #:
Pub Dt:
07/25/2013
Title:
HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
28
Patent #:
Issue Dt:
04/14/2015
Application #:
13792950
Filing Dt:
03/11/2013
Publication #:
Pub Dt:
09/11/2014
Title:
TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS
29
Patent #:
Issue Dt:
08/26/2014
Application #:
13793082
Filing Dt:
03/11/2013
Publication #:
Pub Dt:
09/11/2014
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING AN IMPLANTATION OF IONS INTO A LAYER OF SPACER MATERIAL
30
Patent #:
Issue Dt:
07/08/2014
Application #:
13793363
Filing Dt:
03/11/2013
Publication #:
Pub Dt:
07/25/2013
Title:
HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
31
Patent #:
Issue Dt:
09/09/2014
Application #:
13795030
Filing Dt:
03/12/2013
Publication #:
Pub Dt:
07/25/2013
Title:
FLUID DISTRIBUTION METHOD FACILITATING COOLING OF ELECTRONICS RACK(S) AND SIMULATING HEATED AIRFLOW EXHAUST OF ELECTRONICS RACK(S)
32
Patent #:
Issue Dt:
06/10/2014
Application #:
13795198
Filing Dt:
03/12/2013
Title:
HIERARCHICAL LAYOUT VERSUS SCHEMATIC (LVS) COMPARISON WITH EXTRANEOUS DEVICE ELIMINATION
33
Patent #:
Issue Dt:
06/03/2014
Application #:
13796154
Filing Dt:
03/12/2013
Publication #:
Pub Dt:
07/25/2013
Title:
REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
34
Patent #:
Issue Dt:
09/09/2014
Application #:
13796259
Filing Dt:
03/12/2013
Publication #:
Pub Dt:
07/25/2013
Title:
DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS
35
Patent #:
Issue Dt:
12/02/2014
Application #:
13796278
Filing Dt:
03/12/2013
Publication #:
Pub Dt:
09/18/2014
Title:
NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS
36
Patent #:
Issue Dt:
07/15/2014
Application #:
13796418
Filing Dt:
03/12/2013
Title:
NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH EPITIXIALLY GROWN SOURCE AND DRAIN
37
Patent #:
Issue Dt:
09/23/2014
Application #:
13797001
Filing Dt:
03/12/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE
38
Patent #:
Issue Dt:
01/20/2015
Application #:
13797117
Filing Dt:
03/12/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING FINFET DEVICES WITH A SHARED GATE STRUCTURE
39
Patent #:
Issue Dt:
07/21/2015
Application #:
13798446
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
07/25/2013
Title:
HIGH DENSITY MULTI-ELECTRODE ARRAY
40
Patent #:
NONE
Issue Dt:
Application #:
13798503
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES BY FORMING A REGION THAT INCLUDES A SCHOTTKY BARRIER LOWERING MATERIAL
41
Patent #:
Issue Dt:
10/07/2014
Application #:
13798616
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL STRUCTURE BY PERFORMING AN ANNEAL PROCESS
42
Patent #:
Issue Dt:
08/19/2014
Application #:
13799148
Filing Dt:
03/13/2013
Title:
THERMALLY ASSISTED MRAM WITH MULTILAYER STRAP AND TOP CONTACT FOR LOW THERMAL CONDUCTIVITY
43
Patent #:
Issue Dt:
02/24/2015
Application #:
13799539
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT)
44
Patent #:
Issue Dt:
02/10/2015
Application #:
13799741
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES BASED ON AN AMORPHIZATION PROCESS AND A HEAT TREATMENT
45
Patent #:
Issue Dt:
09/30/2014
Application #:
13799814
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
SEMICONDUCTOR DEVICE HAVING CONTROLLED FINAL METAL CRITICAL DIMENSION
46
Patent #:
Issue Dt:
12/22/2015
Application #:
13800091
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FABRICATING BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE
47
Patent #:
Issue Dt:
09/16/2014
Application #:
13800966
Filing Dt:
03/13/2013
Publication #:
Pub Dt:
09/18/2014
Title:
PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS
48
Patent #:
Issue Dt:
12/23/2014
Application #:
13803048
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
09/18/2014
Title:
STITCH INSERTION FOR REDUCING COLOR DENSITY DIFFERENCES IN DOUBLE PATTERNING TECHNOLOGY (DPT)
49
Patent #:
Issue Dt:
01/13/2015
Application #:
13803281
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
08/08/2013
Title:
HIGHLY SCALABLE TRENCH CAPACITOR
50
Patent #:
Issue Dt:
10/01/2013
Application #:
13826830
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
08/08/2013
Title:
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING
51
Patent #:
Issue Dt:
02/25/2014
Application #:
13826874
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
08/08/2013
Title:
METHOD FOR FORMING SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP
52
Patent #:
Issue Dt:
03/03/2015
Application #:
13827786
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A METAL-INSULATOR-METAL CAPACITOR
53
Patent #:
Issue Dt:
08/05/2014
Application #:
13828276
Filing Dt:
03/14/2013
Title:
DOPING OF FINFET STRUCTURES
54
Patent #:
Issue Dt:
04/21/2015
Application #:
13832442
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METAL LAYER ENABLING DIRECTED SELF-ASSEMBLY SEMICONDUCTOR LAYOUT DESIGNS
55
Patent #:
Issue Dt:
05/13/2014
Application #:
13832929
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
08/22/2013
Title:
LOW HARMONIC RF SWITCH IN SOI
56
Patent #:
Issue Dt:
08/05/2014
Application #:
13833713
Filing Dt:
03/15/2013
Title:
FACILITATING THE DESIGN OF A CLOCK GRID IN AN INTEGRATED CIRCUIT
57
Patent #:
Issue Dt:
02/17/2015
Application #:
13834058
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE
58
Patent #:
Issue Dt:
06/17/2014
Application #:
13834410
Filing Dt:
03/15/2013
Title:
METHODS OF FORMING ISOLATION STRUCTURES AND FINS ON A FINFET SEMICONDUCTOR DEVICE
59
Patent #:
Issue Dt:
03/01/2016
Application #:
13834608
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK
60
Patent #:
Issue Dt:
10/28/2014
Application #:
13834946
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING TRENCH/HOLE TYPE FEATURES IN A LAYER OF MATERIAL OF AN INTEGRATED CIRCUIT PRODUCT
61
Patent #:
Issue Dt:
12/02/2014
Application #:
13836057
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN
62
Patent #:
Issue Dt:
07/29/2014
Application #:
13837624
Filing Dt:
03/15/2013
Title:
VIA NON-STANDARD LIMITING PARAMETERS
63
Patent #:
Issue Dt:
06/17/2014
Application #:
13837810
Filing Dt:
03/15/2013
Title:
SELF ALIGNED CAPACITOR FABRICATION
64
Patent #:
Issue Dt:
09/23/2014
Application #:
13838378
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
VIA INSERTION IN INTEGRATED CIRCUIT (IC) DESIGNS
65
Patent #:
Issue Dt:
06/23/2015
Application #:
13839100
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
11/28/2013
Title:
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
66
Patent #:
Issue Dt:
11/18/2014
Application #:
13839275
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
11/28/2013
Title:
HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS
67
Patent #:
Issue Dt:
12/09/2014
Application #:
13839284
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE USING A PROCESS THAT INCLUDES A MASKING LAYER FORMED BY A DIRECTED SELF-ASSEMBLY PROCESS
68
Patent #:
Issue Dt:
10/28/2014
Application #:
13839626
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
69
Patent #:
Issue Dt:
12/09/2014
Application #:
13839802
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
70
Patent #:
Issue Dt:
01/05/2016
Application #:
13840132
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
CAPACITOR USING BARRIER LAYER METALLURGY
71
Patent #:
Issue Dt:
12/09/2014
Application #:
13840692
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
WRAP AROUND STRESSOR FORMATION
72
Patent #:
Issue Dt:
10/07/2014
Application #:
13841694
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
09/18/2014
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FORMATION OF CHEMICAL GUIDE PATTERNS FOR DIRECTED SELF-ASSEMBLY LITHOGRAPHY
73
Patent #:
Issue Dt:
08/19/2014
Application #:
13842217
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
08/22/2013
Title:
REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
74
Patent #:
Issue Dt:
02/25/2014
Application #:
13842564
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
08/29/2013
Title:
MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS
75
Patent #:
Issue Dt:
06/16/2015
Application #:
13845506
Filing Dt:
03/18/2013
Publication #:
Pub Dt:
09/05/2013
Title:
EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR
76
Patent #:
Issue Dt:
09/23/2014
Application #:
13846044
Filing Dt:
03/18/2013
Publication #:
Pub Dt:
09/18/2014
Title:
FREQUENCY QUADRUPLERS AT MILLIMETER-WAVE FREQUENCIES
77
Patent #:
Issue Dt:
01/06/2015
Application #:
13847695
Filing Dt:
03/20/2013
Publication #:
Pub Dt:
09/25/2014
Title:
SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS
78
Patent #:
Issue Dt:
08/12/2014
Application #:
13849764
Filing Dt:
03/25/2013
Title:
GENERATION OF DESIGN SHAPES FOR CONFINING STITCH-INDUCED VIA STRUCTURES
79
Patent #:
Issue Dt:
09/02/2014
Application #:
13851333
Filing Dt:
03/27/2013
Title:
COMPUTATIONAL THERMAL ANALYSIS DURING MICROCHIP DESIGN
80
Patent #:
Issue Dt:
05/13/2014
Application #:
13851810
Filing Dt:
03/27/2013
Title:
INTEGRATED CIRCUITS HAVING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME
81
Patent #:
Issue Dt:
11/04/2014
Application #:
13852084
Filing Dt:
03/28/2013
Publication #:
Pub Dt:
10/02/2014
Title:
METHODS OF FORMING A BARRIER SYSTEM CONTAINING AN ALLOY OF METALS INTRODUCED INTO THE BARRIER SYSTEM, AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH A BARRIER SYSTEM
82
Patent #:
Issue Dt:
06/16/2015
Application #:
13852086
Filing Dt:
03/28/2013
Publication #:
Pub Dt:
10/02/2014
Title:
FET SEMICONDUCTOR DEVICE WITH LOW RESISTANCE AND ENHANCED METAL FILL
83
Patent #:
Issue Dt:
11/04/2014
Application #:
13852103
Filing Dt:
03/28/2013
Publication #:
Pub Dt:
08/15/2013
Title:
INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
84
Patent #:
Issue Dt:
01/07/2014
Application #:
13852428
Filing Dt:
03/28/2013
Publication #:
Pub Dt:
08/15/2013
Title:
BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION
85
Patent #:
Issue Dt:
03/03/2015
Application #:
13852496
Filing Dt:
03/28/2013
Publication #:
Pub Dt:
10/02/2014
Title:
DOUBLE PATTERNING VIA TRIANGULAR SHAPED SIDEWALL SPACERS
86
Patent #:
NONE
Issue Dt:
Application #:
13853088
Filing Dt:
03/29/2013
Publication #:
Pub Dt:
10/02/2014
Title:
ANGLED GAS CLUSTER ION BEAM
87
Patent #:
Issue Dt:
11/04/2014
Application #:
13853178
Filing Dt:
03/29/2013
Publication #:
Pub Dt:
09/18/2014
Title:
THROUGH-SILICON VIA WITH SIDEWALL AIR GAP
88
Patent #:
Issue Dt:
07/21/2015
Application #:
13853301
Filing Dt:
03/29/2013
Publication #:
Pub Dt:
10/02/2014
Title:
SEMICONDUCTOR STRUCTURES WITH METAL LINES
89
Patent #:
NONE
Issue Dt:
Application #:
13856542
Filing Dt:
04/04/2013
Publication #:
Pub Dt:
10/09/2014
Title:
LOCAL INTERCONNECT TO A PROTECTION DIODE
90
Patent #:
Issue Dt:
07/29/2014
Application #:
13859738
Filing Dt:
04/10/2013
Publication #:
Pub Dt:
11/28/2013
Title:
METHOD AND SYSTEM FOR DESIGN AND MODELING OF VERTICAL INTERCONNECTS FOR 3DI APPLICATIONS
91
Patent #:
Issue Dt:
05/06/2014
Application #:
13860603
Filing Dt:
04/11/2013
Title:
METHOD OF FORMING A LOW-K DIELECTRIC FILM
92
Patent #:
Issue Dt:
06/16/2015
Application #:
13860753
Filing Dt:
04/11/2013
Publication #:
Pub Dt:
10/16/2014
Title:
RELIABLE BACK-SIDE-METAL STRUCTURE
93
Patent #:
Issue Dt:
11/26/2013
Application #:
13862901
Filing Dt:
04/15/2013
Publication #:
Pub Dt:
09/05/2013
Title:
SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE
94
Patent #:
Issue Dt:
04/22/2014
Application #:
13863044
Filing Dt:
04/15/2013
Title:
METHODS OF REMOVING DUMMY FIN STRUCTURES WHEN FORMING FINFET DEVICES
95
Patent #:
Issue Dt:
07/22/2014
Application #:
13863591
Filing Dt:
04/16/2013
Title:
VARIABLE POWER RAIL DESIGN
96
Patent #:
Issue Dt:
06/02/2015
Application #:
13864760
Filing Dt:
04/17/2013
Publication #:
Pub Dt:
10/23/2014
Title:
SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS
97
Patent #:
NONE
Issue Dt:
Application #:
13865093
Filing Dt:
04/17/2013
Publication #:
Pub Dt:
10/23/2014
Title:
MOBILE DEVICE TRANSACTION METHOD AND SYSTEM
98
Patent #:
Issue Dt:
07/08/2014
Application #:
13865306
Filing Dt:
04/18/2013
Publication #:
Pub Dt:
09/05/2013
Title:
EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION
99
Patent #:
Issue Dt:
01/26/2016
Application #:
13865740
Filing Dt:
04/18/2013
Publication #:
Pub Dt:
10/23/2014
Title:
THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES
100
Patent #:
Issue Dt:
02/03/2015
Application #:
13866669
Filing Dt:
04/19/2013
Publication #:
Pub Dt:
10/23/2014
Title:
CRACK CONTROL FOR SUBSTRATE SEPARATION
Assignor
1
Exec Dt:
10/22/2020
Assignee
1
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

Search Results as of: 05/24/2024 08:39 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT