|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
10984373
|
Filing Dt:
|
11/08/2004
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
MEMORY SYSTEM HAVING MULTIPLE ADDRESS ALLOCATION FORMATS AND METHOD FOR USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10985573
|
Filing Dt:
|
11/10/2004
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
Title:
|
INTERMEDIATE SEMICONDUCTOR DEVICE HAVING NITROGEN CONCENTRATION PROFILE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10985960
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
ADVANCED BARRIER LINER FORMATION FOR VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
10988417
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
MEMORY REUSE FOR MULTIPLE ENDPOINTS IN USB DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10989530
|
Filing Dt:
|
11/16/2004
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
Title:
|
METHOD OF MANUFACTURING A MULTILAYERED DOPED CONDUCTOR FOR A CONTACT IN AN INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
10989948
|
Filing Dt:
|
11/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
PROGRAMMABLE POWER TRANSITION COUNTER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10990586
|
Filing Dt:
|
11/17/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
MERGED MOS-BIPOLAR CAPACITOR MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10990713
|
Filing Dt:
|
11/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
MERGED MOS-BIPOLAR CAPACITOR MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10991876
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
DOUBLE DENSITY MRAM WITH PLANAR PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10992052
|
Filing Dt:
|
11/18/2004
|
Title:
|
STATE SAVE-ON-POWER-DOWN USING GMR NON-VOLATILE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10992384
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
METHOD OF ESTABLISHING NON-PERMANENT ELECTRICAL CONNECTION BETWEEN AN INTEGRATED CIRCUIT DEVICE LEAD ELEMENT AND A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10992424
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
Title:
|
DEVICE FOR ESTABLISHING NON-PERMANENT ELECTRICAL CONNECTION BETWEEN AN INTEGRATED CIRCUIT DEVICE LEAD ELEMENT AND A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2007
|
Application #:
|
10992984
|
Filing Dt:
|
11/19/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
METHODS OF FORMING MAGNETIC SHIELDING FOR A THIN-FILM MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
10993692
|
Filing Dt:
|
11/19/2004
|
Title:
|
STORAGE CAPACITY STATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10994995
|
Filing Dt:
|
11/22/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
METHODS OF FABRICATING A VIA-IN-PAD WITH OFF-CENTER GEOMETRY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10995839
|
Filing Dt:
|
11/23/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
SCALABLE INTEGRATED LOGIC AND NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10998380
|
Filing Dt:
|
11/29/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE WITH MULTI LAYERED LEADFRAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10999435
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
Title:
|
MULTICHIP WAFER LEVEL PACKAGES AND COMPUTING SYSTEMS INCORPORATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10999751
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
RESET INITIALIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11000786
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
METHODS OF FORMING FIELD EFFECT TRANSISTOR GATE LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11000809
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
METHOD OF FORMING A FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11000825
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD FOR OBTAINING EXTREME SELECTIVITY OF METAL NITRIDES AND METAL OXIDES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
11001145
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD OF FORMING FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
11001306
|
Filing Dt:
|
12/02/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
DIFFERENTIAL NEGATIVE RESISTANCE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11001930
|
Filing Dt:
|
12/02/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT COOLING SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
11003117
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
SKEW TOLERANT HIGH-SPEED DIGITAL PHASE DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11003133
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
Title:
|
ELECTRICAL COUPLING STACK AND PROCESSES FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11003138
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
07/14/2005
| | | | |
Title:
|
DOPANT BARRIER FOR DOPED GLASS IN MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11003275
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
METHODS OF FORMING INTEGRATED CIRCUITRY, METHODS OF FORMING MEMORY CIRCUITRY, AND METHODS OF FORMING FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11003502
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR ERASING MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
11003547
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION DURING EXTENDED REFRESH PERIODS OF DYNAMIC RANDOM ACCESS MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
11003642
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
CAPACITOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
11004069
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
NON-VOLATILE MEMORY WITH TEST ROWS FOR DISTURB DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
11004454
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
ERASE BLOCK DATA SPLITTING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11004702
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
METHOD FOR IMPROVED DEPOSITION OF DIELECTRIC MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
11005712
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
THREE-DIMENSIONAL PHOTONIC CRYSTAL WAVEGUIDE STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11005909
|
Filing Dt:
|
12/06/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
NOR FLASH MEMORY CELL WITH HIGH STORAGE DENSITY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
11006045
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
APPARATUS AND METHOD FOR DYNAMICALLY REPAIRING A SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
11006312
|
Filing Dt:
|
12/06/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
NOR FLASH MEMORY CELL WITH HIGH STORAGE DENSITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
11006364
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
CURRENT DIFFERENTIAL BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
11007138
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
Title:
|
INTERCONNECTING CONDUCTIVE LAYERS OF MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
11008586
|
Filing Dt:
|
12/09/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR A CONTINUOUS READ COMMAND IN AN EXTENDED MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11008588
|
Filing Dt:
|
12/09/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
SERIAL MEMORY COMPRISING MEANS FOR PROTECTING AN EXTENDED MEMORY ARRAY DURING A WRITE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11009665
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
TRENCH INSULATION STRUCTURES INCLUDING AN OXIDE LINER THAT IS THINNER ALONG THE WALLS OF THE TRENCH THAN ALONG THE BASE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11009687
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
METHOD FOR REDUCING DEFECTS AFTER A METAL ETCHING IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
11010529
|
Filing Dt:
|
12/13/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
LANTHANUM HAFNIUM OXIDE DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
11010671
|
Filing Dt:
|
12/13/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
MAGNETIC NON-VOLATILE MEMORY COIL LAYOUT ARCHITECTURE AND PROCESS INTEGRATION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11010752
|
Filing Dt:
|
12/13/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHODS OF REDUCING FLOATING BODY EFFECT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11010951
|
Filing Dt:
|
12/13/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
ANNULAR GATE AND TECHNIQUE FOR FABRICATING AN ANNULAR GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11012533
|
Filing Dt:
|
12/15/2004
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
VOLTAGE TRANSLATING CONTROL STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11012584
|
Filing Dt:
|
12/14/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
APPARATUS AND METHOD FOR DEPOSITING AND REFLOWING SOLDER PASTE ON A MICROELECTRONIC WORKPIECE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11012693
|
Filing Dt:
|
12/15/2004
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
RESET RAMP CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11012712
|
Filing Dt:
|
12/15/2004
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
RESET CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11013123
|
Filing Dt:
|
12/15/2004
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
ESD BONDING PAD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11013210
|
Filing Dt:
|
12/14/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
LIGHTLY DOPED DRAIN MOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
11013377
|
Filing Dt:
|
12/17/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
SILICON-ON-INSULATOR COMPRISING INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11013487
|
Filing Dt:
|
12/16/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
SEMICONDUCTOR/PRINTED CIRCUIT BOARD ASSEMBLY, AND COMPUTER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
11015703
|
Filing Dt:
|
12/17/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
REDUCED POWER REDUNDANCY ADDRESS DECODER AND COMPARISON CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11015967
|
Filing Dt:
|
12/17/2004
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING A CONNECTION MATRIX
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11016197
|
Filing Dt:
|
12/17/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
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Title:
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CASCADED CONNECTION MATRICES IN A DISTRIBUTED CROSS-CONNECTION SYSTEM
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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11018366
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Filing Dt:
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12/22/2004
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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SMALL ELECTRODE FOR RESISTANCE VARIABLE DEVICES
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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11018580
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Filing Dt:
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12/21/2004
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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BOOSTED SUBSTRATE/TUB PROGRAMMING FOR FLASH MEMORIES
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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11018810
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Filing Dt:
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12/21/2004
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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DUTY CYCLE DISTORTION COMPENSATION FOR THE DATA OUTPUT OF A MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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11018848
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Filing Dt:
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12/20/2004
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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SEMICONDUCTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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11020757
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Filing Dt:
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12/23/2004
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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LOW VOLTAGE CMOS DIFFERENTIAL AMPLIFIER
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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11021175
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Filing Dt:
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12/23/2004
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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TECHNIQUES FOR PACKAGING MULTIPLE DEVICE COMPONENTS
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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11021639
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Filing Dt:
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12/22/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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DOUBLE-SIDED CONTAINER CAPACITORS USING A SACRIFICIAL LAYER
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Patent #:
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Issue Dt:
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03/17/2009
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Application #:
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11022212
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Filing Dt:
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12/23/2004
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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SCALABLE TRACEBACK TECHNIQUE FOR CHANNEL DECODER
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11023719
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Filing Dt:
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12/28/2004
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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METHOD OF FABRICATING MEMORY TRANSISTOR
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Patent #:
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Issue Dt:
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01/23/2007
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Application #:
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11024106
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Filing Dt:
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12/28/2004
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Publication #:
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Pub Dt:
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07/14/2005
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Title:
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ETCH STOP LAYER IN POLY-METAL STRUCTURES
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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11024956
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Filing Dt:
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12/29/2004
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Publication #:
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Pub Dt:
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07/20/2006
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Title:
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SYSTEMS AND METHODS FOR EFFICIENT OPERATIONS OF COMPONENTS IN A WIRELESS COMMUNICATIONS DEVICE
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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11025420
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Filing Dt:
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12/28/2004
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Publication #:
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Pub Dt:
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07/13/2006
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Title:
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TECHNIQUES FOR TRANSMITTING AND RECEIVING TRAFFIC OVER ADVANCED SWITCHING COMPATIBLE SWITCH FABRICS
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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11025913
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Filing Dt:
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01/03/2005
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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SELF-ALIGNED, LOW-RESISTANCE, EFFICIENT MEMORY ARRAY
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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11025960
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Filing Dt:
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01/03/2005
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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WELL FOR CMOS IMAGER
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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11027343
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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SYNCHRONOUS CLOCK GENERATOR INCLUDING DUTY CYCLE CORRECTION
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11027443
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES AND MICROELECTRONIC WORKPIECES FORMED USING SUCH METHODS
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Patent #:
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Issue Dt:
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08/12/2008
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Application #:
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11027784
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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SECURE MEMORY CONTROLLER
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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11027913
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Filing Dt:
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12/28/2004
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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SECURE CONTROLLER FOR BLOCK ORIENTED STORAGE
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11028090
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Filing Dt:
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01/03/2005
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Publication #:
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Pub Dt:
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06/02/2005
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Title:
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APPARATUS FOR IMPROVING STABILITY AND LOCK TIME FOR SYNCHRONOUS CIRCUITS
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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11028361
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Filing Dt:
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01/03/2005
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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MODULE ASSEMBLY AND METHOD FOR STACKED BGA PACKAGES
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Patent #:
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Issue Dt:
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02/03/2009
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Application #:
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11028374
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Filing Dt:
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01/03/2005
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Publication #:
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Pub Dt:
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06/02/2005
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Title:
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METHOD OF MAKING MULTICHIP WAFER LEVEL PACKAGES AND COMPUTING SYSTEMS INCORPORATING SAME
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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11028892
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Filing Dt:
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01/03/2005
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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METHODS OF FABRICATING INTERCONNECTS INCLUDING DEPOSITING A FIRST MATERIAL IN THE INTERCONNECT WITH A THICKNESS OF ANGSTROMS AND A LOW TEMPERATURE FOR SEMICONDUCTOR COMPONENTS
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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11028918
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Filing Dt:
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01/03/2005
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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METHODS OF FABRICATING INTERCONNECTS FOR SEMICONDUCTOR COMPONENTS INCLUDING A THROUGH HOLE ENTIRELY THROUGH THE COMPONENT AND FORMING A METAL NITRIDE INCLUDING SEPARATE PRECURSOR CYCLES
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Patent #:
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Issue Dt:
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07/14/2009
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Application #:
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11029757
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Filing Dt:
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01/05/2005
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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ATOMIC LAYER DEPOSITED HAFNIUM TANTALUM OXIDE DIELECTRICS
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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11029981
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Filing Dt:
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01/05/2005
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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READING PHASE CHANGE MEMORIES TO REDUCE READ DISTURBS
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Patent #:
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Issue Dt:
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01/22/2008
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Application #:
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11030696
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Filing Dt:
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01/06/2005
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Publication #:
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Pub Dt:
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06/02/2005
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Title:
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SEMICONDUCTOR DEVICE PRECURSOR STRUCTURES TO A DOUBLE-SIDED CAPACITOR OR A CONTACT
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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11030772
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Filing Dt:
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01/06/2005
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Publication #:
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Pub Dt:
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07/07/2005
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Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR INTERCONNECT HAVING CONDUCTIVE SPRING CONTACTS
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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11031265
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Filing Dt:
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01/07/2005
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Publication #:
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Pub Dt:
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06/16/2005
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Title:
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CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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11031289
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Filing Dt:
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01/07/2005
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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LANTHANIDE DOPED TIOX DIELECTRIC FILMS BY PLASMA OXIDATION
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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11031961
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Filing Dt:
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01/07/2005
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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PULSED WRITE TECHNIQUES FOR MAGNETO-RESISTIVE MEMORIES
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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11032975
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Filing Dt:
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01/10/2005
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Publication #:
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Pub Dt:
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07/13/2006
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Title:
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INTERCONNECT STRUCTURES WITH BOND-PADS AND METHODS OF FORMING BUMP SITES ON BOND-PADS
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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11033525
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Filing Dt:
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01/12/2005
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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REVERSE METAL PROCESS FOR CREATING A METAL SILICIDE TRANSISTOR GATE STRUCTURE
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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11033873
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Filing Dt:
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01/13/2005
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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METHODS OF OPERATING AND FORMING CHALCOGENIDE GLASS CONSTANT CURRENT DEVICES
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Patent #:
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Issue Dt:
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08/04/2009
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Application #:
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11034165
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Filing Dt:
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01/12/2005
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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CMOS IMAGER WITH INTEGRATED NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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11034751
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Filing Dt:
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01/14/2005
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Publication #:
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Pub Dt:
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07/07/2005
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Title:
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METHOD OF FORMING HIGH GAIN, LOW NOISE, PHOTODIODE SENSOR FOR IMAGE SENSORS
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11035013
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Filing Dt:
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01/13/2005
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Publication #:
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Pub Dt:
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07/13/2006
| | | | |
Title:
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OPTIMIZING WRITE/ERASE OPERATIONS IN MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11035298
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Filing Dt:
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01/12/2005
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Publication #:
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Pub Dt:
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03/09/2006
| | | | |
Title:
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METHODS OF FORMING A LAYER COMPRISING EPITAXIAL SILICON, AND METHODS OF FORMING FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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11036163
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Filing Dt:
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01/14/2005
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Publication #:
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Pub Dt:
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07/20/2006
| | | | |
Title:
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MEMORY ARRAY BURIED DIGIT LINE
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11036179
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Filing Dt:
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01/14/2005
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Publication #:
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Pub Dt:
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07/20/2006
| | | | |
Title:
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CONTROLLING OPERATION OF FLASH MEMORIES
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Patent #:
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Issue Dt:
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09/30/2008
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Application #:
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11036296
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Filing Dt:
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01/14/2005
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Publication #:
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Pub Dt:
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07/21/2005
| | | | |
Title:
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LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN COTIO3 GATE DIELECTRICS
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