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Reel/Frame:051028/0001   Pages: 834
Recorded: 11/12/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 16529
Page 55 of 166
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1
Patent #:
7390756
Issue Dt:
06/24/2008
Application #:
11117121
Filing Dt:
04/28/2005
Publication #:
US20060244100
Pub Dt:
11/02/2006
Title:
ATOMIC LAYER DEPOSITED ZIRCONIUM SILICON OXIDE FILMS
2
Patent #:
7370166
Issue Dt:
05/06/2008
Application #:
11118959
Filing Dt:
04/29/2005
Title:
SECURE PORTABLE STORAGE DEVICE
3
Patent #:
7309889
Issue Dt:
12/18/2007
Application #:
11119127
Filing Dt:
04/29/2005
Publication #:
US20050191766
Pub Dt:
09/01/2005
Title:
CONSTRUCTIONS COMPRISING PEROVSKITE-TYPE DIELECTRIC
4
Patent #:
7268402
Issue Dt:
09/11/2007
Application #:
11119128
Filing Dt:
04/29/2005
Publication #:
US20050202648
Pub Dt:
09/15/2005
Title:
MEMORY CELL WITH TRENCH-ISOLATED TRANSISTOR INCLUDING FIRST AND SECOND ISOLATION TRENCHES
5
Patent #:
8103805
Issue Dt:
01/24/2012
Application #:
11119321
Filing Dt:
04/29/2005
Publication #:
US20060291280
Pub Dt:
12/28/2006
Title:
CONFIGURATION FINALIZATION ON FIRST VALID NAND COMMAND
6
Patent #:
7271092
Issue Dt:
09/18/2007
Application #:
11119370
Filing Dt:
04/29/2005
Publication #:
US20050266624
Pub Dt:
12/01/2005
Title:
BORON INCORPORATED DIFFUSION BARRIER MATERIAL
7
Patent #:
7480762
Issue Dt:
01/20/2009
Application #:
11119589
Filing Dt:
05/02/2005
Publication #:
US20050190599
Pub Dt:
09/01/2005
Title:
ERASE BLOCK DATA SPLITTING
8
Patent #:
7254062
Issue Dt:
08/07/2007
Application #:
11120766
Filing Dt:
05/03/2005
Publication #:
US20050249022
Pub Dt:
11/10/2005
Title:
CIRCUIT FOR SELECTING/DESELECTING A BITLINE OF A NON-VOLATILE MEMORY
9
Patent #:
7366021
Issue Dt:
04/29/2008
Application #:
11121114
Filing Dt:
05/04/2005
Publication #:
US20060250853
Pub Dt:
11/09/2006
Title:
METHOD AND APPARATUS FOR SENSING FLASH MEMORY USING DELTA SIGMA MODULATION
10
Patent #:
7851798
Issue Dt:
12/14/2010
Application #:
11121119
Filing Dt:
05/04/2005
Publication #:
US20060249731
Pub Dt:
11/09/2006
Title:
METHOD AND APPARATUS FOR DARK CURRENT AND BLOOMING SUPPRESSION IN 4T CMOS IMAGER PIXEL
11
Patent #:
7386689
Issue Dt:
06/10/2008
Application #:
11121172
Filing Dt:
05/04/2005
Publication #:
US20050262288
Pub Dt:
11/24/2005
Title:
METHOD AND APPARATUS FOR CONNECTING A MASSIVELY PARALLEL PROCESSOR ARRAY TO A MEMORY ARRAY IN A BIT SERIAL MANNER
12
Patent #:
7389581
Issue Dt:
06/24/2008
Application #:
11121276
Filing Dt:
05/03/2005
Publication #:
US20050202576
Pub Dt:
09/15/2005
Title:
METHOD OF FORMING COMPLIANT CONTACT STRUCTURES
13
Patent #:
7177217
Issue Dt:
02/13/2007
Application #:
11121615
Filing Dt:
05/04/2005
Publication #:
US20050248982
Pub Dt:
11/10/2005
Title:
METHOD AND CIRCUIT FOR VERIFYING AND EVENTUALLY SUBSTITUTING DEFECTIVE REFERENCE CELLS OF A MEMORY
14
Patent #:
7757061
Issue Dt:
07/13/2010
Application #:
11121868
Filing Dt:
05/03/2005
Publication #:
US20060265556
Pub Dt:
11/23/2006
Title:
SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
15
Patent #:
7268023
Issue Dt:
09/11/2007
Application #:
11122362
Filing Dt:
05/05/2005
Publication #:
US20060252187
Pub Dt:
11/09/2006
Title:
METHOD OF FORMING A PSEUDO SOI SUBSTRATE AND SEMICONDUCTOR DEVICES
16
Patent #:
7402908
Issue Dt:
07/22/2008
Application #:
11122409
Filing Dt:
05/05/2005
Publication #:
US20060252225
Pub Dt:
11/09/2006
Title:
INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES
17
Patent #:
7230848
Issue Dt:
06/12/2007
Application #:
11122764
Filing Dt:
05/05/2005
Publication #:
US20050255647
Pub Dt:
11/17/2005
Title:
VERTICAL NROM HAVING A STORAGE DENSITY OF 1 BIT PER 1F2
18
Patent #:
7372092
Issue Dt:
05/13/2008
Application #:
11122854
Filing Dt:
05/05/2005
Publication #:
US20060249776
Pub Dt:
11/09/2006
Title:
MEMORY CELL, DEVICE, AND SYSTEM
19
Patent #:
7273779
Issue Dt:
09/25/2007
Application #:
11122929
Filing Dt:
05/04/2005
Publication #:
US20050208729
Pub Dt:
09/22/2005
Title:
METHOD OF FORMING A DOUBLE-SIDED CAPACITOR
20
Patent #:
7136307
Issue Dt:
11/14/2006
Application #:
11123184
Filing Dt:
05/06/2005
Publication #:
US20050195655
Pub Dt:
09/08/2005
Title:
WRITE STATE MACHINE ARCHITECTURE FOR FLASH MEMORY INTERNAL INSTRUCTIONS
21
Patent #:
7208839
Issue Dt:
04/24/2007
Application #:
11123466
Filing Dt:
05/06/2005
Publication #:
US20050200008
Pub Dt:
09/15/2005
Title:
SEMICONDUCTOR COMPONENT ASSEMBLIES HAVING INTERCONNECTS
22
Patent #:
7176065
Issue Dt:
02/13/2007
Application #:
11123916
Filing Dt:
05/06/2005
Publication #:
US20050190620
Pub Dt:
09/01/2005
Title:
MAGNETIC TUNNELING JUNCTION ANTIFUSE DEVICE
23
Patent #:
7042010
Issue Dt:
05/09/2006
Application #:
11124068
Filing Dt:
05/06/2005
Publication #:
US20050205933
Pub Dt:
09/22/2005
Title:
INTERMEDIATE SEMICONDUCTOR DEVICE HAVING ACTIVATED OXIDE-BASED LAYER FOR ELECTROLESS PLATING
24
Patent #:
7355464
Issue Dt:
04/08/2008
Application #:
11124743
Filing Dt:
05/09/2005
Publication #:
US20060250171
Pub Dt:
11/09/2006
Title:
APPARATUS AND METHOD FOR CONTROLLING A DELAY- OR PHASE-LOCKED LOOP AS A FUNCTION OF LOOP FREQUENCY
25
Patent #:
7457978
Issue Dt:
11/25/2008
Application #:
11124744
Filing Dt:
05/09/2005
Publication #:
US20060253721
Pub Dt:
11/09/2006
Title:
ADJUSTABLE BYTE LANE OFFSET FOR MEMORY MODULE TO REDUCE SKEW
26
Patent #:
7075856
Issue Dt:
07/11/2006
Application #:
11124784
Filing Dt:
05/09/2005
Publication #:
US20050206420
Pub Dt:
09/22/2005
Title:
APPARATUS FOR LATENCY SPECIFIC DUTY CYCLE CORRECTION
27
Patent #:
7368696
Issue Dt:
05/06/2008
Application #:
11125096
Filing Dt:
05/10/2005
Publication #:
US20060231734
Pub Dt:
10/19/2006
Title:
GENERATION AND STORAGE OF COLUMN OFFSETS FOR A COLUMN PARALLEL IMAGE SENSOR
28
Patent #:
7872682
Issue Dt:
01/18/2011
Application #:
11125097
Filing Dt:
05/10/2005
Publication #:
US20060256220
Pub Dt:
11/16/2006
Title:
ECLIPSE ELIMINATION BY MONITORING THE PIXEL SIGNAL LEVEL
29
Patent #:
7405455
Issue Dt:
07/29/2008
Application #:
11126455
Filing Dt:
05/10/2005
Publication #:
US20050205900
Pub Dt:
09/22/2005
Title:
SEMICONDUCTOR CONSTRUCTIONS AND TRANSISTOR GATES
30
Patent #:
7391654
Issue Dt:
06/24/2008
Application #:
11126682
Filing Dt:
05/11/2005
Publication #:
US20060256622
Pub Dt:
11/16/2006
Title:
MEMORY BLOCK ERASING IN A FLASH MEMORY DEVICE
31
Patent #:
7480195
Issue Dt:
01/20/2009
Application #:
11126747
Filing Dt:
05/11/2005
Publication #:
US20060256631
Pub Dt:
11/16/2006
Title:
INTERNAL DATA COMPARISON FOR MEMORY TESTING
32
Patent #:
7443009
Issue Dt:
10/28/2008
Application #:
11126826
Filing Dt:
05/11/2005
Publication #:
US20060255393
Pub Dt:
11/16/2006
Title:
N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE
33
Patent #:
7221603
Issue Dt:
05/22/2007
Application #:
11127465
Filing Dt:
05/12/2005
Publication #:
US20060256629
Pub Dt:
11/16/2006
Title:
DEFECTIVE BLOCK HANDLING IN A FLASH MEMORY DEVICE
34
Patent #:
7203092
Issue Dt:
04/10/2007
Application #:
11127466
Filing Dt:
05/12/2005
Publication #:
US20060256618
Pub Dt:
11/16/2006
Title:
FLASH MEMORY ARRAY USING ADJACENT BIT LINE AS SOURCE
35
Patent #:
7227789
Issue Dt:
06/05/2007
Application #:
11127526
Filing Dt:
05/12/2005
Publication #:
US20060098497
Pub Dt:
05/11/2006
Title:
METHOD AND APPARATUS FOR FILTERING OUTPUT DATA
36
Patent #:
7113435
Issue Dt:
09/26/2006
Application #:
11127599
Filing Dt:
05/12/2005
Publication #:
US20050213397
Pub Dt:
09/29/2005
Title:
DATA COMPRESSION READ MODE FOR MEMORY TESTING
37
Patent #:
7279740
Issue Dt:
10/09/2007
Application #:
11127618
Filing Dt:
05/12/2005
Publication #:
US20060258090
Pub Dt:
11/16/2006
Title:
BAND-ENGINEERED MULTI-GATED NON-VOLATILE MEMORY DEVICE WITH ENHANCED ATTRIBUTES
38
Patent #:
7434152
Issue Dt:
10/07/2008
Application #:
11127810
Filing Dt:
05/12/2005
Publication #:
US20060044880
Pub Dt:
03/02/2006
Title:
MULTIPLE-LEVEL DATA COMPRESSION READ MODE FOR MEMORY TESTING
39
Patent #:
7767129
Issue Dt:
08/03/2010
Application #:
11127942
Filing Dt:
05/11/2005
Publication #:
US20060255505
Pub Dt:
11/16/2006
Title:
IMPRINT TEMPLATES FOR IMPRINT LITHOGRAPHY, AND METHODS OF PATTERNING A PLURALITY OF SUBSTRATES
40
Patent #:
7407885
Issue Dt:
08/05/2008
Application #:
11127943
Filing Dt:
05/11/2005
Publication #:
US20060258155
Pub Dt:
11/16/2006
Title:
METHODS OF FORMING ELECTRICALLY CONDUCTIVE PLUGS
41
Patent #:
7713885
Issue Dt:
05/11/2010
Application #:
11127944
Filing Dt:
05/11/2005
Publication #:
US20060258169
Pub Dt:
11/16/2006
Title:
METHODS OF ETCHING OXIDE, REDUCING ROUGHNESS, AND FORMING CAPACITOR CONSTRUCTIONS
42
Patent #:
7407892
Issue Dt:
08/05/2008
Application #:
11127945
Filing Dt:
05/11/2005
Publication #:
US20060258157
Pub Dt:
11/16/2006
Title:
DEPOSITION METHODS
43
Patent #:
7224009
Issue Dt:
05/29/2007
Application #:
11128176
Filing Dt:
05/13/2005
Publication #:
US20050205905
Pub Dt:
09/22/2005
Title:
METHOD FOR FORMING A LOW LEAKAGE CONTACT IN A CMOS IMAGER
44
Patent #:
7120046
Issue Dt:
10/10/2006
Application #:
11128585
Filing Dt:
05/13/2005
Title:
MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES
45
Patent #:
7419852
Issue Dt:
09/02/2008
Application #:
11129105
Filing Dt:
05/13/2005
Publication #:
US20060043569
Pub Dt:
03/02/2006
Title:
LOW TEMPERATURE METHODS OF FORMING BACK SIDE REDISTRIBUTION LAYERS IN ASSOCIATION WITH THROUGH WAFER INTERCONNECTS, SEMICONDUCTOR DEVICES INCLUDING SAME, AND ASSEMBLIES
46
Patent #:
7320049
Issue Dt:
01/15/2008
Application #:
11129150
Filing Dt:
05/13/2005
Publication #:
US20050207254
Pub Dt:
09/22/2005
Title:
DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION
47
Patent #:
7269079
Issue Dt:
09/11/2007
Application #:
11129315
Filing Dt:
05/16/2005
Publication #:
US20060256640
Pub Dt:
11/16/2006
Title:
POWER CIRCUITS FOR REDUCING A NUMBER OF POWER SUPPLY VOLTAGE TAPS REQUIRED FOR SENSING A RESISTIVE MEMORY
48
Patent #:
7371627
Issue Dt:
05/13/2008
Application #:
11129502
Filing Dt:
05/13/2005
Title:
MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES
49
Patent #:
7683456
Issue Dt:
03/23/2010
Application #:
11129630
Filing Dt:
05/13/2005
Publication #:
US20050207256
Pub Dt:
09/22/2005
Title:
SEMICONDUCTOR DEVICES, CAPACITOR ANTIFUSES, DYNAMIC RANDOM ACCESS MEMORIES, AND CELL PLATE BIAS CONNECTION METHODS
50
Patent #:
7439157
Issue Dt:
10/21/2008
Application #:
11129884
Filing Dt:
05/16/2005
Publication #:
US20050287731
Pub Dt:
12/29/2005
Title:
ISOLATION TRENCHES FOR MEMORY DEVICES
51
Patent #:
7236387
Issue Dt:
06/26/2007
Application #:
11130598
Filing Dt:
05/17/2005
Publication #:
US20050231996
Pub Dt:
10/20/2005
Title:
WRITING TO FERROELECTRIC MEMORY DEVICES
52
Patent #:
7123503
Issue Dt:
10/17/2006
Application #:
11130663
Filing Dt:
05/17/2005
Publication #:
US20050213365
Pub Dt:
09/29/2005
Title:
WRITING TO FERROELECTRIC MEMORY DEVICES
53
Patent #:
7470628
Issue Dt:
12/30/2008
Application #:
11130760
Filing Dt:
05/17/2005
Publication #:
US20050218373
Pub Dt:
10/06/2005
Title:
ETCHING METHODS
54
Patent #:
7612403
Issue Dt:
11/03/2009
Application #:
11131006
Filing Dt:
05/17/2005
Publication #:
US20060261401
Pub Dt:
11/23/2006
Title:
NOVEL LOW POWER NON-VOLATILE MEMORY AND GATE STACK
55
Patent #:
7273566
Issue Dt:
09/25/2007
Application #:
11131070
Filing Dt:
07/07/2005
Publication #:
US20060011579
Pub Dt:
01/19/2006
Title:
GAS COMPOSITIONS
56
Patent #:
7333370
Issue Dt:
02/19/2008
Application #:
11131081
Filing Dt:
05/17/2005
Publication #:
US20050213410
Pub Dt:
09/29/2005
Title:
METHOD TO PREVENT BIT LINE CAPACITIVE COUPLING
57
Patent #:
7473662
Issue Dt:
01/06/2009
Application #:
11131165
Filing Dt:
05/17/2005
Publication #:
US20050221006
Pub Dt:
10/06/2005
Title:
METAL-DOPED ALUMINA AND LAYERS THEREOF
58
Patent #:
7517753
Issue Dt:
04/14/2009
Application #:
11131552
Filing Dt:
05/18/2005
Publication #:
US20060263968
Pub Dt:
11/23/2006
Title:
METHODS OF FORMING PLURALITIES OF CAPACITORS
59
Patent #:
7443022
Issue Dt:
10/28/2008
Application #:
11131553
Filing Dt:
05/18/2005
Publication #:
US20050205973
Pub Dt:
09/22/2005
Title:
BOARD-ON-CHIP PACKAGES
60
Patent #:
7544563
Issue Dt:
06/09/2009
Application #:
11131575
Filing Dt:
05/18/2005
Publication #:
US20060261440
Pub Dt:
11/23/2006
Title:
METHODS OF FORMING A PLURALITY OF CAPACITORS
61
Patent #:
7341906
Issue Dt:
03/11/2008
Application #:
11132472
Filing Dt:
05/19/2005
Publication #:
US20060263969
Pub Dt:
11/23/2006
Title:
METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME
62
Patent #:
7471130
Issue Dt:
12/30/2008
Application #:
11132502
Filing Dt:
05/19/2005
Publication #:
US20060261869
Pub Dt:
11/23/2006
Title:
GRADUATED DELAY LINE FOR INCREASED CLOCK SKEW CORRECTION CIRCUIT OPERATING RANGE
63
Patent #:
7289363
Issue Dt:
10/30/2007
Application #:
11132602
Filing Dt:
05/19/2005
Publication #:
US20060262601
Pub Dt:
11/23/2006
Title:
MEMORY CELL REPAIR USING FUSE PROGRAMMING METHOD IN A FLASH MEMORY DEVICE
64
Patent #:
7239549
Issue Dt:
07/03/2007
Application #:
11132979
Filing Dt:
05/19/2005
Publication #:
US20050213379
Pub Dt:
09/29/2005
Title:
SEMICONDUCTOR DEVICE
65
Patent #:
7235448
Issue Dt:
06/26/2007
Application #:
11133061
Filing Dt:
05/19/2005
Publication #:
US20050215015
Pub Dt:
09/29/2005
Title:
DIELECTRIC LAYER FORMING METHOD AND DEVICES FORMED THEREWITH
66
Patent #:
7393770
Issue Dt:
07/01/2008
Application #:
11133085
Filing Dt:
05/19/2005
Publication #:
US20060261446
Pub Dt:
11/23/2006
Title:
BACKSIDE METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH CONDUCTIVE INTERCONNECTS
67
Patent #:
7082045
Issue Dt:
07/25/2006
Application #:
11133236
Filing Dt:
05/20/2005
Publication #:
US20050219928
Pub Dt:
10/06/2005
Title:
OFFSET COMPENSATED SENSING FOR MAGNETIC RANDOM ACCESS MEMORY
68
Patent #:
7274201
Issue Dt:
09/25/2007
Application #:
11133843
Filing Dt:
05/19/2005
Publication #:
US20060261836
Pub Dt:
11/23/2006
Title:
METHOD AND SYSTEM FOR STRESSING SEMICONDUCTOR WAFERS DURING BURN-IN
69
Patent #:
7402879
Issue Dt:
07/22/2008
Application #:
11134321
Filing Dt:
05/23/2005
Publication #:
US20050207217
Pub Dt:
09/22/2005
Title:
LAYERED MAGNETIC STRUCTURES HAVING IMPROVED SURFACE PLANARITY FOR BIT MATERIAL DEPOSITION
70
Patent #:
7429536
Issue Dt:
09/30/2008
Application #:
11134982
Filing Dt:
05/23/2005
Publication #:
US20060263699
Pub Dt:
11/23/2006
Title:
METHODS FOR FORMING ARRAYS OF A SMALL, CLOSELY SPACED FEATURES
71
Patent #:
7250663
Issue Dt:
07/31/2007
Application #:
11135558
Filing Dt:
05/24/2005
Publication #:
US20050285265
Pub Dt:
12/29/2005
Title:
FRAME SCALE PACKAGE USING CONTACT LINES THROUGH THE ELEMENTS
72
Patent #:
7006382
Issue Dt:
02/28/2006
Application #:
11136145
Filing Dt:
05/24/2005
Publication #:
US20050219908
Pub Dt:
10/06/2005
Title:
PROGRAMMING FLASH MEMORIES
73
Patent #:
7752381
Issue Dt:
07/06/2010
Application #:
11136152
Filing Dt:
05/24/2005
Publication #:
US20060271725
Pub Dt:
11/30/2006
Title:
VERSION BASED NON-VOLATILE MEMORY TRANSLATION LAYER
74
Patent #:
7179717
Issue Dt:
02/20/2007
Application #:
11136823
Filing Dt:
05/25/2005
Publication #:
US20060270181
Pub Dt:
11/30/2006
Title:
METHODS OF FORMING INTEGRATED CIRCUIT DEVICES
75
Patent #:
7276951
Issue Dt:
10/02/2007
Application #:
11136893
Filing Dt:
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Title:
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Pub Dt:
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Title:
MEMORY DEVICE WITH SWITCHING GLASS LAYER
Assignor
1
JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Exec Dt:
07/31/2019
Assignees
1
MICRON TECHNOLOGY, INC.
8000 S FEDERAL WAY
BOISE, IDAHO 83707
2
MICRON SEMICONDUCTOR PRODUCTS, INC.
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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