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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 59 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
10181713
Issue Dt:
01/15/2019
Application #:
14517605
Filing Dt:
10/17/2014
Publication #:
US20160111867
Pub Dt:
04/21/2016
Title:
METHODS OF POST-PROCESS DISPENSATION OF PLASMA INDUCED DAMAGE PROTECTION COMPONENT
2
Patent #:
9547741
Issue Dt:
01/17/2017
Application #:
14518939
Filing Dt:
10/20/2014
Publication #:
US20160110489
Pub Dt:
04/21/2016
Title:
METHODS, APPARATUS, AND SYSTEM FOR USING FILLER CELLS IN DESIGN OF INTEGRATED CIRCUIT DEVICES
3
Patent #:
9812336
Issue Dt:
11/07/2017
Application #:
14519215
Filing Dt:
10/21/2014
Publication #:
US20150115371
Pub Dt:
04/30/2015
Title:
FINFET SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SAME
4
Patent #:
9362239
Issue Dt:
06/07/2016
Application #:
14519291
Filing Dt:
10/21/2014
Publication #:
US20160111382
Pub Dt:
04/21/2016
Title:
VERTICAL BREAKDOWN PROTECTION LAYER
5
Patent #:
8987816
Issue Dt:
03/24/2015
Application #:
14519902
Filing Dt:
10/21/2014
Publication #:
US20150035052
Pub Dt:
02/05/2015
Title:
CONTACT POWER RAIL
6
Patent #:
10459031
Issue Dt:
10/29/2019
Application #:
14520115
Filing Dt:
10/21/2014
Publication #:
US20150113346
Pub Dt:
04/23/2015
Title:
ELECTRONIC CIRCUIT HAVING SERIAL LATCH SCAN CHAINS
7
Patent #:
9552474
Issue Dt:
01/24/2017
Application #:
14521795
Filing Dt:
10/23/2014
Publication #:
US20150121493
Pub Dt:
04/30/2015
Title:
Method and Computer System for Dynamically Providing Multi-Dimensional Based Password/Challenge Authentication
8
Patent #:
9385232
Issue Dt:
07/05/2016
Application #:
14521939
Filing Dt:
10/23/2014
Publication #:
US20160118499
Pub Dt:
04/28/2016
Title:
FD DEVICES IN ADVANCED SEMICONDUCTOR TECHNIQUES
9
Patent #:
9318217
Issue Dt:
04/19/2016
Application #:
14522017
Filing Dt:
10/23/2014
Publication #:
US20160118138
Pub Dt:
04/28/2016
Title:
PROGRAMMING AN ELECTRICAL FUSE WITH A SILICON-CONTROLLED RECTIFIER
10
Patent #:
9105606
Issue Dt:
08/11/2015
Application #:
14522119
Filing Dt:
10/23/2014
Publication #:
US20150041868
Pub Dt:
02/12/2015
Title:
SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS
11
Patent #:
9275907
Issue Dt:
03/01/2016
Application #:
14522649
Filing Dt:
10/24/2014
Publication #:
US20150041858
Pub Dt:
02/12/2015
Title:
3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT
12
Patent #:
9777388
Issue Dt:
10/03/2017
Application #:
14522809
Filing Dt:
10/24/2014
Publication #:
US20160115616
Pub Dt:
04/28/2016
Title:
ELECTROPLATING SYSTEM AND METHOD OF USING ELECTROPLATING SYSTEM FOR CONTROLLING CONCENTRATION OF ORGANIC ADDITIVES IN ELECTROPLATING SOLUTION
13
Patent #:
9337041
Issue Dt:
05/10/2016
Application #:
14524079
Filing Dt:
10/27/2014
Publication #:
US20150111350
Pub Dt:
04/23/2015
Title:
ANISOTROPIC DIELECTRIC MATERIAL GATE SPACER FOR A FIELD EFFECT TRANSISTOR
14
Patent #:
9576856
Issue Dt:
02/21/2017
Application #:
14524628
Filing Dt:
10/27/2014
Publication #:
US20160118304
Pub Dt:
04/28/2016
Title:
FABRICATION OF NANOWIRE FIELD EFFECT TRANSISTOR STRUCTURES
15
Patent #:
9614056
Issue Dt:
04/04/2017
Application #:
14525288
Filing Dt:
10/28/2014
Publication #:
US20160118480
Pub Dt:
04/28/2016
Title:
METHODS OF FORMING A TRI-GATE FINFET DEVICE
16
Patent #:
9018052
Issue Dt:
04/28/2015
Application #:
14525559
Filing Dt:
10/28/2014
Publication #:
US20150064853
Pub Dt:
03/05/2015
Title:
INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
17
Patent #:
9335368
Issue Dt:
05/10/2016
Application #:
14525596
Filing Dt:
10/28/2014
Publication #:
US20160116526
Pub Dt:
04/28/2016
Title:
METHOD AND APPARATUS FOR QUANTIFYING DEFECTS DUE TO THROUGH SILICON VIAs IN INTEGRATED CIRCUITS
18
Patent #:
9324827
Issue Dt:
04/26/2016
Application #:
14525744
Filing Dt:
10/28/2014
Publication #:
US20160118473
Pub Dt:
04/28/2016
Title:
NON-PLANAR SCHOTTKY DIODE AND METHOD OF FABRICATION
19
Patent #:
9337197
Issue Dt:
05/10/2016
Application #:
14525763
Filing Dt:
10/28/2014
Publication #:
US20160118386
Pub Dt:
04/28/2016
Title:
SEMICONDUCTOR STRUCTURE HAVING FINFET ULTRA THIN BODY AND METHODS OF FABRICATION THEREOF
20
Patent #:
9431294
Issue Dt:
08/30/2016
Application #:
14525796
Filing Dt:
10/28/2014
Publication #:
US20160118292
Pub Dt:
04/28/2016
Title:
METHODS OF PRODUCING INTEGRATED CIRCUITS WITH AN AIR GAP
21
Patent #:
9508743
Issue Dt:
11/29/2016
Application #:
14525842
Filing Dt:
10/28/2014
Publication #:
US20160118414
Pub Dt:
04/28/2016
Title:
DUAL THREE-DIMENSIONAL AND RF SEMICONDUCTOR DEVICES USING LOCAL SOI
22
Patent #:
9263537
Issue Dt:
02/16/2016
Application #:
14526126
Filing Dt:
10/28/2014
Publication #:
US20150041869
Pub Dt:
02/12/2015
Title:
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
23
Patent #:
10163892
Issue Dt:
12/25/2018
Application #:
14526580
Filing Dt:
10/29/2014
Publication #:
US20150048416
Pub Dt:
02/19/2015
Title:
SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES
24
Patent #:
9478663
Issue Dt:
10/25/2016
Application #:
14526617
Filing Dt:
10/29/2014
Publication #:
US20160126353
Pub Dt:
05/05/2016
Title:
FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN
25
Patent #:
9559059
Issue Dt:
01/31/2017
Application #:
14526678
Filing Dt:
10/29/2014
Publication #:
US20160126190
Pub Dt:
05/05/2016
Title:
METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A CONDUCTIVE CAPPING LAYER
26
Patent #:
10014379
Issue Dt:
07/03/2018
Application #:
14526980
Filing Dt:
10/29/2014
Publication #:
US20170077247
Pub Dt:
03/16/2017
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE
27
Patent #:
9318551
Issue Dt:
04/19/2016
Application #:
14527042
Filing Dt:
10/29/2014
Publication #:
US20150060950
Pub Dt:
03/05/2015
Title:
TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS
28
Patent #:
9299616
Issue Dt:
03/29/2016
Application #:
14527867
Filing Dt:
10/30/2014
Title:
INTEGRATED CIRCUITS WITH SEPARATE WORKFUNCTION MATERIAL LAYERS AND METHODS FOR FABRICATING THE SAME
29
Patent #:
9070734
Issue Dt:
06/30/2015
Application #:
14528388
Filing Dt:
10/30/2014
Publication #:
US20150053982
Pub Dt:
02/26/2015
Title:
HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE
30
Patent #:
9269629
Issue Dt:
02/23/2016
Application #:
14528830
Filing Dt:
10/30/2014
Publication #:
US20150064874
Pub Dt:
03/05/2015
Title:
DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM
31
Patent #:
9417501
Issue Dt:
08/16/2016
Application #:
14529243
Filing Dt:
10/31/2014
Publication #:
US20150064817
Pub Dt:
03/05/2015
Title:
ELECTRICALLY CONTROLLED OPTICAL FUSE AND METHOD OF FABRICATION
32
Patent #:
9478549
Issue Dt:
10/25/2016
Application #:
14529332
Filing Dt:
10/31/2014
Publication #:
US20150064855
Pub Dt:
03/05/2015
Title:
FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION
33
Patent #:
9501638
Issue Dt:
11/22/2016
Application #:
14529338
Filing Dt:
10/31/2014
Publication #:
US20150121538
Pub Dt:
04/30/2015
Title:
TECHNIQUES FOR MANAGING SECURITY MODES APPLIED TO APPLICATION PROGRAM EXECUTION
34
Patent #:
9385231
Issue Dt:
07/05/2016
Application #:
14530796
Filing Dt:
11/02/2014
Publication #:
US20150060944
Pub Dt:
03/05/2015
Title:
DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE
35
Patent #:
9443948
Issue Dt:
09/13/2016
Application #:
14532122
Filing Dt:
11/04/2014
Publication #:
US20150083999
Pub Dt:
03/26/2015
Title:
Gate-All-Around Nanowire MOSFET and Method of Formation
36
Patent #:
9257361
Issue Dt:
02/09/2016
Application #:
14532437
Filing Dt:
11/04/2014
Publication #:
US20150059361
Pub Dt:
03/05/2015
Title:
IN-SITU THERMOELECTRIC COOLING
37
Patent #:
9252022
Issue Dt:
02/02/2016
Application #:
14533629
Filing Dt:
11/05/2014
Title:
PATTERNING ASSIST FEATURE TO MITIGATE REACTIVE ION ETCH MICROLOADING EFFECT
38
Patent #:
9276064
Issue Dt:
03/01/2016
Application #:
14535433
Filing Dt:
11/07/2014
Title:
FABRICATING STACKED NANOWIRE, FIELD-EFFECT TRANSISTORS
39
Patent #:
9412839
Issue Dt:
08/09/2016
Application #:
14535942
Filing Dt:
11/07/2014
Publication #:
US20160133720
Pub Dt:
05/12/2016
Title:
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON FINFET DEVICES AND THE RESULTING DEVICES
40
Patent #:
9543416
Issue Dt:
01/10/2017
Application #:
14536026
Filing Dt:
11/07/2014
Publication #:
US20160133726
Pub Dt:
05/12/2016
Title:
METHODS OF FORMING PRODUCTS WITH FINFET SEMICONDUCTOR DEVICES WITHOUT REMOVING FINS IN CERTAIN AREAS OF THE PRODUCT
41
Patent #:
9379209
Issue Dt:
06/28/2016
Application #:
14536167
Filing Dt:
11/07/2014
Publication #:
US20160133721
Pub Dt:
05/12/2016
Title:
SELECTIVELY FORMING A PROTECTIVE CONDUCTIVE CAP ON A METAL GATE ELECTRODE
42
Patent #:
9076787
Issue Dt:
07/07/2015
Application #:
14536737
Filing Dt:
11/10/2014
Publication #:
US20150061032
Pub Dt:
03/05/2015
Title:
FABRICATION OF NICKEL FREE SILICIDE FOR SEMICONDUCTOR CONTACT METALLIZATION
43
Patent #:
9478642
Issue Dt:
10/25/2016
Application #:
14537832
Filing Dt:
11/10/2014
Publication #:
US20160133727
Pub Dt:
05/12/2016
Title:
SEMICONDUCTOR JUNCTION FORMATION
44
Patent #:
9627377
Issue Dt:
04/18/2017
Application #:
14538401
Filing Dt:
11/11/2014
Publication #:
US20150061040
Pub Dt:
03/05/2015
Title:
SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES
45
Patent #:
9111938
Issue Dt:
08/18/2015
Application #:
14538944
Filing Dt:
11/12/2014
Publication #:
US20150061135
Pub Dt:
03/05/2015
Title:
COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP
46
Patent #:
9190260
Issue Dt:
11/17/2015
Application #:
14540504
Filing Dt:
11/13/2014
Title:
TOPOLOGICAL METHOD TO BUILD SELF-ALIGNED MTJ WITHOUT A MASK
47
Patent #:
9466604
Issue Dt:
10/11/2016
Application #:
14540724
Filing Dt:
11/13/2014
Publication #:
US20160141291
Pub Dt:
05/19/2016
Title:
METAL SEGMENTS AS LANDING PADS AND LOCAL INTERCONNECTS IN AN IC DEVICE
48
Patent #:
9087722
Issue Dt:
07/21/2015
Application #:
14541182
Filing Dt:
11/14/2014
Publication #:
US20150069525
Pub Dt:
03/12/2015
Title:
SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES
49
Patent #:
9443944
Issue Dt:
09/13/2016
Application #:
14541754
Filing Dt:
11/14/2014
Publication #:
US20160141379
Pub Dt:
05/19/2016
Title:
INTEGRATED CIRCUITS WITH MIDDLE OF LINE CAPACITANCE REDUCTION IN SELF-ALIGNED CONTACT PROCESS FLOW AND FABRICATION METHODS
50
Patent #:
9490197
Issue Dt:
11/08/2016
Application #:
14541803
Filing Dt:
11/14/2014
Publication #:
US20160141237
Pub Dt:
05/19/2016
Title:
THREE DIMENSIONAL ORGANIC OR GLASS INTERPOSER
51
Patent #:
9502293
Issue Dt:
11/22/2016
Application #:
14543992
Filing Dt:
11/18/2014
Publication #:
US20160141206
Pub Dt:
05/19/2016
Title:
SELF-ALIGNED VIA PROCESS FLOW
52
Patent #:
9165819
Issue Dt:
10/20/2015
Application #:
14546058
Filing Dt:
11/18/2014
Publication #:
US20150072504
Pub Dt:
03/12/2015
Title:
HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS
53
Patent #:
10031989
Issue Dt:
07/24/2018
Application #:
14546065
Filing Dt:
11/18/2014
Publication #:
US20160140273
Pub Dt:
05/19/2016
Title:
INTEGRATED CIRCUIT PERFORMANCE MODELING USING A CONNECTIVITY-BASED CONDENSED RESISTANCE MODEL FOR A CONDUCTIVE STRUCTURE IN AN INTEGRATED CIRCUIT
54
Patent #:
9293189
Issue Dt:
03/22/2016
Application #:
14549117
Filing Dt:
11/20/2014
Publication #:
US20150078068
Pub Dt:
03/19/2015
Title:
INTEGRATED CIRCUITS WITH SRAM CELLS HAVING ADDITIONAL READ STACKS
55
Patent #:
9219666
Issue Dt:
12/22/2015
Application #:
14549663
Filing Dt:
11/21/2014
Publication #:
US20150082102
Pub Dt:
03/19/2015
Title:
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
56
Patent #:
9455330
Issue Dt:
09/27/2016
Application #:
14550019
Filing Dt:
11/21/2014
Publication #:
US20160149015
Pub Dt:
05/26/2016
Title:
RECESSING RMG METAL GATE STACK FOR FORMING SELF-ALIGNED CONTACT
57
Patent #:
9293414
Issue Dt:
03/22/2016
Application #:
14551249
Filing Dt:
11/24/2014
Publication #:
US20150076656
Pub Dt:
03/19/2015
Title:
ELECTRONIC FUSE HAVING A SUBSTANTIALLY UNIFORM THERMAL PROFILE
58
Patent #:
9726547
Issue Dt:
08/08/2017
Application #:
14553203
Filing Dt:
11/25/2014
Publication #:
US20160146672
Pub Dt:
05/26/2016
Title:
MICROBOLOMETER DEVICES IN CMOS AND BiCMOS TECHNOLOGIES
59
Patent #:
9087717
Issue Dt:
07/21/2015
Application #:
14554766
Filing Dt:
11/26/2014
Publication #:
US20150084091
Pub Dt:
03/26/2015
Title:
TUNNEL FIELD-EFFECT TRANSISTORS WITH A GATE-SWING BROKEN-GAP HETEROSTRUCTURE
60
Patent #:
9064743
Issue Dt:
06/23/2015
Application #:
14556200
Filing Dt:
11/30/2014
Publication #:
US20150123204
Pub Dt:
05/07/2015
Title:
FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES
61
Patent #:
9059139
Issue Dt:
06/16/2015
Application #:
14556638
Filing Dt:
12/01/2014
Publication #:
US20150087120
Pub Dt:
03/26/2015
Title:
Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer
62
Patent #:
9892958
Issue Dt:
02/13/2018
Application #:
14558037
Filing Dt:
12/02/2014
Publication #:
US20160155661
Pub Dt:
06/02/2016
Title:
CONTACT MODULE FOR OPTIMIZING EMITTER AND CONTACT RESISTANCE
63
Patent #:
9412691
Issue Dt:
08/09/2016
Application #:
14558782
Filing Dt:
12/03/2014
Publication #:
US20160163631
Pub Dt:
06/09/2016
Title:
CHIP CARRIER WITH DUAL-SIDED CHIP ACCESS AND A METHOD FOR TESTING A CHIP USING THE CHIP CARRIER
64
Patent #:
9535703
Issue Dt:
01/03/2017
Application #:
14559087
Filing Dt:
12/03/2014
Publication #:
US20150089208
Pub Dt:
03/26/2015
Title:
PREDICTOR DATA STRUCTURE FOR USE IN PIPELINED PROCESSING
65
Patent #:
9607989
Issue Dt:
03/28/2017
Application #:
14560049
Filing Dt:
12/04/2014
Publication #:
US20160163702
Pub Dt:
06/09/2016
Title:
FORMING SELF-ALIGNED NISI PLACEMENT WITH IMPROVED PERFORMANCE AND YIELD
66
Patent #:
9761691
Issue Dt:
09/12/2017
Application #:
14560054
Filing Dt:
12/04/2014
Publication #:
US20160163824
Pub Dt:
06/09/2016
Title:
INTEGRATED CIRCUITS INCLUDING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME
67
Patent #:
9082852
Issue Dt:
07/14/2015
Application #:
14560472
Filing Dt:
12/04/2014
Title:
LDMOS FINFET DEVICE USING A LONG CHANNEL REGION AND METHOD OF MANUFACTURE
68
Patent #:
9547232
Issue Dt:
01/17/2017
Application #:
14560688
Filing Dt:
12/04/2014
Publication #:
US20160161857
Pub Dt:
06/09/2016
Title:
PELLICLE WITH AEROGEL SUPPORT FRAME
69
Patent #:
9406616
Issue Dt:
08/02/2016
Application #:
14561359
Filing Dt:
12/05/2014
Publication #:
US20160163644
Pub Dt:
06/09/2016
Title:
MERGED SOURCE/DRAIN AND GATE CONTACTS IN SRAM BITCELL
70
Patent #:
9392679
Issue Dt:
07/12/2016
Application #:
14562570
Filing Dt:
12/05/2014
Publication #:
US20160165710
Pub Dt:
06/09/2016
Title:
METHOD, APPARATUS AND SYSTEM FOR USING FREE-ELECTRON LASER COMPATIBLE EUV BEAM FOR SEMICONDUCTOR WAFER PROCESSING
71
Patent #:
9449887
Issue Dt:
09/20/2016
Application #:
14563009
Filing Dt:
12/08/2014
Publication #:
US20160163814
Pub Dt:
06/09/2016
Title:
METHOD OF FORMING REPLACEMENT GATE PFET HAVING TIALCO LAYER FOR IMPROVED NBTI PERFORMANCE
72
Patent #:
9455926
Issue Dt:
09/27/2016
Application #:
14563152
Filing Dt:
12/08/2014
Publication #:
US20150092546
Pub Dt:
04/02/2015
Title:
QUEUE CREDIT MANAGEMENT
73
Patent #:
9472470
Issue Dt:
10/18/2016
Application #:
14564323
Filing Dt:
12/09/2014
Publication #:
US20160163826
Pub Dt:
06/09/2016
Title:
METHODS OF FORMING FINFET WITH WIDE UNMERGED SOURCE DRAIN EPI
74
Patent #:
9490223
Issue Dt:
11/08/2016
Application #:
14566773
Filing Dt:
12/11/2014
Publication #:
US20160172314
Pub Dt:
06/16/2016
Title:
STRUCTURE TO PREVENT DEEP TRENCH MOAT CHARGING AND MOAT ISOLATION FAILS
75
Patent #:
9412759
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08/09/2016
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Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
10/22/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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