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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 60 of 85
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Patent #:	9466722	Issue Dt:	10/11/2016	Application #:	14584639	Filing Dt:	12/29/2014
Publication #:	US20160190322	Pub Dt:	06/30/2016
Title:	LARGE AREA CONTACTS FOR SMALL TRANSISTORS

Patent #:	10050115	Issue Dt:	08/14/2018	Application #:	14585933	Filing Dt:	12/30/2014
Publication #:	US20160190269	Pub Dt:	06/30/2016
Title:	TAPERED GATE OXIDE IN LDMOS DEVICES

Patent #:	9305834	Issue Dt:	04/05/2016	Application #:	14586268	Filing Dt:	12/30/2014
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DESIGNS OF INTEGRATED CIRCUITS ADAPTED TO DIRECTED SELF-ASSEMBLY FABRICATION TO FORM VIA AND CONTACT STRUCTURES

Patent #:	9859423	Issue Dt:	01/02/2018	Application #:	14587655	Filing Dt:	12/31/2014
Publication #:	US20160190317	Pub Dt:	06/30/2016
Title:	HETERO-CHANNEL FINFET

Patent #:	10032912	Issue Dt:	07/24/2018	Application #:	14588221	Filing Dt:	12/31/2014
Publication #:	US20160190304	Pub Dt:	06/30/2016
Title:	A SEMICONDUCTOR INTEGRATED STRUCTURE HAVING AN EPITAXIAL SiGe LAYER EXTENDING FROM SILICON-CONTAINING REGIONS FORMED BETWEEN SEGMENTS OF OXIDE REGIONS

Patent #:	9263385	Issue Dt:	02/16/2016	Application #:	14589011	Filing Dt:	01/05/2015
Title:	SEMICONDUCTOR FUSES AND FABRICATION METHODS THEREOF

Patent #:	9660573	Issue Dt:	05/23/2017	Application #:	14589171	Filing Dt:	01/05/2015
Publication #:	US20160197579	Pub Dt:	07/07/2016
Title:	PASSIVE SOLAR PANEL COOLING

Patent #:	9064733	Issue Dt:	06/23/2015	Application #:	14590076	Filing Dt:	01/06/2015
Publication #:	US20150145061	Pub Dt:	05/28/2015
Title:	NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME

Patent #:	9881830	Issue Dt:	01/30/2018	Application #:	14590591	Filing Dt:	01/06/2015
Publication #:	US20160197004	Pub Dt:	07/07/2016
Title:	ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS

Patent #:	9443871	Issue Dt:	09/13/2016	Application #:	14592069	Filing Dt:	01/08/2015
Publication #:	US20160204128	Pub Dt:	07/14/2016
Title:	COINTEGRATION OF BULK AND SOI SEMICONDUCTOR DEVICES

Patent #:	9368407	Issue Dt:	06/14/2016	Application #:	14592421	Filing Dt:	01/08/2015
Publication #:	US20150140831	Pub Dt:	05/21/2015
Title:	CRACK CONTROL FOR SUBSTRATE SEPARATION

Patent #:	9508602	Issue Dt:	11/29/2016	Application #:	14593183	Filing Dt:	01/09/2015
Publication #:	US20160204039	Pub Dt:	07/14/2016
Title:	TEMPERATURE-CONTROLLED IMPLANTING OF A DIFFUSION-SUPPRESSING DOPANT IN A SEMICONDUCTOR STRUCTURE

Patent #:	9087868	Issue Dt:	07/21/2015	Application #:	14593282	Filing Dt:	01/09/2015
Publication #:	US20150115399	Pub Dt:	04/30/2015
Title:	BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS

Patent #:	9472643	Issue Dt:	10/18/2016	Application #:	14595756	Filing Dt:	01/13/2015
Publication #:	US20150126020	Pub Dt:	05/07/2015
Title:	METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Patent #:	9541935	Issue Dt:	01/10/2017	Application #:	14595850	Filing Dt:	01/13/2015
Publication #:	US20150123633	Pub Dt:	05/07/2015
Title:	PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS

Patent #:	9735174	Issue Dt:	08/15/2017	Application #:	14596331	Filing Dt:	01/14/2015
Publication #:	US20160204129	Pub Dt:	07/14/2016
Title:	FDSOI - CAPACITOR

Patent #:	9412620	Issue Dt:	08/09/2016	Application #:	14597327	Filing Dt:	01/15/2015
Publication #:	US20150147869	Pub Dt:	05/28/2015
Title:	THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION INCLUDING WAFER SCALE MEMBRANE

Patent #:	9275989	Issue Dt:	03/01/2016	Application #:	14598701	Filing Dt:	01/16/2015
Publication #:	US20150123181	Pub Dt:	05/07/2015
Title:	CAPACITORS POSITIONED AT THE DEVICE LEVEL IN AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF MAKING SUCH CAPACITORS

Patent #:	10020256	Issue Dt:	07/10/2018	Application #:	14599576	Filing Dt:	01/19/2015
Publication #:	US20150130019	Pub Dt:	05/14/2015
Title:	ELECTRONIC FUSE HAVING AN INSULATION LAYER

Patent #:	9443945	Issue Dt:	09/13/2016	Application #:	14600097	Filing Dt:	01/20/2015
Publication #:	US20150129966	Pub Dt:	05/14/2015
Title:	TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS

Patent #:	9225360	Issue Dt:	12/29/2015	Application #:	14601172	Filing Dt:	01/20/2015
Publication #:	US20150149860	Pub Dt:	05/28/2015
Title:	ITERATIVE DATA STORAGE READ CHANNEL ARCHITECTURE

Patent #:	9099493	Issue Dt:	08/04/2015	Application #:	14601745	Filing Dt:	01/21/2015
Publication #:	US20150132898	Pub Dt:	05/14/2015
Title:	Semiconductor Device With Raised Source/Drain And Replacement Metal Gate

Patent #:	9653204	Issue Dt:	05/16/2017	Application #:	14602567	Filing Dt:	01/22/2015
Publication #:	US20160217904	Pub Dt:	07/28/2016
Title:	SYMMETRIC MULTI-PORT INDUCTOR FOR DIFFERENTIAL MULTI-BAND RF CIRCUITS

Patent #:	9478671	Issue Dt:	10/25/2016	Application #:	14602940	Filing Dt:	01/22/2015
Publication #:	US20150137316	Pub Dt:	05/21/2015
Title:	SEMICONDUCTOR DEVICE INCLUDING A RESISTOR AND METHOD FOR THE FORMATION THEREOF

Patent #:	9172132	Issue Dt:	10/27/2015	Application #:	14603856	Filing Dt:	01/23/2015
Publication #:	US20150129668	Pub Dt:	05/14/2015
Title:	INTEGRATED ANTENNA FOR RFIC PACKAGE APPLICATIONS

Patent #:	9460760	Issue Dt:	10/04/2016	Application #:	14604009	Filing Dt:	01/23/2015
Publication #:	US20160217832	Pub Dt:	07/28/2016
Title:	DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER

Patent #:	NONE	Issue Dt:		Application #:	14605009	Filing Dt:	01/26/2015
Publication #:	US20150144886	Pub Dt:	05/28/2015
Title:	FINFET WITH MERGE-FREE FINS

Patent #:	NONE	Issue Dt:		Application #:	14605018	Filing Dt:	01/26/2015
Publication #:	US20150140762	Pub Dt:	05/21/2015
Title:	FINFET WITH MERGE-FREE FINS

Patent #:	9263442	Issue Dt:	02/16/2016	Application #:	14606224	Filing Dt:	01/27/2015
Publication #:	US20150137267	Pub Dt:	05/21/2015
Title:	REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING

Patent #:	9299617	Issue Dt:	03/29/2016	Application #:	14607191	Filing Dt:	01/28/2015
Publication #:	US20150147868	Pub Dt:	05/28/2015
Title:	LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE

Patent #:	NONE	Issue Dt:		Application #:	14607611	Filing Dt:	01/28/2015
Publication #:	US20150144887	Pub Dt:	05/28/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	NONE	Issue Dt:		Application #:	14607629	Filing Dt:	01/28/2015
Publication #:	US20150144888	Pub Dt:	05/28/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	NONE	Issue Dt:		Application #:	14607657	Filing Dt:	01/28/2015
Publication #:	US20150153320	Pub Dt:	06/04/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	NONE	Issue Dt:		Application #:	14607694	Filing Dt:	01/28/2015
Publication #:	US20150140716	Pub Dt:	05/21/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	9484428	Issue Dt:	11/01/2016	Application #:	14608288	Filing Dt:	01/29/2015
Publication #:	US20160225870	Pub Dt:	08/04/2016
Title:	NON-PLANAR EXCITON TRANSISTOR (BISFET) AND METHODS FOR MAKING

Patent #:	9097698	Issue Dt:	08/04/2015	Application #:	14608781	Filing Dt:	01/29/2015
Publication #:	US20150137069	Pub Dt:	05/21/2015
Title:	NANOGAP DEVICE WITH CAPPED NANOWIRE STRUCTURES

Patent #:	10026659	Issue Dt:	07/17/2018	Application #:	14608815	Filing Dt:	01/29/2015
Publication #:	US20160225676	Pub Dt:	08/04/2016
Title:	METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FINS ON FINFET SEMICONDUCTOR DEVICES

Patent #:	9741622	Issue Dt:	08/22/2017	Application #:	14608902	Filing Dt:	01/29/2015
Publication #:	US20160225674	Pub Dt:	08/04/2016
Title:	METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT

Patent #:	9472574	Issue Dt:	10/18/2016	Application #:	14609115	Filing Dt:	01/29/2015
Publication #:	US20160225791	Pub Dt:	08/04/2016
Title:	ULTRATHIN BODY (UTB) FINFET SEMICONDUCTOR STRUCTURE

Patent #:	9412659	Issue Dt:	08/09/2016	Application #:	14609271	Filing Dt:	01/29/2015
Publication #:	US20160225667	Pub Dt:	08/04/2016
Title:	SEMICONDUCTOR STRUCTURE HAVING SOURCE/DRAIN GOUGING IMMUNITY

Patent #:	9436078	Issue Dt:	09/06/2016	Application #:	14609588	Filing Dt:	01/30/2015
Publication #:	US20160223896	Pub Dt:	08/04/2016
Title:	METHOD FOR A LOW PROFILE ETCHABLE EUV ABSORBER LAYER WITH EMBEDDED PARTICLES IN A PHOTOLITHOGRAPHY MASK

Patent #:	9368496	Issue Dt:	06/14/2016	Application #:	14609614	Filing Dt:	01/30/2015
Title:	METHOD FOR UNIFORM RECESS DEPTH AND FILL IN SINGLE DIFFUSION BREAK FOR FIN-TYPE PROCESS AND RESULTING DEVICES

Patent #:	9425252	Issue Dt:	08/23/2016	Application #:	14609653	Filing Dt:	01/30/2015
Publication #:	US20160225848	Pub Dt:	08/04/2016
Title:	PROCESS FOR SINGLE DIFFUSION BREAK WITH SIMPLIFIED PROCESS

Patent #:	9337099	Issue Dt:	05/10/2016	Application #:	14610260	Filing Dt:	01/30/2015
Title:	SPECIAL CONSTRUCTS FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS

Patent #:	9460975	Issue Dt:	10/04/2016	Application #:	14611496	Filing Dt:	02/02/2015
Publication #:	US20160225679	Pub Dt:	08/04/2016
Title:	DFT STRUCTURE FOR TSVS IN 3D ICS WHILE MAINTAINING FUNCTIONAL PURPOSE

Patent #:	9318437	Issue Dt:	04/19/2016	Application #:	14611740	Filing Dt:	02/02/2015
Title:	MOISTURE SCAVENGING LAYER FOR THINNER BARRIER APPLICATION IN BEOL INTEGRATION

Patent #:	9552455	Issue Dt:	01/24/2017	Application #:	14612683	Filing Dt:	02/03/2015
Publication #:	US20160224717	Pub Dt:	08/04/2016
Title:	Method for an Efficient Modeling of the Impact of Device-Level Self-Heating on Electromigration Limited Current Specifications

Patent #:	9324869	Issue Dt:	04/26/2016	Application #:	14613425	Filing Dt:	02/04/2015
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE AND RESULTING SEMICONDUCTOR DEVICES

Patent #:	9852956	Issue Dt:	12/26/2017	Application #:	14613570	Filing Dt:	02/04/2015
Publication #:	US20160225680	Pub Dt:	08/04/2016
Title:	EXTRACTION OF RESISTANCE ASSOCIATED WITH LATERALLY DIFFUSED DOPANT PROFILES IN CMOS DEVICES

Patent #:	9508795	Issue Dt:	11/29/2016	Application #:	14613983	Filing Dt:	02/04/2015
Publication #:	US20160225849	Pub Dt:	08/04/2016
Title:	METHODS OF FABRICATING NANOWIRE STRUCTURES

Patent #:	9390981	Issue Dt:	07/12/2016	Application #:	14614489	Filing Dt:	02/05/2015
Title:	METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURE WITH N-TYPE AND P-TYPE FIELD EFFECT TRANSISTORS HAVING SYMMETRIC SOURCE/DRAIN JUNCTIONS AND OPTIONAL DUAL SILICIDES

Patent #:	9412848	Issue Dt:	08/09/2016	Application #:	14615529	Filing Dt:	02/06/2015
Publication #:	US20160233318	Pub Dt:	08/11/2016
Title:	METHODS OF FORMING A COMPLEX GAA FET DEVICE AT ADVANCED TECHNOLOGY NODES

Patent #:	9184162	Issue Dt:	11/10/2015	Application #:	14615762	Filing Dt:	02/06/2015
Publication #:	US20150179644	Pub Dt:	06/25/2015
Title:	FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION

Patent #:	9443738	Issue Dt:	09/13/2016	Application #:	14616226	Filing Dt:	02/06/2015
Publication #:	US20160233091	Pub Dt:	08/11/2016
Title:	INTEGRATED CIRCUITS WITH MIDDLE OF LINE CAPACITANCE REDUCTION IN SELF-ALIGNED CONTACT PROCESS FLOW AND FABRICATION METHODS

Patent #:	9818796	Issue Dt:	11/14/2017	Application #:	14616855	Filing Dt:	02/09/2015
Publication #:	US20160380026	Pub Dt:	12/29/2016
Title:	PLANAR QUBITS HAVING INCREASED COHERENCE TIMES

Patent #:	NONE	Issue Dt:		Application #:	14617647	Filing Dt:	02/09/2015
Publication #:	US20150200277	Pub Dt:	07/16/2015
Title:	NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME

Patent #:	9305883	Issue Dt:	04/05/2016	Application #:	14620233	Filing Dt:	02/12/2015
Publication #:	US20150179576	Pub Dt:	06/25/2015
Title:	LOCALLY RAISED EPITAXY FOR IMPROVED CONTACT BY LOCAL SILICON CAPPING DURING TRENCH SILICIDE PROCESSINGS

Patent #:	10096609	Issue Dt:	10/09/2018	Application #:	14622997	Filing Dt:	02/16/2015
Publication #:	US20160240438	Pub Dt:	08/18/2016
Title:	MODIFIED TUNGSTEN SILICON

Patent #:	9059267	Issue Dt:	06/16/2015	Application #:	14623720	Filing Dt:	02/17/2015
Publication #:	US20150162425	Pub Dt:	06/11/2015
Title:	III-V Device with Overlapped Extension Regions Using Replacement Gate

Patent #:	9064946	Issue Dt:	06/23/2015	Application #:	14623732	Filing Dt:	02/17/2015
Publication #:	US20150162426	Pub Dt:	06/11/2015
Title:	III-V FET Device with Overlapped Extension Regions Using Gate Last

Patent #:	10082483	Issue Dt:	09/25/2018	Application #:	14626191	Filing Dt:	02/19/2015
Publication #:	US20150160157	Pub Dt:	06/11/2015
Title:	SCANNING PROBE WITH TWIN-NANOPORE OR A-SINGLE-NANOPORE FOR SENSING BIOMOLECULES

Patent #:	9466685	Issue Dt:	10/11/2016	Application #:	14628947	Filing Dt:	02/23/2015
Publication #:	US20160247891	Pub Dt:	08/25/2016
Title:	SEMICONDUCTOR STRUCTURE INCLUDING AT LEAST ONE ELECTRICALLY CONDUCTIVE PILLAR, SEMICONDUCTOR STRUCTURE INCLUDING A CONTACT CONTACTING AN OUTER LAYER OF AN ELECTRICALLY CONDUCTIVE STRUCTURE AND METHOD FOR THE FORMATION THEREOF

Patent #:	10147652	Issue Dt:	12/04/2018	Application #:	14630529	Filing Dt:	02/24/2015
Publication #:	US20160247724	Pub Dt:	08/25/2016
Title:	METHOD, APPARATUS AND SYSTEM FOR ADVANCED CHANNEL CMOS INTEGRATION

Patent #:	9530662	Issue Dt:	12/27/2016	Application #:	14630676	Filing Dt:	02/25/2015
Publication #:	US20160247686	Pub Dt:	08/25/2016
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY INCLUDING A SUBSTANTIALLY PERIODIC ARRAY OF TOPOGRAPHICAL FEATURES THAT INCLUDES ETCH RESISTANT TOPOGRAPHICAL FEATURES FOR TRANSFERABILITY CONTROL

Patent #:	9814982	Issue Dt:	11/14/2017	Application #:	14630774	Filing Dt:	02/25/2015
Publication #:	US20160243443	Pub Dt:	08/25/2016
Title:	MITIGATING COLLISIONS IN A PHYSICAL SPACE DURING GAMING

Patent #:	9378972	Issue Dt:	06/28/2016	Application #:	14632313	Filing Dt:	02/26/2015
Publication #:	US20150170927	Pub Dt:	06/18/2015
Title:	INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES

Patent #:	9337122	Issue Dt:	05/10/2016	Application #:	14633069	Filing Dt:	02/26/2015
Publication #:	US20150221575	Pub Dt:	08/06/2015
Title:	TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY

Patent #:	9425318	Issue Dt:	08/23/2016	Application #:	14633351	Filing Dt:	02/27/2015
Publication #:	US20160254382	Pub Dt:	09/01/2016
Title:	INTEGRATED CIRCUITS WITH FETS HAVING NANOWIRES AND METHODS OF MANUFACTURING THE SAME

Patent #:	9520321	Issue Dt:	12/13/2016	Application #:	14633914	Filing Dt:	02/27/2015
Publication #:	US20160254185	Pub Dt:	09/01/2016
Title:	INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SELF-ALIGNED VIAS

Patent #:	10008848	Issue Dt:	06/26/2018	Application #:	14635005	Filing Dt:	03/02/2015
Publication #:	US20160261109	Pub Dt:	09/08/2016
Title:	METHOD TO PROTECT SENSITIVE DEVICES FROM ELECTROSTATIC DISCHARGE DAMAGE

Patent #:	9851397	Issue Dt:	12/26/2017	Application #:	14635125	Filing Dt:	03/02/2015
Publication #:	US20160258998	Pub Dt:	09/08/2016
Title:	ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS

Patent #:	9541839	Issue Dt:	01/10/2017	Application #:	14637459	Filing Dt:	03/04/2015
Publication #:	US20160259251	Pub Dt:	09/08/2016
Title:	METHOD AND DEVICE FOR SPLITTING A HIGH-POWER LIGHT BEAM TO PROVIDE SIMULTANEOUS SUB-BEAMS TO PHOTOLITHOGRAPHY SCANNERS

Patent #:	9449972	Issue Dt:	09/20/2016	Application #:	14640151	Filing Dt:	03/06/2015
Publication #:	US20160260714	Pub Dt:	09/08/2016
Title:	FERROELECTRIC FINFET

Patent #:	9196700	Issue Dt:	11/24/2015	Application #:	14640698	Filing Dt:	03/06/2015
Publication #:	US20150187901	Pub Dt:	07/02/2015
Title:	MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC

Patent #:	9276118	Issue Dt:	03/01/2016	Application #:	14640851	Filing Dt:	03/06/2015
Publication #:	US20150179789	Pub Dt:	06/25/2015
Title:	FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME

Patent #:	9401373	Issue Dt:	07/26/2016	Application #:	14641462	Filing Dt:	03/09/2015
Publication #:	US20150187815	Pub Dt:	07/02/2015
Title:	MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES

Patent #:	9324656	Issue Dt:	04/26/2016	Application #:	14641551	Filing Dt:	03/09/2015
Title:	METHODS OF FORMING CONTACTS ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9412695	Issue Dt:	08/09/2016	Application #:	14641699	Filing Dt:	03/09/2015
Title:	INTERCONNECT STRUCTURES AND METHODS OF FABRICATION

Patent #:	9577099	Issue Dt:	02/21/2017	Application #:	14641917	Filing Dt:	03/09/2015
Publication #:	US20160268413	Pub Dt:	09/15/2016
Title:	DIAMOND SHAPED SOURCE DRAIN EPITAXY WITH UNDERLYING BUFFER LAYER

Patent #:	9530869	Issue Dt:	12/27/2016	Application #:	14643409	Filing Dt:	03/10/2015
Publication #:	US20160268399	Pub Dt:	09/15/2016
Title:	METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES

Patent #:	9865514	Issue Dt:	01/09/2018	Application #:	14643436	Filing Dt:	03/10/2015
Publication #:	US20150187667	Pub Dt:	07/02/2015
Title:	INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH

Patent #:	9899268	Issue Dt:	02/20/2018	Application #:	14644269	Filing Dt:	03/11/2015
Publication #:	US20160268171	Pub Dt:	09/15/2016
Title:	CAP LAYER FOR SPACER-CONSTRAINED EPITAXIALLY GROWN MATERIAL ON FINS OF A FINFET DEVICE

Patent #:	10032870	Issue Dt:	07/24/2018	Application #:	14645449	Filing Dt:	03/12/2015
Publication #:	US20160268123	Pub Dt:	09/15/2016
Title:	LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON

Patent #:	9696376	Issue Dt:	07/04/2017	Application #:	14645541	Filing Dt:	03/12/2015
Publication #:	US20160266200	Pub Dt:	09/15/2016
Title:	LEAKAGE TESTING OF INTEGRATED CIRCUITS USING A LOGARITHMIC TRANSDUCER AND A VOLTMETER

Patent #:	9844124	Issue Dt:	12/12/2017	Application #:	14645871	Filing Dt:	03/12/2015
Publication #:	US20160270200	Pub Dt:	09/15/2016
Title:	METHOD, APPARATUS AND SYSTEM FOR USING FREE-ELECTRON LASER COMPATIBLE EUV BEAM FOR SEMICONDUCTOR WAFER METROLOGY

Patent #:	9640533	Issue Dt:	05/02/2017	Application #:	14656412	Filing Dt:	03/12/2015
Publication #:	US20160268257	Pub Dt:	09/15/2016
Title:	METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LAYER WITH LATERAL OVER-GROWTH SUPPRESSION

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100

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Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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