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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 62 of 85
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Patent #:	9865546	Issue Dt:	01/09/2018	Application #:	14729298	Filing Dt:	06/03/2015
Publication #:	US20160358860	Pub Dt:	12/08/2016
Title:	CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME

Patent #:	9754941	Issue Dt:	09/05/2017	Application #:	14729845	Filing Dt:	06/03/2015
Publication #:	US20160358922	Pub Dt:	12/08/2016
Title:	METHOD AND STRUCTURE TO FORM TENSILE STRAINED SIGE FINS AND COMPRESSIVE STRAINED SIGE FINS ON A SAME SUBSTRATE

Patent #:	9768325	Issue Dt:	09/19/2017	Application #:	14730294	Filing Dt:	06/04/2015
Publication #:	US20160359056	Pub Dt:	12/08/2016
Title:	DIODES AND FABRICATION METHODS THEREOF

Patent #:	9496341	Issue Dt:	11/15/2016	Application #:	14730320	Filing Dt:	06/04/2015
Publication #:	US20160359001	Pub Dt:	12/08/2016
Title:	SILICON GERMANIUM FIN

Patent #:	9543216	Issue Dt:	01/10/2017	Application #:	14731480	Filing Dt:	06/05/2015
Publication #:	US20160358826	Pub Dt:	12/08/2016
Title:	INTEGRATION OF HYBRID GERMANIUM AND GROUP III-V CONTACT EPILAYER IN CMOS

Patent #:	9711503	Issue Dt:	07/18/2017	Application #:	14731569	Filing Dt:	06/05/2015
Publication #:	US20150270262	Pub Dt:	09/24/2015
Title:	GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH

Patent #:	9711503	Issue Dt:	07/18/2017	Application #:	14731569	Filing Dt:	06/05/2015
Publication #:	US20150270262	Pub Dt:	09/24/2015
Title:	GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH

Patent #:	NONE	Issue Dt:		Application #:	14731644	Filing Dt:	06/05/2015
Publication #:	US20150270346	Pub Dt:	09/24/2015
Title:	SEMICONDUCTOR DEVICES WITH A REPLACEMENT GATE STRUCTURE HAVING A RECESSED CHANNEL

Patent #:	9331202	Issue Dt:	05/03/2016	Application #:	14731876	Filing Dt:	06/05/2015
Publication #:	US20150364595	Pub Dt:	12/17/2015
Title:	REPLACEMENT GATE STRUCTURE ON FINFET DEVICES WITH REDUCED SIZE FIN IN THE CHANNEL REGION

Patent #:	9780178	Issue Dt:	10/03/2017	Application #:	14731960	Filing Dt:	06/05/2015
Publication #:	US20160359009	Pub Dt:	12/08/2016
Title:	METHODS OF FORMING A GATE CONTACT ABOVE AN ACTIVE REGION OF A SEMICONDUCTOR DEVICE

Patent #:	10546854	Issue Dt:	01/28/2020	Application #:	14732038	Filing Dt:	06/05/2015
Publication #:	US20160358908	Pub Dt:	12/08/2016
Title:	METHODS OF FORMING V0 STRUCTURES FOR SEMICONDUCTOR DEVICES BY FORMING A PROTECTION LAYER WITH A NON-UNIFORM THICKNESS

Patent #:	9368420	Issue Dt:	06/14/2016	Application #:	14732689	Filing Dt:	06/06/2015
Publication #:	US20150270187	Pub Dt:	09/24/2015
Title:	FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES

Patent #:	9590001	Issue Dt:	03/07/2017	Application #:	14732835	Filing Dt:	06/08/2015
Publication #:	US20150303229	Pub Dt:	10/22/2015
Title:	CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING

Patent #:	9708508	Issue Dt:	07/18/2017	Application #:	14733235	Filing Dt:	06/08/2015
Publication #:	US20150267084	Pub Dt:	09/24/2015
Title:	SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF

Patent #:	9716036	Issue Dt:	07/25/2017	Application #:	14733398	Filing Dt:	06/08/2015
Publication #:	US20160358852	Pub Dt:	12/08/2016
Title:	ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH

Patent #:	9812359	Issue Dt:	11/07/2017	Application #:	14733445	Filing Dt:	06/08/2015
Publication #:	US20160358821	Pub Dt:	12/08/2016
Title:	THRU-SILICON-VIA STRUCTURES

Patent #:	9977002	Issue Dt:	05/22/2018	Application #:	14734018	Filing Dt:	06/09/2015
Publication #:	US20150268206	Pub Dt:	09/24/2015
Title:	NANOPOROUS STRUCTURES BY REACTIVE ION ETCHING

Patent #:	9276002	Issue Dt:	03/01/2016	Application #:	14734310	Filing Dt:	06/09/2015
Publication #:	US20150294973	Pub Dt:	10/15/2015
Title:	INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET

Patent #:	9853128	Issue Dt:	12/26/2017	Application #:	14735283	Filing Dt:	06/10/2015
Publication #:	US20160365451	Pub Dt:	12/15/2016
Title:	DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE

Patent #:	9613958	Issue Dt:	04/04/2017	Application #:	14735984	Filing Dt:	06/10/2015
Publication #:	US20160365346	Pub Dt:	12/15/2016
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9401312	Issue Dt:	07/26/2016	Application #:	14736769	Filing Dt:	06/11/2015
Title:	TSV REDUNDANCY SCHEME AND ARCHITECTURE USING DECODER/ENCODER

Patent #:	9337436	Issue Dt:	05/10/2016	Application #:	14736942	Filing Dt:	06/11/2015
Publication #:	US20150280157	Pub Dt:	10/01/2015
Title:	TRANSFERABLE TRANSPARENT CONDUCTIVE OXIDE

Patent #:	9595478	Issue Dt:	03/14/2017	Application #:	14737551	Filing Dt:	06/12/2015
Publication #:	US20160365288	Pub Dt:	12/15/2016
Title:	DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME

Patent #:	9553092	Issue Dt:	01/24/2017	Application #:	14738288	Filing Dt:	06/12/2015
Publication #:	US20160365347	Pub Dt:	12/15/2016
Title:	ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

Patent #:	9530843	Issue Dt:	12/27/2016	Application #:	14738336	Filing Dt:	06/12/2015
Publication #:	US20150279936	Pub Dt:	10/01/2015
Title:	FINFET HAVING AN EPITAXIALLY GROWN SEMICONDUCTOR ON THE FIN IN THE CHANNEL REGION

Patent #:	9953117	Issue Dt:	04/24/2018	Application #:	14738355	Filing Dt:	06/12/2015
Publication #:	US20150278412	Pub Dt:	10/01/2015
Title:	PLANNING ECONOMIC ENERGY DISPATCH IN ELECTRICAL GRID UNDER UNCERTAINTY

Patent #:	9431494	Issue Dt:	08/30/2016	Application #:	14739137	Filing Dt:	06/15/2015
Publication #:	US20150311302	Pub Dt:	10/29/2015
Title:	LOW INTERFACIAL DEFECT FIELD EFFECT TRANSISTOR

Patent #:	10134840	Issue Dt:	11/20/2018	Application #:	14739543	Filing Dt:	06/15/2015
Publication #:	US20160365411	Pub Dt:	12/15/2016
Title:	SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS

Patent #:	9332628	Issue Dt:	05/03/2016	Application #:	14739703	Filing Dt:	06/15/2015
Publication #:	US20150289361	Pub Dt:	10/08/2015
Title:	MICROELECTRONIC STRUCTURE INCLUDING AIR GAP

Patent #:	9741610	Issue Dt:	08/22/2017	Application #:	14740035	Filing Dt:	06/15/2015
Publication #:	US20160365277	Pub Dt:	12/15/2016
Title:	SACRIFICIAL AMORPHOUS SILICON HARD MASK FOR BEOL

Patent #:	9728615	Issue Dt:	08/08/2017	Application #:	14740872	Filing Dt:	06/16/2015
Publication #:	US20160372559	Pub Dt:	12/22/2016
Title:	FIN SHAPE CONTACTS AND METHODS FOR FORMING FIN SHAPE CONTACTS

Patent #:	9564372	Issue Dt:	02/07/2017	Application #:	14740987	Filing Dt:	06/16/2015
Publication #:	US20160372380	Pub Dt:	12/22/2016
Title:	DUAL LINER SILICIDE

Patent #:	9368506	Issue Dt:	06/14/2016	Application #:	14741528	Filing Dt:	06/17/2015
Publication #:	US20150333080	Pub Dt:	11/19/2015
Title:	INTEGRATED CIRCUITS AND METHODS FOR OPERATING INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY

Patent #:	9496234	Issue Dt:	11/15/2016	Application #:	14741802	Filing Dt:	06/17/2015
Title:	WAFER-LEVEL CHIP-SCALE PACKAGE STRUCTURE UTILIZING CONDUCTIVE POLYMER

Patent #:	9385126	Issue Dt:	07/05/2016	Application #:	14742537	Filing Dt:	06/17/2015
Publication #:	US20150287727	Pub Dt:	10/08/2015
Title:	SILICON-ON-INSULATOR FINFET WITH BULK SOURCE AND DRAIN

Patent #:	10103060	Issue Dt:	10/16/2018	Application #:	14742895	Filing Dt:	06/18/2015
Publication #:	US20160372389	Pub Dt:	12/22/2016
Title:	TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS

Patent #:	9941179	Issue Dt:	04/10/2018	Application #:	14742917	Filing Dt:	06/18/2015
Publication #:	US20160370311	Pub Dt:	12/22/2016
Title:	CAPACITIVE MEASUREMENTS OF DIVOTS IN SEMICONDUCTOR DEVICES

Patent #:	9437588	Issue Dt:	09/06/2016	Application #:	14742935	Filing Dt:	06/18/2015
Title:	MIDDLE-OF-LINE ARCHITECTURE FOR DENSE LIBRARY LAYOUT USING M0 HAND-SHAKE

Patent #:	9299590	Issue Dt:	03/29/2016	Application #:	14743030	Filing Dt:	06/18/2015
Title:	INTEGRATED MICRO-PELTIER COOLING COMPONENTS IN SILICON-ON-INSULATOR (SOI) LAYERS

Patent #:	10103068	Issue Dt:	10/16/2018	Application #:	14743208	Filing Dt:	06/18/2015
Publication #:	US20160370421	Pub Dt:	12/22/2016
Title:	DETECTING A VOID BETWEEN A VIA AND A WIRING LINE

Patent #:	9508560	Issue Dt:	11/29/2016	Application #:	14743511	Filing Dt:	06/18/2015
Publication #:	US20160372334	Pub Dt:	12/22/2016
Title:	SiARC REMOVAL WITH PLASMA ETCH AND FLUORINATED WET CHEMICAL SOLUTION COMBINATION

Patent #:	9892979	Issue Dt:	02/13/2018	Application #:	14744198	Filing Dt:	06/19/2015
Publication #:	US20160372385	Pub Dt:	12/22/2016
Title:	NON-DESTRUCTIVE DIELECTRIC LAYER THICKNESS AND DOPANT MEASURING METHOD

Patent #:	9779783	Issue Dt:	10/03/2017	Application #:	14744800	Filing Dt:	06/19/2015
Publication #:	US20160372164	Pub Dt:	12/22/2016
Title:	LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY

Patent #:	9685553	Issue Dt:	06/20/2017	Application #:	14745547	Filing Dt:	06/22/2015
Publication #:	US20160372598	Pub Dt:	12/22/2016
Title:	GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL

Patent #:	10446644	Issue Dt:	10/15/2019	Application #:	14745704	Filing Dt:	06/22/2015
Publication #:	US20160372582	Pub Dt:	12/22/2016
Title:	DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER

Patent #:	9728603	Issue Dt:	08/08/2017	Application #:	14745764	Filing Dt:	06/22/2015
Publication #:	US20160372548	Pub Dt:	12/22/2016
Title:	BIPOLAR JUNCTION TRANSISTORS WITH DOUBLE-TAPERED EMITTER FINGERS

Patent #:	9461042	Issue Dt:	10/04/2016	Application #:	14746017	Filing Dt:	06/22/2015
Publication #:	US20150287721	Pub Dt:	10/08/2015
Title:	SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY

Patent #:	9576899	Issue Dt:	02/21/2017	Application #:	14746891	Filing Dt:	06/23/2015
Publication #:	US20160379930	Pub Dt:	12/29/2016
Title:	ELECTRICAL FUSE WITH HIGH OFF RESISTANCE

Patent #:	9496377	Issue Dt:	11/15/2016	Application #:	14747525	Filing Dt:	06/23/2015
Publication #:	US20150311324	Pub Dt:	10/29/2015
Title:	SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE

Patent #:	9722057	Issue Dt:	08/01/2017	Application #:	14747668	Filing Dt:	06/23/2015
Publication #:	US20160380088	Pub Dt:	12/29/2016
Title:	BIPOLAR JUNCTION TRANSISTORS WITH A BURIED DIELECTRIC REGION IN THE ACTIVE DEVICE REGION

Patent #:	9530798	Issue Dt:	12/27/2016	Application #:	14748355	Filing Dt:	06/24/2015
Publication #:	US20160379999	Pub Dt:	12/29/2016
Title:	HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE

Patent #:	9691971	Issue Dt:	06/27/2017	Application #:	14749165	Filing Dt:	06/24/2015
Publication #:	US20160190207	Pub Dt:	06/30/2016
Title:	INTEGRATED CIRCUITS INCLUDING MAGNETIC TUNNEL JUNCTIONS FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME

Patent #:	9287180	Issue Dt:	03/15/2016	Application #:	14749245	Filing Dt:	06/24/2015
Publication #:	US20150294915	Pub Dt:	10/15/2015
Title:	INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME

Patent #:	9606291	Issue Dt:	03/28/2017	Application #:	14749907	Filing Dt:	06/25/2015
Publication #:	US20160377806	Pub Dt:	12/29/2016
Title:	MULTILEVEL WAVEGUIDE STRUCTURE

Patent #:	9690898	Issue Dt:	06/27/2017	Application #:	14749909	Filing Dt:	06/25/2015
Publication #:	US20160378902	Pub Dt:	12/29/2016
Title:	GENERATIVE LEARNING FOR REALISTIC AND GROUND RULE CLEAN HOT SPOT SYNTHESIS

Patent #:	9748270	Issue Dt:	08/29/2017	Application #:	14750236	Filing Dt:	06/25/2015
Publication #:	US20160379993	Pub Dt:	12/29/2016
Title:	TUNABLE CAPACITOR FOR FDSOI APPLICATIONS

Patent #:	9558995	Issue Dt:	01/31/2017	Application #:	14750741	Filing Dt:	06/25/2015
Publication #:	US20160379873	Pub Dt:	12/29/2016
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	9324795	Issue Dt:	04/26/2016	Application #:	14751493	Filing Dt:	06/26/2015
Publication #:	US20150303257	Pub Dt:	10/22/2015
Title:	GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION

Patent #:	9293532	Issue Dt:	03/22/2016	Application #:	14751542	Filing Dt:	06/26/2015
Publication #:	US20150325664	Pub Dt:	11/12/2015
Title:	GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION

Patent #:	9805990	Issue Dt:	10/31/2017	Application #:	14751557	Filing Dt:	06/26/2015
Publication #:	US20160380100	Pub Dt:	12/29/2016
Title:	FDSOI VOLTAGE REFERENCE

Patent #:	9324796	Issue Dt:	04/26/2016	Application #:	14751646	Filing Dt:	06/26/2015
Publication #:	US20150295037	Pub Dt:	10/15/2015
Title:	Gate-All-Around Nanowire MOSFET and Method of Formation

Patent #:	9299777	Issue Dt:	03/29/2016	Application #:	14751706	Filing Dt:	06/26/2015
Publication #:	US20150295038	Pub Dt:	10/15/2015
Title:	Gate-All-Around Nanowire MOSFET and Method of Formation

Patent #:	9324797	Issue Dt:	04/26/2016	Application #:	14751761	Filing Dt:	06/26/2015
Publication #:	US20150295039	Pub Dt:	10/15/2015
Title:	Gate-All-Around Nanowire MOSFET and Method of Formation

Patent #:	9391065	Issue Dt:	07/12/2016	Application #:	14753628	Filing Dt:	06/29/2015
Title:	ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE

Patent #:	9659131	Issue Dt:	05/23/2017	Application #:	14754585	Filing Dt:	06/29/2015
Publication #:	US20150317423	Pub Dt:	11/05/2015
Title:	Copper Feature Design for Warpage Control of Substrates

Patent #:	9659941	Issue Dt:	05/23/2017	Application #:	14754958	Filing Dt:	06/30/2015
Publication #:	US20170005101	Pub Dt:	01/05/2017
Title:	INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME

Patent #:	9991202	Issue Dt:	06/05/2018	Application #:	14755440	Filing Dt:	06/30/2015
Publication #:	US20170005037	Pub Dt:	01/05/2017
Title:	METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM

Patent #:	9843303	Issue Dt:	12/12/2017	Application #:	14755522	Filing Dt:	06/30/2015
Publication #:	US20150318839	Pub Dt:	11/05/2015
Title:	SWITCHABLE FILTERS AND DESIGN STRUCTURES

Patent #:	10288645	Issue Dt:	05/14/2019	Application #:	14755733	Filing Dt:	06/30/2015
Publication #:	US20170003318	Pub Dt:	01/05/2017
Title:	ORGANIC PROBE SUBSTRATE

Patent #:	9601379	Issue Dt:	03/21/2017	Application #:	14757996	Filing Dt:	12/23/2015
Title:	METHODS OF FORMING METAL SOURCE/DRAIN CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES WITH GATE ALL AROUND CHANNEL STRUCTURES

Patent #:	9910348	Issue Dt:	03/06/2018	Application #:	14788296	Filing Dt:	06/30/2015
Publication #:	US20170004233	Pub Dt:	01/05/2017
Title:	METHOD OF SIMULTANEOUS LITHOGRAPHY AND ETCH CORRECTION FLOW

Patent #:	9425129	Issue Dt:	08/23/2016	Application #:	14789160	Filing Dt:	07/01/2015
Title:	METHODS FOR FABRICATING CONDUCTIVE VIAS OF CIRCUIT STRUCTURES

Patent #:	9680020	Issue Dt:	06/13/2017	Application #:	14794997	Filing Dt:	07/09/2015
Publication #:	US20170012129	Pub Dt:	01/12/2017
Title:	INCREASED CONTACT AREA FOR FINFETS

Patent #:	9356149	Issue Dt:	05/31/2016	Application #:	14795716	Filing Dt:	07/09/2015
Publication #:	US20160005867	Pub Dt:	01/07/2016
Title:	SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES

Patent #:	9583584	Issue Dt:	02/28/2017	Application #:	14795984	Filing Dt:	07/10/2015
Publication #:	US20170012107	Pub Dt:	01/12/2017
Title:	METHODS FOR PRODUCING INTEGRATED CIRCUITS USING LONG AND SHORT REGIONS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS

Patent #:	9455331	Issue Dt:	09/27/2016	Application #:	14796646	Filing Dt:	07/10/2015
Title:	METHOD AND STRUCTURE OF FORMING CONTROLLABLE UNMERGED EPITAXIAL MATERIAL

Patent #:	9831098	Issue Dt:	11/28/2017	Application #:	14797337	Filing Dt:	07/13/2015
Publication #:	US20170018452	Pub Dt:	01/19/2017
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING FLOWABLE CHEMICAL VAPOR DEPOSITION TECHNIQUES WITH LOW-TEMPERATURE THERMAL ANNEALING

Patent #:	9406651	Issue Dt:	08/02/2016	Application #:	14797804	Filing Dt:	07/13/2015
Publication #:	US20150318269	Pub Dt:	11/05/2015
Title:	Chip Stack with Oleic Acid-Aligned Nanotubes in Thermal Interface Material

Patent #:	9659786	Issue Dt:	05/23/2017	Application #:	14799297	Filing Dt:	07/14/2015
Publication #:	US20170018437	Pub Dt:	01/19/2017
Title:	GATE CUT WITH HIGH SELECTIVITY TO PRESERVE INTERLEVEL DIELECTRIC LAYER

Patent #:	9589851	Issue Dt:	03/07/2017	Application #:	14800970	Filing Dt:	07/16/2015
Publication #:	US20170018463	Pub Dt:	01/19/2017
Title:	Dipole-Based Contact Structure to Reduce Metal-Semiconductor Contact Resistance in MOSFETs

Patent #:	9601512	Issue Dt:	03/21/2017	Application #:	14801519	Filing Dt:	07/16/2015
Publication #:	US20170018573	Pub Dt:	01/19/2017
Title:	SOI-BASED SEMICONDUCTOR DEVICE WITH DYNAMIC THRESHOLD VOLTAGE

Patent #:	9806067	Issue Dt:	10/31/2017	Application #:	14803466	Filing Dt:	07/20/2015
Publication #:	US20170025398	Pub Dt:	01/26/2017
Title:	DIE-DIE STACKING

Patent #:	9337281	Issue Dt:	05/10/2016	Application #:	14803910	Filing Dt:	07/20/2015
Publication #:	US20150325682	Pub Dt:	11/12/2015
Title:	PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL

Patent #:	9293363	Issue Dt:	03/22/2016	Application #:	14805443	Filing Dt:	07/21/2015
Publication #:	US20150332959	Pub Dt:	11/19/2015
Title:	METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION

Patent #:	9570318	Issue Dt:	02/14/2017	Application #:	14805527	Filing Dt:	07/22/2015
Publication #:	US20170025285	Pub Dt:	01/26/2017
Title:	HIGH-K AND P-TYPE WORK FUNCTION METAL FIRST FABRICATION PROCESS HAVING IMPROVED ANNEALING PROCESS FLOWS

Patent #:	9711346	Issue Dt:	07/18/2017	Application #:	14807289	Filing Dt:	07/23/2015
Publication #:	US20170025270	Pub Dt:	01/26/2017
Title:	METHOD TO FABRICATE A HIGH PERFORMANCE CAPACITOR IN A BACK END OF LINE (BEOL)

Patent #:	9536035	Issue Dt:	01/03/2017	Application #:	14809698	Filing Dt:	07/27/2015
Publication #:	US20150331988	Pub Dt:	11/19/2015
Title:	WIDE PIN FOR IMPROVED CIRCUIT ROUTING

Patent #:	9431520	Issue Dt:	08/30/2016	Application #:	14810017	Filing Dt:	07/27/2015
Publication #:	US20150333157	Pub Dt:	11/19/2015
Title:	GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SIC FINS OR NANOWIRE TEMPLATES

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100

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Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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