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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 66 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
10056486
Issue Dt:
08/21/2018
Application #:
15079142
Filing Dt:
03/24/2016
Publication #:
US20170278965
Pub Dt:
09/28/2017
Title:
METHODS FOR FIN THINNING PROVIDING IMPROVED SCE AND S/D EPI GROWTH
2
Patent #:
10367083
Issue Dt:
07/30/2019
Application #:
15081443
Filing Dt:
03/25/2016
Publication #:
US20170278955
Pub Dt:
09/28/2017
Title:
COMPACT DEVICE STRUCTURES FOR A BIPOLAR JUNCTION TRANSISTOR
3
Patent #:
10388790
Issue Dt:
08/20/2019
Application #:
15082103
Filing Dt:
03/28/2016
Publication #:
US20160211375
Pub Dt:
07/21/2016
Title:
FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING
4
Patent #:
9837404
Issue Dt:
12/05/2017
Application #:
15082242
Filing Dt:
03/28/2016
Publication #:
US20170278844
Pub Dt:
09/28/2017
Title:
METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES
5
Patent #:
10732202
Issue Dt:
08/04/2020
Application #:
15083787
Filing Dt:
03/29/2016
Publication #:
US20170285068
Pub Dt:
10/05/2017
Title:
REPAIRABLE RIGID TEST PROBE CARD ASSEMBLY
6
Patent #:
9953900
Issue Dt:
04/24/2018
Application #:
15083914
Filing Dt:
03/29/2016
Publication #:
US20170287812
Pub Dt:
10/05/2017
Title:
TRANSISTOR STRUCTURES GATED USING A CONDUCTOR-FILLED VIA OR TRENCH
7
Patent #:
9881122
Issue Dt:
01/30/2018
Application #:
15084576
Filing Dt:
03/30/2016
Publication #:
US20170286586
Pub Dt:
10/05/2017
Title:
OVERLAY SAMPLING REDUCTION
8
Patent #:
9853055
Issue Dt:
12/26/2017
Application #:
15084807
Filing Dt:
03/30/2016
Publication #:
US20170287942
Pub Dt:
10/05/2017
Title:
METHOD TO IMPROVE CRYSTALLINE REGROWTH
9
Patent #:
9991167
Issue Dt:
06/05/2018
Application #:
15085077
Filing Dt:
03/30/2016
Publication #:
US20170287829
Pub Dt:
10/05/2017
Title:
METHOD AND IC STRUCTURE FOR INCREASING PITCH BETWEEN GATES
10
Patent #:
9425292
Issue Dt:
08/23/2016
Application #:
15085112
Filing Dt:
03/30/2016
Title:
FIELD EFFECT TRANSISTOR DEVICE SPACERS
11
Patent #:
9472670
Issue Dt:
10/18/2016
Application #:
15085376
Filing Dt:
03/30/2016
Title:
FIELD EFFECT TRANSISTOR DEVICE SPACERS
12
Patent #:
9711618
Issue Dt:
07/18/2017
Application #:
15087074
Filing Dt:
03/31/2016
Title:
FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
13
Patent #:
9633857
Issue Dt:
04/25/2017
Application #:
15087392
Filing Dt:
03/31/2016
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A TRENCH CAPPING LAYER AND METHOD FOR THE FORMATION THEREOF
14
Patent #:
9935106
Issue Dt:
04/03/2018
Application #:
15088874
Filing Dt:
04/01/2016
Publication #:
US20170287911
Pub Dt:
10/05/2017
Title:
MULTI-FINGER DEVICES IN MUTLIPLE-GATE-CONTACTED-PITCH, INTEGRATED STRUCTURES
15
Patent #:
9660105
Issue Dt:
05/23/2017
Application #:
15089647
Filing Dt:
04/04/2016
Publication #:
US20160218222
Pub Dt:
07/28/2016
Title:
FINFET CROSSPOINT FLASH MEMORY
16
Patent #:
9824920
Issue Dt:
11/21/2017
Application #:
15089834
Filing Dt:
04/04/2016
Publication #:
US20170287780
Pub Dt:
10/05/2017
Title:
METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES BY WORK FUNCTION MATERIAL LAYER RECESSING AND THE RESULTING DEVICES
17
Patent #:
9786657
Issue Dt:
10/10/2017
Application #:
15089914
Filing Dt:
04/04/2016
Publication #:
US20170287901
Pub Dt:
10/05/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR INCLUDING A GATE ELECTRODE REGION PROVIDED IN A SUBSTRATE AND METHOD FOR THE FORMATION THEREOF
18
Patent #:
9876111
Issue Dt:
01/23/2018
Application #:
15091020
Filing Dt:
04/05/2016
Publication #:
US20170170317
Pub Dt:
06/15/2017
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE USING DIFFERING SPACER WIDTHS AND THE RESULTING SEMICONDUCTOR DEVICE STRUCTURE
19
Patent #:
9831123
Issue Dt:
11/28/2017
Application #:
15091138
Filing Dt:
04/05/2016
Publication #:
US20170287777
Pub Dt:
10/05/2017
Title:
METHODS OF FORMING MIS CONTACT STRUCTURES ON TRANSISTOR DEVICES
20
Patent #:
NONE
Issue Dt:
Application #:
15091910
Filing Dt:
04/06/2016
Publication #:
US20160225901
Pub Dt:
08/04/2016
Title:
SEMICONDUCTOR STRUCTURE HAVING FINFET ULTRA THIN BODY
21
Patent #:
9991366
Issue Dt:
06/05/2018
Application #:
15092039
Filing Dt:
04/06/2016
Publication #:
US20160218198
Pub Dt:
07/28/2016
Title:
ANCHORED STRESS-GENERATING ACTIVE SEMICONDUCTOR REGIONS FOR SEMICONDUCTOR-ON-INSULATOR FINFET
22
Patent #:
10347748
Issue Dt:
07/09/2019
Application #:
15092168
Filing Dt:
04/06/2016
Publication #:
US20170294522
Pub Dt:
10/12/2017
Title:
METHODS OF FORMING SOURCE/DRAIN REGIONS ON FINFET DEVICES
23
Patent #:
9553032
Issue Dt:
01/24/2017
Application #:
15092233
Filing Dt:
04/06/2016
Publication #:
US20160218043
Pub Dt:
07/28/2016
Title:
FIN FIELD EFFECT TRANSISTOR INCLUDING ASYMMETRIC RAISED ACTIVE REGIONS
24
Patent #:
9721834
Issue Dt:
08/01/2017
Application #:
15092272
Filing Dt:
04/06/2016
Publication #:
US20160380078
Pub Dt:
12/29/2016
Title:
HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
25
Patent #:
9806161
Issue Dt:
10/31/2017
Application #:
15092910
Filing Dt:
04/07/2016
Publication #:
US20170294519
Pub Dt:
10/12/2017
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING THIN GATE DIELECTRIC DEVICE AND THICK GATE DIELECTRIC DEVICE
26
Patent #:
9852900
Issue Dt:
12/26/2017
Application #:
15093212
Filing Dt:
04/07/2016
Publication #:
US20170294304
Pub Dt:
10/12/2017
Title:
OXIDIZING FILLER MATERIAL LINES TO INCREASE WIDTH OF HARD MASK LINES
27
Patent #:
9799514
Issue Dt:
10/24/2017
Application #:
15093292
Filing Dt:
04/07/2016
Publication #:
US20170294308
Pub Dt:
10/12/2017
Title:
PROTECTING, OXIDIZING, AND ETCHING OF MATERIAL LINES FOR USE IN INCREASING OR DECREASING CRITICAL DIMENSIONS OF HARD MASK LINES
28
Patent #:
10068766
Issue Dt:
09/04/2018
Application #:
15093310
Filing Dt:
04/07/2016
Publication #:
US20170294309
Pub Dt:
10/12/2017
Title:
OXIDIZING AND ETCHING OF MATERIAL LINES FOR USE IN INCREASING OR DECREASING CRITICAL DIMENSIONS OF HARD MASK LINES
29
Patent #:
9659835
Issue Dt:
05/23/2017
Application #:
15094026
Filing Dt:
04/08/2016
Title:
TECHNIQUES FOR INTEGRATING THERMAL VIA STRUCTURES IN INTEGRATED CIRCUITS
30
Patent #:
9916415
Issue Dt:
03/13/2018
Application #:
15095239
Filing Dt:
04/11/2016
Publication #:
US20170293709
Pub Dt:
10/12/2017
Title:
INTEGRATED CIRCUIT PERFORMANCE MODELING THAT INCLUDES SUBSTRATE-GENERATED SIGNAL DISTORTIONS
31
Patent #:
9698226
Issue Dt:
07/04/2017
Application #:
15095376
Filing Dt:
04/11/2016
Title:
RECESS LINER FOR SILICON GERMANIUM FIN FORMATION
32
Patent #:
9666488
Issue Dt:
05/30/2017
Application #:
15095612
Filing Dt:
04/11/2016
Title:
PASS-THROUGH CONTACT USING SILICIDE
33
Patent #:
9966374
Issue Dt:
05/08/2018
Application #:
15096681
Filing Dt:
04/12/2016
Publication #:
US20160225766
Pub Dt:
08/04/2016
Title:
Semiconductor Device with Gate Structures having Low-K Spacers on Sidewalls and Electrical Contacts therebetween
34
Patent #:
9530863
Issue Dt:
12/27/2016
Application #:
15097574
Filing Dt:
04/13/2016
Title:
METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH SELF-ALIGNED REPLACEMENT GATE STRUCTURES
35
Patent #:
9530866
Issue Dt:
12/27/2016
Application #:
15097621
Filing Dt:
04/13/2016
Title:
METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH SELF-ALIGNED TOP SOURCE/DRAIN CONDUCTIVE CONTACTS
36
Patent #:
9666524
Issue Dt:
05/30/2017
Application #:
15098513
Filing Dt:
04/14/2016
Publication #:
US20160225712
Pub Dt:
08/04/2016
Title:
ELECTRO-MIGRATION ENHANCING METHOD FOR SELF-FORMING BARRIER PROCESS IN COPPER METTALIZATION
37
Patent #:
10068920
Issue Dt:
09/04/2018
Application #:
15098722
Filing Dt:
04/14/2016
Publication #:
US20170301697
Pub Dt:
10/19/2017
Title:
SILICON GERMANIUM FINS ON INSULATOR FORMED BY LATERAL RECRYSTALLIZATION
38
Patent #:
10020202
Issue Dt:
07/10/2018
Application #:
15099641
Filing Dt:
04/15/2016
Publication #:
US20170301551
Pub Dt:
10/19/2017
Title:
FABRICATION OF MULTI THRESHOLD-VOLTAGE DEVICES
39
Patent #:
10516767
Issue Dt:
12/24/2019
Application #:
15131174
Filing Dt:
04/18/2016
Publication #:
US20170302764
Pub Dt:
10/19/2017
Title:
UNIFYING REALTIME AND STATIC DATA FOR PRESENTING OVER A WEB SERVICE
40
Patent #:
9799751
Issue Dt:
10/24/2017
Application #:
15132383
Filing Dt:
04/19/2016
Publication #:
US20170301776
Pub Dt:
10/19/2017
Title:
METHODS OF FORMING A GATE STRUCTURE ON A VERTICAL TRANSISTOR DEVICE
41
Patent #:
9698018
Issue Dt:
07/04/2017
Application #:
15132589
Filing Dt:
04/19/2016
Title:
INTRODUCING SELF-ALIGNED DOPANTS IN SEMICONDUCTOR FINS
42
Patent #:
10115718
Issue Dt:
10/30/2018
Application #:
15134942
Filing Dt:
04/21/2016
Publication #:
US20170309615
Pub Dt:
10/26/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION
43
Patent #:
9536793
Issue Dt:
01/03/2017
Application #:
15135917
Filing Dt:
04/22/2016
Title:
SELF-ALIGNED GATE-FIRST VFETs USING A GATE SPACER RECESS
44
Patent #:
10262941
Issue Dt:
04/16/2019
Application #:
15136384
Filing Dt:
04/22/2016
Publication #:
US20170309560
Pub Dt:
10/26/2017
Title:
DEVICES AND METHODS FOR FORMING CROSS COUPLED CONTACTS
45
Patent #:
9818689
Issue Dt:
11/14/2017
Application #:
15137362
Filing Dt:
04/25/2016
Publication #:
US20170309563
Pub Dt:
10/26/2017
Title:
METAL-INSULATOR-METAL CAPACITOR AND METHODS OF FABRICATION
46
Patent #:
9627317
Issue Dt:
04/18/2017
Application #:
15137740
Filing Dt:
04/25/2016
Publication #:
US20160240473
Pub Dt:
08/18/2016
Title:
WAFER WITH IMPROVED PLATING CURRENT DISTRIBUTION
47
Patent #:
9741713
Issue Dt:
08/22/2017
Application #:
15138954
Filing Dt:
04/26/2016
Title:
PARASITIC LATERAL BIPOLAR TRANSISTOR WITH IMPROVED IDEALITY AND LEAKAGE CURRENTS
48
Patent #:
9793262
Issue Dt:
10/17/2017
Application #:
15139644
Filing Dt:
04/27/2016
Publication #:
US20170317071
Pub Dt:
11/02/2017
Title:
FIN DIODE WITH INCREASED JUNCTION AREA
49
Patent #:
9946152
Issue Dt:
04/17/2018
Application #:
15139994
Filing Dt:
04/27/2016
Publication #:
US20170315438
Pub Dt:
11/02/2017
Title:
EXTREME ULTRAVIOLET LITHOGRAPHY PHOTOMASKS
50
Patent #:
9818652
Issue Dt:
11/14/2017
Application #:
15140025
Filing Dt:
04/27/2016
Publication #:
US20170316986
Pub Dt:
11/02/2017
Title:
COMMONLY-BODIED FIELD-EFFECT TRANSISTORS
51
Patent #:
9633946
Issue Dt:
04/25/2017
Application #:
15140121
Filing Dt:
04/27/2016
Title:
SEAMLESS METALLIZATION CONTACTS
52
Patent #:
10108771
Issue Dt:
10/23/2018
Application #:
15140183
Filing Dt:
04/27/2016
Publication #:
US20170316140
Pub Dt:
11/02/2017
Title:
METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS WITH TRIPLE PATTERNED METAL LAYER STRUCTURES
53
Patent #:
9704852
Issue Dt:
07/11/2017
Application #:
15140516
Filing Dt:
04/28/2016
Publication #:
US20160379972
Pub Dt:
12/29/2016
Title:
ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERTICAL GATE FIN-TYPE FIELD EFFECT DIODE
54
Patent #:
9530780
Issue Dt:
12/27/2016
Application #:
15140548
Filing Dt:
04/28/2016
Publication #:
US20160322367
Pub Dt:
11/03/2016
Title:
MEMORY BIT CELL FOR REDUCED LAYOUT AREA
55
Patent #:
9691775
Issue Dt:
06/27/2017
Application #:
15141087
Filing Dt:
04/28/2016
Title:
COMBINED SADP FINS FOR SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME
56
Patent #:
9941348
Issue Dt:
04/10/2018
Application #:
15142332
Filing Dt:
04/29/2016
Publication #:
US20170317161
Pub Dt:
11/02/2017
Title:
METHOD OF FORMING A CAPACITOR STRUCTURE AND CAPACITOR STRUCTURE
57
Patent #:
9761525
Issue Dt:
09/12/2017
Application #:
15142525
Filing Dt:
04/29/2016
Title:
MULTIPLE BACK GATE TRANSISTOR
58
Patent #:
9548306
Issue Dt:
01/17/2017
Application #:
15144924
Filing Dt:
05/03/2016
Publication #:
US20160247805
Pub Dt:
08/25/2016
Title:
METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURE WITH N-TYPE AND P-TYPE FIELD EFFECT TRANSISTORS HAVING SYMMETRIC SOURCE/DRAIN JUNCTIONS AND OPTIONAL DUAL SILICIDES
59
Patent #:
9728509
Issue Dt:
08/08/2017
Application #:
15147525
Filing Dt:
05/05/2016
Title:
LASER SCRIBE STRUCTURES FOR A WAFER
60
Patent #:
10043962
Issue Dt:
08/07/2018
Application #:
15147595
Filing Dt:
05/05/2016
Publication #:
US20170324015
Pub Dt:
11/09/2017
Title:
THERMOELECTRIC COOLING USING THROUGH-SILICON VIAS
61
Patent #:
9923527
Issue Dt:
03/20/2018
Application #:
15148668
Filing Dt:
05/06/2016
Publication #:
US20170324385
Pub Dt:
11/09/2017
Title:
METHOD, APPARATUS AND SYSTEM FOR BACK GATE BIASING FOR FD-SOI DEVICES
62
Patent #:
9755015
Issue Dt:
09/05/2017
Application #:
15150977
Filing Dt:
05/10/2016
Title:
AIR GAPS FORMED BY POROUS SILICON REMOVAL
63
Patent #:
9806170
Issue Dt:
10/31/2017
Application #:
15151550
Filing Dt:
05/11/2016
Publication #:
US20170330953
Pub Dt:
11/16/2017
Title:
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPACER WIDTHS & DUAL RAISED SOURCE DRAIN EXPITAXIAL SILICON AND TRIPLE-NITRIDE SPACER INTEGRATION ENABLING HIGH-VOLTAGE EG DEVICE ON FDSOI
64
Patent #:
9799660
Issue Dt:
10/24/2017
Application #:
15151622
Filing Dt:
05/11/2016
Publication #:
US20170330883
Pub Dt:
11/16/2017
Title:
STABLE AND RELIABLE FINFET SRAM WITH IMPROVED BETA RATIO
65
Patent #:
9583397
Issue Dt:
02/28/2017
Application #:
15151720
Filing Dt:
05/11/2016
Title:
SOURCE/DRAIN TERMINAL CONTACT AND METHOD OF FORMING SAME
66
Patent #:
10211146
Issue Dt:
02/19/2019
Application #:
15152794
Filing Dt:
05/12/2016
Publication #:
US20170330832
Pub Dt:
11/16/2017
Title:
AIR GAP OVER TRANSISTOR GATE AND RELATED METHOD
67
Patent #:
10157777
Issue Dt:
12/18/2018
Application #:
15152797
Filing Dt:
05/12/2016
Publication #:
US20170330790
Pub Dt:
11/16/2017
Title:
AIR GAP OVER TRANSISTOR GATE AND RELATED METHOD
68
Patent #:
9614047
Issue Dt:
04/04/2017
Application #:
15153249
Filing Dt:
05/12/2016
Publication #:
US20160260812
Pub Dt:
09/08/2016
Title:
GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN
69
Patent #:
9812573
Issue Dt:
11/07/2017
Application #:
15153831
Filing Dt:
05/13/2016
Publication #:
US20170330970
Pub Dt:
11/16/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING STRESS CREATING REGIONS AND METHOD FOR THE FORMATION THEREOF
70
Patent #:
10115621
Issue Dt:
10/30/2018
Application #:
15153936
Filing Dt:
05/13/2016
Publication #:
US20170330782
Pub Dt:
11/16/2017
Title:
METHOD FOR IN-DIE OVERLAY CONTROL USING FEOL DUMMY FILL LAYER
71
Patent #:
10062689
Issue Dt:
08/28/2018
Application #:
15154087
Filing Dt:
05/13/2016
Publication #:
US20170330878
Pub Dt:
11/16/2017
Title:
NOVEL METHOD TO FABRICATE VERTICAL FIN FIELD-EFFECT-TRANSISTORS
72
Patent #:
9812400
Issue Dt:
11/07/2017
Application #:
15154367
Filing Dt:
05/13/2016
Publication #:
US20170330834
Pub Dt:
11/16/2017
Title:
CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME
73
Patent #:
9875334
Issue Dt:
01/23/2018
Application #:
15155425
Filing Dt:
05/16/2016
Publication #:
US20170329886
Pub Dt:
11/16/2017
Title:
GENERATING MANUFACTURABLE SUB-RESOLUTION ASSIST FEATURE SHAPES FROM A USEFULNESS MAP
74
Patent #:
9922986
Issue Dt:
03/20/2018
Application #:
15155483
Filing Dt:
05/16/2016
Publication #:
US20170330889
Pub Dt:
11/16/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF PAIRS OF NONVOLATILE MEMORY CELLS AND AN EDGE CELL AND METHOD FOR THE FORMATION THEREOF
75
Patent #:
10388729
Issue Dt:
08/20/2019
Application #:
15155761
Filing Dt:
05/16/2016
Publication #:
US20170330934
Pub Dt:
11/16/2017
Title:
DEVICES AND METHODS OF FORMING SELF-ALIGNED, UNIFORM NANO SHEET SPACERS
76
Patent #:
9673222
Issue Dt:
06/06/2017
Application #:
15156506
Filing Dt:
05/17/2016
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US20160260742
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Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
10/22/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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