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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 68 of 85
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Patent #:	9646885	Issue Dt:	05/09/2017	Application #:	15224091	Filing Dt:	07/29/2016
Title:	METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES BY PERFORMING PLASMA NITRIDATION PROCESS ON FIN ENDS

Patent #:	10008577	Issue Dt:	06/26/2018	Application #:	15225152	Filing Dt:	08/01/2016
Publication #:	US20180033863	Pub Dt:	02/01/2018
Title:	METHODS OF FORMING AN AIR-GAP SPACER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9653583	Issue Dt:	05/16/2017	Application #:	15226165	Filing Dt:	08/02/2016
Title:	METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES

Patent #:	9899375	Issue Dt:	02/20/2018	Application #:	15226575	Filing Dt:	08/02/2016
Publication #:	US20180040611	Pub Dt:	02/08/2018
Title:	CO-INTEGRATION OF SELF-ALIGNED AND NON-SELF ALIGNED HETEROJUNCTION BIPOLAR TRANSISTORS

Patent #:	10340288	Issue Dt:	07/02/2019	Application #:	15226867	Filing Dt:	08/02/2016
Publication #:	US20180040631	Pub Dt:	02/08/2018
Title:	METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVING UNIDIRECTIONAL LAYOUT USING SELF-ALIGNED DOUBLE PATTERNING

Patent #:	9882081	Issue Dt:	01/30/2018	Application #:	15227081	Filing Dt:	08/03/2016
Publication #:	US20170062647	Pub Dt:	03/02/2017
Title:	PHOTODETECTOR METHODS AND PHOTODETECTOR STRUCTURES

Patent #:	10170319	Issue Dt:	01/01/2019	Application #:	15227142	Filing Dt:	08/03/2016
Publication #:	US20170047226	Pub Dt:	02/16/2017
Title:	FORMING A CONTACT FOR A TALL FIN TRANSISTOR

Patent #:	9966433	Issue Dt:	05/08/2018	Application #:	15227330	Filing Dt:	08/03/2016
Publication #:	US20180040696	Pub Dt:	02/08/2018
Title:	MULTIPLE-STEP EPITAXIAL GROWTH S/D REGIONS FOR NMOS FINFET

Patent #:	9917009	Issue Dt:	03/13/2018	Application #:	15228317	Filing Dt:	08/04/2016
Publication #:	US20180040511	Pub Dt:	02/08/2018
Title:	METHODS OF FORMING A THROUGH-SUBSTRATE-VIA (TSV) AND A METALLIZATION LAYER AFTER FORMATION OF A SEMICONDUCTOR DEVICE

Patent #:	10030971	Issue Dt:	07/24/2018	Application #:	15228772	Filing Dt:	08/04/2016
Publication #:	US20170038201	Pub Dt:	02/09/2017
Title:	MEASUREMENT SYSTEM AND METHOD FOR MEASURING IN THIN FILMS

Patent #:	9825031	Issue Dt:	11/21/2017	Application #:	15229292	Filing Dt:	08/05/2016
Title:	METHODS OF FORMING A HIGH-K CONTACT LINER TO IMPROVE EFFECTIVE VIA SEPARATION DISTANCE AND THE RESULTING DEVICES

Patent #:	9966313	Issue Dt:	05/08/2018	Application #:	15229431	Filing Dt:	08/05/2016
Publication #:	US20180040516	Pub Dt:	02/08/2018
Title:	FINFET DEVICE AND METHOD OF MANUFACTURING

Patent #:	9966466	Issue Dt:	05/08/2018	Application #:	15231105	Filing Dt:	08/08/2016
Publication #:	US20180040731	Pub Dt:	02/08/2018
Title:	SEMICONDUCTOR-ON-INSULATOR WAFER, SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR, AND METHODS FOR THE FORMATION AND OPERATION THEREOF

Patent #:	9864136	Issue Dt:	01/09/2018	Application #:	15231840	Filing Dt:	08/09/2016
Title:	NON-PLANAR MONOLITHIC HYBRID OPTOELECTRONIC STRUCTURES AND METHODS

Patent #:	10062619	Issue Dt:	08/28/2018	Application #:	15232090	Filing Dt:	08/09/2016
Publication #:	US20180047642	Pub Dt:	02/15/2018
Title:	AIR GAP SPACER IMPLANT FOR NZG RELIABILITY FIX

Patent #:	9711648	Issue Dt:	07/18/2017	Application #:	15232164	Filing Dt:	08/09/2016
Title:	STRUCTURE AND METHOD FOR CMP-FREE III-V ISOLATION

Patent #:	9824933	Issue Dt:	11/21/2017	Application #:	15232174	Filing Dt:	08/09/2016
Title:	STACKED VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS

Patent #:	9564440	Issue Dt:	02/07/2017	Application #:	15232246	Filing Dt:	08/09/2016
Publication #:	US20160365348	Pub Dt:	12/15/2016
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9780185	Issue Dt:	10/03/2017	Application #:	15232300	Filing Dt:	08/09/2016
Publication #:	US20160365290	Pub Dt:	12/15/2016
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9768028	Issue Dt:	09/19/2017	Application #:	15232873	Filing Dt:	08/10/2016
Title:	SEMICONDUCTOR STRUCTURE WITH A DOPANT IMPLANT REGION HAVING A LINEARLY GRADED CONDUCTIVITY LEVEL AND METHOD OF FORMING THE STRUCTURE

Patent #:	9871050	Issue Dt:	01/16/2018	Application #:	15232906	Filing Dt:	08/10/2016
Title:	FLASH MEMORY DEVICE

Patent #:	9773881	Issue Dt:	09/26/2017	Application #:	15233315	Filing Dt:	08/10/2016
Publication #:	US20170125539	Pub Dt:	05/04/2017
Title:	ETCH STOP FOR AIRGAP PROTECTION

Patent #:	10931143	Issue Dt:	02/23/2021	Application #:	15233454	Filing Dt:	08/10/2016
Publication #:	US20180048169	Pub Dt:	02/15/2018
Title:	RECHARGEABLE WAFER CARRIER SYSTEMS

Patent #:	9972634	Issue Dt:	05/15/2018	Application #:	15234066	Filing Dt:	08/11/2016
Publication #:	US20180047738	Pub Dt:	02/15/2018
Title:	SEMICONDUCTOR DEVICE COMPRISING A FLOATING GATE FLASH MEMORY DEVICE

Patent #:	9927698	Issue Dt:	03/27/2018	Application #:	15234078	Filing Dt:	08/11/2016
Publication #:	US20180046073	Pub Dt:	02/15/2018
Title:	DUAL EXPOSURE PATTERNING OF A PHOTOMASK TO PRINT A CONTACT, A VIA OR A CURVILINEAR SHAPE ON AN INTEGRATED CIRCUIT

Patent #:	9972620	Issue Dt:	05/15/2018	Application #:	15234762	Filing Dt:	08/11/2016
Publication #:	US20180047727	Pub Dt:	02/15/2018
Title:	PREVENTING SHORTING BETWEEN SOURCE AND/OR DRAIN CONTACTS AND GATE

Patent #:	9837439	Issue Dt:	12/05/2017	Application #:	15235256	Filing Dt:	08/12/2016
Title:	COMPENSATION OF TEMPERATURE EFFECTS IN SEMICONDUCTOR DEVICE STRUCTURES

Patent #:	9704746	Issue Dt:	07/11/2017	Application #:	15235892	Filing Dt:	08/12/2016
Title:	ADVANCED SELF-ALIGNED PATTERNING PROCESS WITH SIT SPACER AS A FINAL DIELECTRIC ETCH HARDMASK

Patent #:	9825041	Issue Dt:	11/21/2017	Application #:	15236608	Filing Dt:	08/15/2016
Title:	INTEGRATED CIRCUIT STRUCTURE WITH INSULATED MEMORY DEVICE AND RELATED METHODS

Patent #:	9947602	Issue Dt:	04/17/2018	Application #:	15237066	Filing Dt:	08/15/2016
Publication #:	US20180047648	Pub Dt:	02/15/2018
Title:	IC STRUCTURE INTEGRITY SENSOR HAVING INTERDIGITATED CONDUCTIVE ELEMENTS

Patent #:	10084057	Issue Dt:	09/25/2018	Application #:	15237794	Filing Dt:	08/16/2016
Publication #:	US20180053832	Pub Dt:	02/22/2018
Title:	NVM DEVICE IN SOI TECHNOLOGY AND METHOD OF FABRICATING AN ACCORDING DEVICE

Patent #:	10056376	Issue Dt:	08/21/2018	Application #:	15238023	Filing Dt:	08/16/2016
Publication #:	US20160358915	Pub Dt:	12/08/2016
Title:	FERROELECTRIC FINFET

Patent #:	9905552	Issue Dt:	02/27/2018	Application #:	15238107	Filing Dt:	08/16/2016
Publication #:	US20180053757	Pub Dt:	02/22/2018
Title:	ASSIST CUTS DISPOSED IN DUMMY LINES TO IMPROVE METAL SIGNAL CUTS IN ACTIVE LINES OF A SEMICONDUCTOR STRUCTURE

Patent #:	9952500	Issue Dt:	04/24/2018	Application #:	15239072	Filing Dt:	08/17/2016
Publication #:	US20180052388	Pub Dt:	02/22/2018
Title:	ADJUSTING OF PATTERNS IN DESIGN LAYOUT FOR OPTICAL PROXIMITY CORRECTION

Patent #:	10157789	Issue Dt:	12/18/2018	Application #:	15239178	Filing Dt:	08/17/2016
Publication #:	US20160358820	Pub Dt:	12/08/2016
Title:	VIA FORMATION USING SIDEWALL IMAGE TRANFER PROCESS TO DEFINE LATERAL DIMENSION

Patent #:	9773717	Issue Dt:	09/26/2017	Application #:	15242643	Filing Dt:	08/22/2016
Title:	INTEGRATED CIRCUITS WITH PELTIER COOLING PROVIDED BY BACK-END WIRING

Patent #:	9741615	Issue Dt:	08/22/2017	Application #:	15242951	Filing Dt:	08/22/2016
Title:	CONTACTS FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR

Patent #:	10170583	Issue Dt:	01/01/2019	Application #:	15244067	Filing Dt:	08/23/2016
Publication #:	US20170054004	Pub Dt:	02/23/2017
Title:	FORMING A GATE CONTACT IN THE ACTIVE AREA

Patent #:	9773708	Issue Dt:	09/26/2017	Application #:	15245634	Filing Dt:	08/24/2016
Title:	DEVICES AND METHODS OF FORMING VFET WITH SELF-ALIGNED REPLACEMENT METAL GATES ALIGNED TO TOP SPACER POST TOP SOURCE DRAIN EPI

Patent #:	10043764	Issue Dt:	08/07/2018	Application #:	15247513	Filing Dt:	08/25/2016
Publication #:	US20160372425	Pub Dt:	12/22/2016
Title:	THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME

Patent #:	9842927	Issue Dt:	12/12/2017	Application #:	15248367	Filing Dt:	08/26/2016
Title:	INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME

Patent #:	10014303	Issue Dt:	07/03/2018	Application #:	15248889	Filing Dt:	08/26/2016
Publication #:	US20180061842	Pub Dt:	03/01/2018
Title:	DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS

Patent #:	10199315	Issue Dt:	02/05/2019	Application #:	15249700	Filing Dt:	08/29/2016
Publication #:	US20180061749	Pub Dt:	03/01/2018
Title:	POST ZERO VIA LAYER KEEP OUT ZONE OVER THROUGH SILICON VIA REDUCING BEOL PUMPING EFFECTS

Patent #:	9728626	Issue Dt:	08/08/2017	Application #:	15251435	Filing Dt:	08/30/2016
Title:	ALMOST DEFECT-FREE ACTIVE CHANNEL REGION

Patent #:	9679888	Issue Dt:	06/13/2017	Application #:	15251632	Filing Dt:	08/30/2016
Title:	ESD DEVICE FOR A SEMICONDUCTOR STRUCTURE

Patent #:	10388602	Issue Dt:	08/20/2019	Application #:	15251804	Filing Dt:	08/30/2016
Publication #:	US20170170118	Pub Dt:	06/15/2017
Title:	LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES

Patent #:	9559018	Issue Dt:	01/31/2017	Application #:	15252315	Filing Dt:	08/31/2016
Publication #:	US20160372493	Pub Dt:	12/22/2016
Title:	DUAL CHANNEL FINFET WITH RELAXED PFET REGION

Patent #:	9607903	Issue Dt:	03/28/2017	Application #:	15252586	Filing Dt:	08/31/2016
Publication #:	US20170040224	Pub Dt:	02/09/2017
Title:	METHOD FOR FORMING FIELD EFFECT TRANSISTORS

Patent #:	10418364	Issue Dt:	09/17/2019	Application #:	15252995	Filing Dt:	08/31/2016
Publication #:	US20180061839	Pub Dt:	03/01/2018
Title:	SEMICONDUCTOR DEVICE STRUCTURE WITH SELF-ALIGNED CAPACITOR DEVICE

Patent #:	10026645	Issue Dt:	07/17/2018	Application #:	15253097	Filing Dt:	08/31/2016
Publication #:	US20180061699	Pub Dt:	03/01/2018
Title:	MULTIPLE PATTERNING PROCESS FOR FORMING PILLAR MASK ELEMENTS

Patent #:	9640436	Issue Dt:	05/02/2017	Application #:	15254096	Filing Dt:	09/01/2016
Publication #:	US20170140987	Pub Dt:	05/18/2017
Title:	MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT

Patent #:	10095115	Issue Dt:	10/09/2018	Application #:	15255237	Filing Dt:	09/02/2016
Publication #:	US20180067396	Pub Dt:	03/08/2018
Title:	FORMING EDGE ETCH PROTECTION USING DUAL LAYER OF POSITIVE-NEGATIVE TONE RESISTS

Patent #:	9570583	Issue Dt:	02/14/2017	Application #:	15255628	Filing Dt:	09/02/2016
Publication #:	US20160372576	Pub Dt:	12/22/2016
Title:	RECESSING RMG METAL GATE STACK FOR FORMING SELF-ALIGNED CONTACT

Patent #:	10050119	Issue Dt:	08/14/2018	Application #:	15256027	Filing Dt:	09/02/2016
Publication #:	US20180069091	Pub Dt:	03/08/2018
Title:	METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFORMANCE AND HCI OPTIMIZATION

Patent #:	10090195	Issue Dt:	10/02/2018	Application #:	15257245	Filing Dt:	09/06/2016
Publication #:	US20170117179	Pub Dt:	04/27/2017
Title:	METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCTOR STRUCTURE INCLUDING A DIFFUSION BARRIER

Patent #:	10056468	Issue Dt:	08/21/2018	Application #:	15258333	Filing Dt:	09/07/2016
Publication #:	US20180069092	Pub Dt:	03/08/2018
Title:	SOURCE/DRAIN PARASITIC CAPACITANCE REDUCTION IN FINFET-BASED SEMICONDUCTOR STRUCTURE HAVING TUCKED FINS

Patent #:	9960252	Issue Dt:	05/01/2018	Application #:	15258597	Filing Dt:	09/07/2016
Publication #:	US20160380076	Pub Dt:	12/29/2016
Title:	METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Patent #:	10056381	Issue Dt:	08/21/2018	Application #:	15259268	Filing Dt:	09/08/2016
Publication #:	US20180069005	Pub Dt:	03/08/2018
Title:	PUNCHTHROUGH STOP LAYERS FOR FIN-TYPE FIELD-EFFECT TRANSISTORS

Patent #:	10096604	Issue Dt:	10/09/2018	Application #:	15259472	Filing Dt:	09/08/2016
Publication #:	US20180069009	Pub Dt:	03/08/2018
Title:	SELECTIVE SAC CAPPING ON FIN FIELD EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS

Patent #:	9786751	Issue Dt:	10/10/2017	Application #:	15263551	Filing Dt:	09/13/2016
Publication #:	US20160380065	Pub Dt:	12/29/2016
Title:	SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)

Patent #:	9715064	Issue Dt:	07/25/2017	Application #:	15263817	Filing Dt:	09/13/2016
Title:	MULTI-CHIP MODULES WITH VERTICALLY ALIGNED GRATING COUPLERS FOR TRANSMISSION OF LIGHT SIGNALS BETWEEN OPTICAL WAVEGUIDES

Patent #:	10192864	Issue Dt:	01/29/2019	Application #:	15264885	Filing Dt:	09/14/2016
Publication #:	US20170005085	Pub Dt:	01/05/2017
Title:	LATERAL BICMOS REPLACEMENT METAL GATE

Patent #:	10153224	Issue Dt:	12/11/2018	Application #:	15264957	Filing Dt:	09/14/2016
Publication #:	US20180076110	Pub Dt:	03/15/2018
Title:	BACKSIDE SPACER STRUCTURES FOR IMPROVED THERMAL PERFORMANCE

Patent #:	9812575	Issue Dt:	11/07/2017	Application #:	15266092	Filing Dt:	09/15/2016
Title:	CONTACT FORMATION FOR STACKED FINFETs

Patent #:	9837168	Issue Dt:	12/05/2017	Application #:	15266201	Filing Dt:	09/15/2016
Title:	WORD LINE VOLTAGE GENERATOR FOR PROGRAMMABLE MEMORY ARRAY

Patent #:	9685497	Issue Dt:	06/20/2017	Application #:	15266439	Filing Dt:	09/15/2016
Publication #:	US20170005159	Pub Dt:	01/05/2017
Title:	EMBEDDED METAL-INSULATOR-METAL CAPACITOR

Patent #:	9972697	Issue Dt:	05/15/2018	Application #:	15267887	Filing Dt:	09/16/2016
Publication #:	US20170005179	Pub Dt:	01/05/2017
Title:	METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Patent #:	10347745	Issue Dt:	07/09/2019	Application #:	15268751	Filing Dt:	09/19/2016
Publication #:	US20180083121	Pub Dt:	03/22/2018
Title:	METHODS OF FORMING BOTTOM AND TOP SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE

Patent #:	10170616	Issue Dt:	01/01/2019	Application #:	15268796	Filing Dt:	09/19/2016
Publication #:	US20180083136	Pub Dt:	03/22/2018
Title:	METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE

Patent #:	10049917	Issue Dt:	08/14/2018	Application #:	15269023	Filing Dt:	09/19/2016
Publication #:	US20180082889	Pub Dt:	03/22/2018
Title:	FDSOI CHANNEL CONTROL BY IMPLANTED HIGH-K BURIED OXIDE

Patent #:	10013519	Issue Dt:	07/03/2018	Application #:	15270598	Filing Dt:	09/20/2016
Publication #:	US20180082007	Pub Dt:	03/22/2018
Title:	PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION

Patent #:	9818640	Issue Dt:	11/14/2017	Application #:	15271475	Filing Dt:	09/21/2016
Title:	APPARATUS AND METHOD OF FORMING SELF-ALIGNED CUTS IN A NON-MANDREL LINE OF AN ARRAY OF METAL LINES

Patent #:	9818641	Issue Dt:	11/14/2017	Application #:	15271497	Filing Dt:	09/21/2016
Title:	APPARATUS AND METHOD OF FORMING SELF-ALIGNED CUTS IN MANDREL AND A NON-MANDREL LINES OF AN ARRAY OF METAL LINES

Patent #:	9978608	Issue Dt:	05/22/2018	Application #:	15271511	Filing Dt:	09/21/2016
Publication #:	US20180082852	Pub Dt:	03/22/2018
Title:	FIN PATTERNING FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR

Patent #:	9786545	Issue Dt:	10/10/2017	Application #:	15271519	Filing Dt:	09/21/2016
Title:	METHOD OF FORMING ANA REGIONS IN AN INTEGRATED CIRCUIT

Patent #:	9923046	Issue Dt:	03/20/2018	Application #:	15271730	Filing Dt:	09/21/2016
Publication #:	US20180083089	Pub Dt:	03/22/2018
Title:	SEMICONDUCTOR DEVICE RESISTOR STRUCTURE

Patent #:	9853115	Issue Dt:	12/26/2017	Application #:	15272919	Filing Dt:	09/22/2016
Publication #:	US20170125535	Pub Dt:	05/04/2017
Title:	HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

Patent #:	9748351	Issue Dt:	08/29/2017	Application #:	15273777	Filing Dt:	09/23/2016
Publication #:	US20170012105	Pub Dt:	01/12/2017
Title:	PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE

Patent #:	10749031	Issue Dt:	08/18/2020	Application #:	15273778	Filing Dt:	09/23/2016
Publication #:	US20170012130	Pub Dt:	01/12/2017
Title:	LARGE AREA CONTACTS FOR SMALL TRANSISTORS

Patent #:	9960086	Issue Dt:	05/01/2018	Application #:	15274974	Filing Dt:	09/23/2016
Publication #:	US20180090391	Pub Dt:	03/29/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED RETROGRADE WELL DOPING FOR FINFET DEVICES

Patent #:	10069015	Issue Dt:	09/04/2018	Application #:	15276372	Filing Dt:	09/26/2016
Publication #:	US20180090624	Pub Dt:	03/29/2018
Title:	Width Adjustment of Stacked Nanowires

Patent #:	10283584	Issue Dt:	05/07/2019	Application #:	15277583	Filing Dt:	09/27/2016
Publication #:	US20180090558	Pub Dt:	03/29/2018
Title:	CAPACITIVE STRUCTURE IN A SEMICONDUCTOR DEVICE HAVING REDUCED CAPACITANCE VARIABILITY

Patent #:	9786607	Issue Dt:	10/10/2017	Application #:	15277732	Filing Dt:	09/27/2016
Publication #:	US20170018459	Pub Dt:	01/19/2017
Title:	INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER

Patent #:	10055535	Issue Dt:	08/21/2018	Application #:	15277796	Filing Dt:	09/27/2016
Publication #:	US20180089357	Pub Dt:	03/29/2018
Title:	METHOD, SYSTEM AND PROGRAM PRODUCT FOR IDENTIFYING ANOMALIES IN INTEGRATED CIRCUIT DESIGN LAYOUTS

Patent #:	9799746	Issue Dt:	10/24/2017	Application #:	15278925	Filing Dt:	09/28/2016
Publication #:	US20170077258	Pub Dt:	03/16/2017
Title:	PREVENTING LEAKAGE INSIDE AIR-GAP SPACER DURING CONTACT FORMATION

Patent #:	10141229	Issue Dt:	11/27/2018	Application #:	15279559	Filing Dt:	09/29/2016
Publication #:	US20180090386	Pub Dt:	03/29/2018
Title:	PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES

Patent #:	9831131	Issue Dt:	11/28/2017	Application #:	15279732	Filing Dt:	09/29/2016
Title:	METHOD FOR FORMING NANOWIRES INCLUDING MULTIPLE INTEGRATED DEVICES WITH ALTERNATE CHANNEL MATERIALS

Patent #:	10199480	Issue Dt:	02/05/2019	Application #:	15280451	Filing Dt:	09/29/2016
Publication #:	US20180090598	Pub Dt:	03/29/2018
Title:	CONTROLLING SELF-ALIGNED GATE LENGTH IN VERTICAL TRANSISTOR REPLACEMENT GATE FLOW

Patent #:	10042973	Issue Dt:	08/07/2018	Application #:	15281183	Filing Dt:	09/30/2016
Publication #:	US20180096093	Pub Dt:	04/05/2018
Title:	EXPANSION OF ALLOWED DESIGN RULE SPACE BY WAIVING BENIGN GEOMETRIES

Patent #:	9882025	Issue Dt:	01/30/2018	Application #:	15281227	Filing Dt:	09/30/2016
Title:	METHODS OF SIMULTANEOUSLY FORMING BOTTOM AND TOP SPACERS ON A VERTICAL TRANSISTOR DEVICE

Patent #:	9991155	Issue Dt:	06/05/2018	Application #:	15281418	Filing Dt:	09/30/2016
Publication #:	US20180096884	Pub Dt:	04/05/2018
Title:	LOCAL TRAP-RICH ISOLATION

Patent #:	9953876	Issue Dt:	04/24/2018	Application #:	15282211	Filing Dt:	09/30/2016
Publication #:	US20180096894	Pub Dt:	04/05/2018
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	9864132	Issue Dt:	01/09/2018	Application #:	15282320	Filing Dt:	09/30/2016
Title:	SILICON WAVEGUIDE DEVICES IN INTEGRATED PHOTONICS

Patent #:	9837553	Issue Dt:	12/05/2017	Application #:	15282415	Filing Dt:	09/30/2016
Title:	VERTICAL FIELD EFFECT TRANSISTOR

Patent #:	9601335	Issue Dt:	03/21/2017	Application #:	15282836	Filing Dt:	09/30/2016
Publication #:	US20170033196	Pub Dt:	02/02/2017
Title:	TRENCH FORMATION FOR DIELECTRIC FILLED CUT REGION

Patent #:	9698230	Issue Dt:	07/04/2017	Application #:	15283951	Filing Dt:	10/03/2016
Publication #:	US20170141198	Pub Dt:	05/18/2017
Title:	MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT

Patent #:	9953879	Issue Dt:	04/24/2018	Application #:	15284110	Filing Dt:	10/03/2016
Publication #:	US20180096895	Pub Dt:	04/05/2018
Title:	PREVENTING OXIDATION DEFECTS IN STRAIN-RELAXED FINS BY REDUCING LOCAL GAP FILL VOIDS

Patent #:	10153162	Issue Dt:	12/11/2018	Application #:	15284773	Filing Dt:	10/04/2016
Publication #:	US20180096839	Pub Dt:	04/05/2018
Title:	SHRINK PROCESS AWARE ASSIST FEATURES

Patent #:	10079173	Issue Dt:	09/18/2018	Application #:	15285092	Filing Dt:	10/04/2016
Publication #:	US20180096932	Pub Dt:	04/05/2018
Title:	METHODS OF FORMING METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING PRODUCTS

100

Patent #:	10049944	Issue Dt:	08/14/2018	Application #:	15285978	Filing Dt:	10/05/2016
Publication #:	US20180096899	Pub Dt:	04/05/2018
Title:	METHOD OF MANUFACTURING SELECTIVE NANOSTRUCTURES INTO FINFET PROCESS FLOW

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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