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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
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Patent #:	6645780	Issue Dt:	11/11/2003	Application #:	10022321	Filing Dt:	12/13/2001
Title:	METHOD AND APPARATUS FOR COMBINING INTEGRATED AND OFFLINE METROLOGY FOR PROCESS CONTROL

Patent #:	6788988	Issue Dt:	09/07/2004	Application #:	10023098	Filing Dt:	12/17/2001
Title:	METHOD AND APPARATUS USING INTEGRATED METROLOGY DATA FOR PRE-PROCESS AND POST-PROCESS CONTROL

Patent #:	6650955	Issue Dt:	11/18/2003	Application #:	10024675	Filing Dt:	12/18/2001
Title:	METHOD AND APPARATUS FOR DETERMINING A SAMPLING PLAN BASED ON PROCESS AND EQUIPMENT FINGERPRINTING

Patent #:	6982844	Issue Dt:	01/03/2006	Application #:	10026029	Filing Dt:	12/18/2001
Publication #:	US20030112542	Pub Dt:	06/19/2003
Title:	OPTICAL APERTURE FOR DATA RECORDING HAVING TRANSMISSION ENHANCED BY SURFACE PLASMON RESONANCE

Patent #:	6599778	Issue Dt:	07/29/2003	Application #:	10026103	Filing Dt:	12/19/2001
Publication #:	US20030111733	Pub Dt:	06/19/2003
Title:	CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS

Patent #:	6718444	Issue Dt:	04/06/2004	Application #:	10028840	Filing Dt:	12/20/2001
Title:	READ-MODIFY-WRITE FOR PARTIAL WRITES IN A MEMORY CONTROLLER

Patent #:	6667528	Issue Dt:	12/23/2003	Application #:	10033902	Filing Dt:	01/03/2002
Publication #:	US20030122210	Pub Dt:	07/03/2003
Title:	SEMICONDUCTOR-ON-INSULATOR LATERAL P-I-N PHOTODETECTOR WITH A REFLECTING MIRROR AND BACKSIDE CONTACT AND METHOD FOR FORMING THE SAME

Patent #:	6790755	Issue Dt:	09/14/2004	Application #:	10034163	Filing Dt:	12/27/2001
Publication #:	US20030194853	Pub Dt:	10/16/2003
Title:	PREPARATION OF STACK HIGH-K GATE DIELECTRICS WITH NITRIDED LAYER

Patent #:	6791554	Issue Dt:	09/14/2004	Application #:	10034560	Filing Dt:	12/27/2001
Title:	I/O NODE FOR A COMPUTER SYSTEM INCLUDING AN INTEGRATED GRAPHICS ENGINE

Patent #:	6774998	Issue Dt:	08/10/2004	Application #:	10034790	Filing Dt:	12/27/2001
Title:	METHOD AND APPARATUS FOR IDENTIFYING MISREGISTRATION IN A COMPLIMENTARY PHASE SHIFT MASK PROCESS

Patent #:	6857033	Issue Dt:	02/15/2005	Application #:	10034967	Filing Dt:	12/27/2001
Title:	I/O NODE FOR A COMPUTER SYSTEM INCLUDING AN INTEGRATED GRAPHICS ENGINE AND AN INTEGRATED I/O HUB

Patent #:	6515335	Issue Dt:	02/04/2003	Application #:	10037611	Filing Dt:	01/04/2002
Title:	METHOD FOR FABRICATION OF RELAXED SIGE BUFFER LAYERS ON SILICON-ON-INSULATORS AND STRUCTURES CONTAINING THE SAME

Patent #:	7116736	Issue Dt:	10/03/2006	Application #:	10038163	Filing Dt:	01/02/2002
Publication #:	US20030123587	Pub Dt:	07/03/2003
Title:	METHOD, SYSTEM, AND PROGRAM FOR SYNCHRONIZATION AND RESYNCHRONIZATION OF A DATA STREAM

Patent #:	6784668	Issue Dt:	08/31/2004	Application #:	10040002	Filing Dt:	11/07/2001
Title:	ELECTRICAL CONDUCTION ARRAY ON THE BOTTOM SIDE OF A TESTER THERMAL HEAD

Patent #:	6613594	Issue Dt:	09/02/2003	Application #:	10040325	Filing Dt:	11/07/2001
Title:	SURFACE PLASMON RESONANCE-BASED ENDPOINT DETECTION FOR CHEMICAL MECHANICAL PLANARIZATION (CMP)

Patent #:	6634543	Issue Dt:	10/21/2003	Application #:	10040839	Filing Dt:	01/07/2002
Publication #:	US20030127495	Pub Dt:	07/10/2003
Title:	METHOD OF FORMING METALLIC Z-INTERCONNECTS FOR LAMINATE CHIP PACKAGES AND BOARDS

Patent #:	6703706	Issue Dt:	03/09/2004	Application #:	10041347	Filing Dt:	01/08/2002
Publication #:	US20030127728	Pub Dt:	07/10/2003
Title:	CONCURRENT ELECTRICAL SIGNAL WIRING OPTIMIZATION FOR AN ELECTRONIC PACKAGE

Patent #:	6779162	Issue Dt:	08/17/2004	Application #:	10042101	Filing Dt:	01/07/2002
Publication #:	US20030131328	Pub Dt:	07/10/2003
Title:	METHOD OF ANALYZING AND FILTERING TIMING RUNS USING COMMON TIMING CHARACTERISTICS

Patent #:	7058668	Issue Dt:	06/06/2006	Application #:	10042366	Filing Dt:	01/11/2002
Publication #:	US20030135486	Pub Dt:	07/17/2003
Title:	SYSTEM FOR ESTIMATING THE TEMPORAL VALIDITY OF LOCATION REPORTS THROUGH PATTERN ANALYSIS

Patent #:	6590278	Issue Dt:	07/08/2003	Application #:	10043060	Filing Dt:	01/08/2002
Publication #:	US20030127714	Pub Dt:	07/10/2003
Title:	ELECTRONIC PACKAGE

Patent #:	6630360	Issue Dt:	10/07/2003	Application #:	10044641	Filing Dt:	01/10/2002
Publication #:	US20030129774	Pub Dt:	07/10/2003
Title:	ADVANCED PROCESS CONTROL (APC) OF COPPER THICKNESS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OPTIMIZATION

Patent #:	7698522	Issue Dt:	04/13/2010	Application #:	10044667	Filing Dt:	01/11/2002
Title:	METHOD AND APPARATUS FOR LINEAR ADDRESS BASED PAGE LEVEL SECURITY SCHEME TO DETERMINE CURRENT SECURITY CONTEXT

Patent #:	7305675	Issue Dt:	12/04/2007	Application #:	10044707	Filing Dt:	01/11/2002
Title:	PROCESSING TASKS WITH FAILURE RECOVERY

Patent #:	6528858	Issue Dt:	03/04/2003	Application #:	10044892	Filing Dt:	01/11/2002
Title:	MOSFETS WITH DIFFERING GATE DIELECTRICS AND METHOD OF FORMATION

Patent #:	6639219	Issue Dt:	10/28/2003	Application #:	10045445	Filing Dt:	11/09/2001
Publication #:	US20030089853	Pub Dt:	05/15/2003
Title:	ELECTRON SCATTER IN A THIN MEMBRANE TO ELIMINATE DETECTOR SATURATION

Patent #:	6737727	Issue Dt:	05/18/2004	Application #:	10045711	Filing Dt:	01/14/2002
Publication #:	US20020093075	Pub Dt:	07/18/2002
Title:	ELECTRONIC STRUCTURES WITH REDUCED CAPACITANCE

Patent #:	7739498	Issue Dt:	06/15/2010	Application #:	10047188	Filing Dt:	01/15/2002
Publication #:	US20040054895	Pub Dt:	03/18/2004
Title:	METHOD AND APPARATUS FOR MULTI-TABLE ACCESSING OF INPUT/OUTPUT DEVICES USING TARGET SECURITY

Patent #:	6587345	Issue Dt:	07/01/2003	Application #:	10047497	Filing Dt:	11/09/2001
Publication #:	US20030090872	Pub Dt:	05/15/2003
Title:	ELECTRONIC DEVICE SUBSTRATE ASSEMBLY WITH IMPERMEABLE BARRIER AND METHOD OF MAKING

Patent #:	6737747	Issue Dt:	05/18/2004	Application #:	10047965	Filing Dt:	01/15/2002
Publication #:	US20030132510	Pub Dt:	07/17/2003
Title:	ADVANCED BEOL INTERCONNECT STRUCTURES WITH LOW-K PE CVD CAP LAYER AND METHOD THEREOF

Patent #:	6758612	Issue Dt:	07/06/2004	Application #:	10050471	Filing Dt:	01/16/2002
Title:	SYSTEM AND METHOD FOR DEVELOPER ENDPOINT DETECTION BY REFLECTOMETRY OR SCATTEROMETRY

Patent #:	6451621	Issue Dt:	09/17/2002	Application #:	10050732	Filing Dt:	01/16/2002
Title:	USING SCATTEROMETRY TO MEASURE RESIST THICKNESS AND CONTROL IMPLANT

Patent #:	6559028	Issue Dt:	05/06/2003	Application #:	10051549	Filing Dt:	01/18/2002
Title:	METHOD OF TOPOGRAPHY MANAGEMENT IN SEMICONDUCTOR FORMATION

Patent #:	6645882	Issue Dt:	11/11/2003	Application #:	10051790	Filing Dt:	01/17/2002
Title:	PREPARATION OF COMPOSITE HIGH-K / STANDARD-K DIELECTRICS FOR SEMICONDUCTOR DEVICES

Patent #:	6633392	Issue Dt:	10/14/2003	Application #:	10052142	Filing Dt:	01/17/2002
Title:	X-RAY REFLECTANCE SYSTEM TO DETERMINE SUITABILITY OF SION ARC LAYER

Patent #:	6670271	Issue Dt:	12/30/2003	Application #:	10052146	Filing Dt:	01/17/2002
Title:	GROWING A DUAL DAMASCENE STRUCTURE USING A COPPER SEED LAYER AND A DAMASCENE RESIST STRUCTURE

Patent #:	6621353	Issue Dt:	09/16/2003	Application #:	10053033	Filing Dt:	11/07/2001
Publication #:	US20030085768	Pub Dt:	05/08/2003
Title:	PHASE LOCKED LOOP RECONFIGURATION

Patent #:	6744338	Issue Dt:	06/01/2004	Application #:	10054409	Filing Dt:	11/13/2001
Publication #:	US20030090346	Pub Dt:	05/15/2003
Title:	RESONANT OPERATION OF MEMS SWITCH

Patent #:	6805962	Issue Dt:	10/19/2004	Application #:	10055138	Filing Dt:	01/23/2002
Publication #:	US20030139000	Pub Dt:	07/24/2003
Title:	METHOD OF CREATING HIGH-QUALITY RELAXED SIGE-ON-INSULATOR FOR STRAINED SI CMOS APPLICATIONS

Patent #:	6495429	Issue Dt:	12/17/2002	Application #:	10055139	Filing Dt:	01/23/2002
Title:	CONTROLLING INTERNAL THERMAL OXIDATION AND ELIMINATING DEEP DIVOTS IN SIMOX BY CHLORINE-BASED ANNEALING

Patent #:	6968489	Issue Dt:	11/22/2005	Application #:	10055275	Filing Dt:	01/23/2002
Publication #:	US20030140293	Pub Dt:	07/24/2003
Title:	PSEUDO RANDOM OPTIMIZED BUILT-IN SELF-TEST

Patent #:	6993814	Issue Dt:	02/07/2006	Application #:	10057185	Filing Dt:	01/25/2002
Publication #:	US20020071237	Pub Dt:	06/13/2002
Title:	METHOD OF FABRICATING A CAPACITOR HAVING SIDEWALL SPACER PROTECTING THE DIELECTRIC LAYER

Patent #:	6744132	Issue Dt:	06/01/2004	Application #:	10058999	Filing Dt:	01/29/2002
Publication #:	US20030141586	Pub Dt:	07/31/2003
Title:	MODULE WITH ADHESIVELY ATTACHED HEAT SINK

Patent #:	6713382	Issue Dt:	03/30/2004	Application #:	10059268	Filing Dt:	01/31/2002
Title:	VAPOR TREATMENT FOR REPAIRING DAMAGE OF LOW-K DIELECTRIC

Patent #:	6620029	Issue Dt:	09/16/2003	Application #:	10059775	Filing Dt:	01/30/2002
Publication #:	US20030143930	Pub Dt:	07/31/2003
Title:	APPARATUS AND METHOD FOR FRONT SIDE CHEMICAL MECHANICAL PLANARIZATION (CMP) OF SEMICONDUCTOR WORKPIECES

Patent #:	6614064	Issue Dt:	09/02/2003	Application #:	10060422	Filing Dt:	01/30/2002
Title:	TRANSISTOR HAVING A GATE STACK COMPRISED OF A METAL, AND A METHOD OF MAKING SAME

Patent #:	6677645	Issue Dt:	01/13/2004	Application #:	10061263	Filing Dt:	01/31/2002
Publication #:	US20030141543	Pub Dt:	07/31/2003
Title:	BODY CONTACT MOSFET

Patent #:	6775736	Issue Dt:	08/10/2004	Application #:	10062812	Filing Dt:	01/31/2002
Publication #:	US20030145158	Pub Dt:	07/31/2003
Title:	EMBEDDED DRAM SYSTEM HAVING WIDE DATA BANDWIDTH AND DATA TRANSFER DATA PROTOCOL

Patent #:	6778447	Issue Dt:	08/17/2004	Application #:	10062972	Filing Dt:	01/31/2002
Publication #:	US20030142558	Pub Dt:	07/31/2003
Title:	EMBEDDED DRAM SYSTEM HAVING WIDE DATA BANDWIDTH AND DATA TRANSFER DATA PROTOCOL

Patent #:	6657252	Issue Dt:	12/02/2003	Application #:	10063095	Filing Dt:	03/19/2002
Publication #:	US20030178670	Pub Dt:	09/25/2003
Title:	FINFET CMOS WITH NVRAM CAPABILITY

Patent #:	6731488	Issue Dt:	05/04/2004	Application #:	10063225	Filing Dt:	04/01/2002
Publication #:	US20030184943	Pub Dt:	10/02/2003
Title:	DUAL EMITTER TRANSISTOR WITH ESD PROTECTION

Patent #:	6750487	Issue Dt:	06/15/2004	Application #:	10063323	Filing Dt:	04/11/2002
Publication #:	US20030193065	Pub Dt:	10/16/2003
Title:	DUAL DOUBLE GATE TRANSISTOR AND METHOD FOR FORMING

Patent #:	6697293	Issue Dt:	02/24/2004	Application #:	10063329	Filing Dt:	04/12/2002
Publication #:	US20030193828	Pub Dt:	10/16/2003
Title:	LOCALIZED DIRECT SENSE ARCHITECTURE

Patent #:	6664582	Issue Dt:	12/16/2003	Application #:	10063330	Filing Dt:	04/12/2002
Publication #:	US20030197194	Pub Dt:	10/23/2003
Title:	FIN MEMORY CELL AND METHOD OF FABRICATION

Patent #:	6794726	Issue Dt:	09/21/2004	Application #:	10063376	Filing Dt:	04/17/2002
Publication #:	US20030201514	Pub Dt:	10/30/2003
Title:	MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE

Patent #:	6774019	Issue Dt:	08/10/2004	Application #:	10063846	Filing Dt:	05/17/2002
Publication #:	US20030213433	Pub Dt:	11/20/2003
Title:	INCORPORATION OF AN IMPURITY INTO A THIN FILM

Patent #:	6762918	Issue Dt:	07/13/2004	Application #:	10063858	Filing Dt:	05/20/2002
Publication #:	US20030213978	Pub Dt:	11/20/2003
Title:	FAULT FREE FUSE NETWORK

Patent #:	6642090	Issue Dt:	11/04/2003	Application #:	10063994	Filing Dt:	06/03/2002
Title:	FIN FET DEVICES FROM BULK SEMICONDUCTOR AND METHOD FOR FORMING

Patent #:	6639242	Issue Dt:	10/28/2003	Application #:	10064303	Filing Dt:	07/01/2002
Title:	MONOLITHICALLY INTEGRATED SOLID-STATE SIGE THERMOELECTRIC ENERGY CONVERTER FOR HIGH SPEED AND LOW POWER CIRCUITS

Patent #:	6711078	Issue Dt:	03/23/2004	Application #:	10064306	Filing Dt:	07/01/2002
Publication #:	US20040001382	Pub Dt:	01/01/2004
Title:	WRITEBACK AND REFRESH CIRCUITRY FOR DIRECT SENSED DRAM MACRO

Patent #:	6753590	Issue Dt:	06/22/2004	Application #:	10064375	Filing Dt:	07/08/2002
Publication #:	US20040004269	Pub Dt:	01/08/2004
Title:	HIGH IMPEDANCE ANTIFUSE

Patent #:	6794706	Issue Dt:	09/21/2004	Application #:	10064493	Filing Dt:	07/22/2002
Publication #:	US20040012046	Pub Dt:	01/22/2004
Title:	APPLICATIONS OF SPACE-CHARGE-LIMITED CONDUCTION INDUCED CURRENT INCREASE IN NITRIDE-OXIDE DIELECTRIC CAPACITORS: VOLTAGE REGULATOR FOR POWER SUPPLY SYSTEM AND OTHERS

Patent #:	6674673	Issue Dt:	01/06/2004	Application #:	10064867	Filing Dt:	08/26/2002
Title:	COLUMN REDUNDANCY SYSTEM AND METHOD FOR A MICRO-CELL EMBEDDED DRAM (E-DRAM) ARCHITECTURE

Patent #:	6820240	Issue Dt:	11/16/2004	Application #:	10065201	Filing Dt:	09/25/2002
Publication #:	US20040060023	Pub Dt:	03/25/2004
Title:	VOLTAGE ISLAND CHIP IMPLEMENTATION

Patent #:	6577548	Issue Dt:	06/10/2003	Application #:	10065223	Filing Dt:	09/26/2002
Title:	SELF TIMING INTERLOCK CIRCUIT FOR EMBEDDED DRAM

Patent #:	6854041	Issue Dt:	02/08/2005	Application #:	10065839	Filing Dt:	11/25/2002
Publication #:	US20040100851	Pub Dt:	05/27/2004
Title:	DRAM-BASED SEPARATE I/O MEMORY SOLUTION FOR COMMUNICATION APPLICATIONS

Patent #:	6734047	Issue Dt:	05/11/2004	Application #:	10065884	Filing Dt:	11/27/2002
Title:	THINNING OF FUSE PASSIVATION AFTER C4 FORMATION

Patent #:	6670259	Issue Dt:	12/30/2003	Application #:	10068396	Filing Dt:	02/05/2002
Title:	INERT ATOM IMPLANTATION METHOD FOR SOI GETTERING

Patent #:	6562642	Issue Dt:	05/13/2003	Application #:	10072330	Filing Dt:	02/07/2002
Title:	MICRO-STRUCTURES AND METHODS FOR THEIR MANUFACTURE

Patent #:	6774647	Issue Dt:	08/10/2004	Application #:	10072486	Filing Dt:	02/07/2002
Publication #:	US20030146768	Pub Dt:	08/07/2003
Title:	NONINVASIVE OPTICAL METHOD AND SYSTEM FOR INSPECTING OR TESTING CMOS CIRCUITS

Patent #:	6784095	Issue Dt:	08/31/2004	Application #:	10073066	Filing Dt:	02/12/2002
Title:	PHOSPHINE TREATMENT OF LOW DIELECTRIC CONSTANT MATERIALS IN SEMICONDUCTOR DEVICE MANUFACTURING

Patent #:	6740600	Issue Dt:	05/25/2004	Application #:	10073695	Filing Dt:	02/11/2002
Publication #:	US20020166839	Pub Dt:	11/14/2002
Title:	ENHANCED INTERFACE THERMOELECTRIC COOLERS WITH ALL-METAL TIPS

Patent #:	6897650	Issue Dt:	05/24/2005	Application #:	10073755	Filing Dt:	02/11/2002
Publication #:	US20030151407	Pub Dt:	08/14/2003
Title:	MAGNETIC-FIELD SENSOR DEVICE

Patent #:	6562713	Issue Dt:	05/13/2003	Application #:	10078779	Filing Dt:	02/19/2002
Title:	METHOD OF PROTECTING SEMICONDUCTOR AREAS WHILE EXPOSING A GATE

Patent #:	6622907	Issue Dt:	09/23/2003	Application #:	10078948	Filing Dt:	02/19/2002
Publication #:	US20030155408	Pub Dt:	08/21/2003
Title:	SACRIFICIAL SEED LAYER PROCESS FOR FORMING C4 SOLDER BUMPS

Patent #:	6576548	Issue Dt:	06/10/2003	Application #:	10079861	Filing Dt:	02/22/2002
Title:	METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH RELIABLE CONTACTS/VIAS

Patent #:	7519089	Issue Dt:	04/14/2009	Application #:	10083149	Filing Dt:	02/27/2002
Title:	ARRANGEMENT IN A CHANNEL ADAPTER FOR TRANSMITTING DATA ACCORDING TO LINK WIDTHS SELECTED BASED ON RECEIVED LINK MANAGEMENT PACKETS

Patent #:	6643008	Issue Dt:	11/04/2003	Application #:	10083699	Filing Dt:	02/26/2002
Title:	METHOD OF DETECTING DEGRADATION IN PHOTOLITHOGRAPHY PROCESSES BASED UPON SCATTEROMETRIC MEASUREMENTS OF GRATING STRUCTURES, AND A DEVICE COMPRISING SUCH STRUCTURES

Patent #:	6660633	Issue Dt:	12/09/2003	Application #:	10083809	Filing Dt:	02/26/2002
Title:	METHOD OF REDUCING ELECTOMIGRATION IN A COPPER LINE BY ELECTROPLATING AN INTERIM COPPER-ZINC ALLOY THIN FILM ON A COPPER SURFACE AND A SEMICONDUCTOR DEVICE THEREBY FORMED

Patent #:	6764808	Issue Dt:	07/20/2004	Application #:	10083914	Filing Dt:	02/27/2002
Publication #:	US20030162135	Pub Dt:	08/28/2003
Title:	SELF-ALIGNED PATTERN FORMATION USING DUAL WAVELENGTHS

Patent #:	6764951	Issue Dt:	07/20/2004	Application #:	10084321	Filing Dt:	02/28/2002
Title:	METHOD FOR FORMING NITRIDE CAPPED CU LINES WITH REDUCED HILLOCK FORMATION

Patent #:	6717236	Issue Dt:	04/06/2004	Application #:	10084563	Filing Dt:	02/26/2002
Title:	METHOD OF REDUCING ELECTROMIGRATION BY FORMING AN ELECTROPLATED COPPER-ZINC INTERCONNECT AND A SEMICONDUCTOR DEVICE THEREBY FORMED

Patent #:	6693004	Issue Dt:	02/17/2004	Application #:	10085318	Filing Dt:	02/27/2002
Title:	INTERFACIAL BARRIER LAYER IN SEMICONDUCTOR DEVICES WITH HIGH-K GATE DIELECTRIC MATERIAL

Patent #:	6451641	Issue Dt:	09/17/2002	Application #:	10085348	Filing Dt:	02/27/2002
Title:	NON-REDUCING PROCESS FOR DEPOSITION OF POLYSILICON GATE ELECTRODE OVER HIGH-K GATE DIELECTRIC MATERIAL

Patent #:	6698009	Issue Dt:	02/24/2004	Application #:	10085938	Filing Dt:	02/28/2002
Title:	METHOD AND APPARATUS FOR MODELING OF BATCH DYNAMICS BASED UPON INTEGRATED METROLOGY

Patent #:	6826437	Issue Dt:	11/30/2004	Application #:	10085956	Filing Dt:	02/28/2002
Publication #:	US20030163213	Pub Dt:	08/28/2003
Title:	ASSOCIATION OF PROCESS CONTEXT WITH CONFIGURATION DOCUMENT FOR MANUFACTURING PROCESS

Patent #:	7030877	Issue Dt:	04/18/2006	Application #:	10090507	Filing Dt:	03/04/2002
Title:	COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER

Patent #:	6975580	Issue Dt:	12/13/2005	Application #:	10090589	Filing Dt:	02/28/2002
Publication #:	US20030123335	Pub Dt:	07/03/2003
Title:	OPTICAL APERTURE FOR DATA RECORDING HAVING TRANSMISSION ENHANCED BY WAVEGUIDE MODE RESONANCE

Patent #:	6603690	Issue Dt:	08/05/2003	Application #:	10091663	Filing Dt:	03/06/2002
Title:	LOW-POWER STATIC COLUMN REDUNDANCY SCHEME FOR SEMICONDUCTOR MEMORIES

Patent #:	7058779	Issue Dt:	06/06/2006	Application #:	10091766	Filing Dt:	03/05/2002
Title:	COMPUTER SYSTEM INITIALIZATION VIA BOOT CODE STORED IN A NON-VOLATILE MEMORY HAVING AN INTERFACE COMPATIBLE WITH SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY

Patent #:	6834314	Issue Dt:	12/21/2004	Application #:	10093055	Filing Dt:	03/07/2002
Title:	METHOD AND APPARATUS FOR REORDERING PACKET TRANSACTIONS WITHIN A PERIPHERAL INTERFACE CIRCUIT

Patent #:	6760791	Issue Dt:	07/06/2004	Application #:	10093125	Filing Dt:	03/07/2002
Title:	BUFFER CIRCUIT FOR A PERIPHERAL INTERFACE CIRCUIT IN AN I/O NODE OF A COMPUTER SYSTEM

Patent #:	6725297	Issue Dt:	04/20/2004	Application #:	10093146	Filing Dt:	03/07/2002
Title:	PERIPHERAL INTERFACE CIRCUIT FOR AN I/O NODE OF A COMPUTER SYSTEM

Patent #:	6760792	Issue Dt:	07/06/2004	Application #:	10093270	Filing Dt:	03/07/2002
Title:	BUFFER CIRCUIT FOR ROTATING OUTSTANDING TRANSACTIONS

Patent #:	6757755	Issue Dt:	06/29/2004	Application #:	10093346	Filing Dt:	03/07/2002
Publication #:	US20030074493	Pub Dt:	04/17/2003
Title:	PERIPHERAL INTERFACE CIRCUIT FOR HANDLING GRAPHICS RESPONSES IN AN I/O NODE OF A COMPUTER SYSTEM

Patent #:	6823405	Issue Dt:	11/23/2004	Application #:	10093349	Filing Dt:	03/07/2002
Title:	METHOD AND APPARATUS FOR INITIATING PARTIAL TRANSACTIONS IN A PERIPHERAL INTERFACE CIRCUIT FOR AN I/O NODE OF A COMPUTER SYSTEM

Patent #:	6529402	Issue Dt:	03/04/2003	Application #:	10094533	Filing Dt:	03/08/2002
Title:	LOW POWER STATIC MEMORY

Patent #:	6682988	Issue Dt:	01/27/2004	Application #:	10097637	Filing Dt:	03/14/2002
Title:	GROWTH OF PHOTORESIST LAYER IN PHOTOLITHOGRAPHIC PROCESS

Patent #:	6630404	Issue Dt:	10/07/2003	Application #:	10097819	Filing Dt:	03/14/2002
Title:	REDUCING FEATURE DIMENSION USING SELF-ASSEMBLED MONOLAYER

Patent #:	6770500	Issue Dt:	08/03/2004	Application #:	10099004	Filing Dt:	03/15/2002
Publication #:	US20030186518	Pub Dt:	10/02/2003
Title:	PROCESS OF PASSIVATING A METAL-GATED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

100

Patent #:	6769108	Issue Dt:	07/27/2004	Application #:	10099776	Filing Dt:	03/14/2002
Publication #:	US20030177466	Pub Dt:	09/18/2003
Title:	TRIANGULAR ASSIGNMENT OF PINS USED FOR DIAGONAL INTERCONNECTIONS BETWEEN DIAGONAL CHIPS IN A MULTI-CHIP MODULE

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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