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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 74 of 85
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Patent #:	10497692	Issue Dt:	12/03/2019	Application #:	15689934	Filing Dt:	08/29/2017
Publication #:	US20190067262	Pub Dt:	02/28/2019
Title:	SRAM STRUCTURE WITH ALTERNATE GATE PITCHES

Patent #:	10546822	Issue Dt:	01/28/2020	Application #:	15690398	Filing Dt:	08/30/2017
Publication #:	US20190067210	Pub Dt:	02/28/2019
Title:	SEAL RING STRUCTURE OF INTEGRATED CIRCUIT AND METHOD OF FORMING SAME

Patent #:	10559743	Issue Dt:	02/11/2020	Application #:	15690828	Filing Dt:	08/30/2017
Publication #:	US20170365775	Pub Dt:	12/21/2017
Title:	BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE

Patent #:	10511143	Issue Dt:	12/17/2019	Application #:	15692136	Filing Dt:	08/31/2017
Publication #:	US20190067905	Pub Dt:	02/28/2019
Title:	III-V LASERS WITH ON-CHIP INTEGRATION

Patent #:	10037911	Issue Dt:	07/31/2018	Application #:	15692666	Filing Dt:	08/31/2017
Publication #:	US20180005873	Pub Dt:	01/04/2018
Title:	DEVICE LAYER TRANSFER WITH A PRESERVED HANDLE WAFER SECTION

Patent #:	10106892	Issue Dt:	10/23/2018	Application #:	15692816	Filing Dt:	08/31/2017
Title:	THERMAL OXIDE EQUIVALENT LOW TEMPERATURE ALD OXIDE FOR DUAL PURPOSE GATE OXIDE AND METHOD FOR PRODUCING THE SAME

Patent #:	10411107	Issue Dt:	09/10/2019	Application #:	15693537	Filing Dt:	09/01/2017
Publication #:	US20190074364	Pub Dt:	03/07/2019
Title:	SEMICONDUCTOR DEVICE WITH AIRGAP SPACER FOR TRANSISTOR AND RELATED METHOD

Patent #:	10243074	Issue Dt:	03/26/2019	Application #:	15693938	Filing Dt:	09/01/2017
Publication #:	US20180102432	Pub Dt:	04/12/2018
Title:	VERTICAL VACUUM CHANNEL TRANSISTOR

Patent #:	10431682	Issue Dt:	10/01/2019	Application #:	15693952	Filing Dt:	09/01/2017
Publication #:	US20180102433	Pub Dt:	04/12/2018
Title:	VERTICAL VACUUM CHANNEL TRANSISTOR

Patent #:	10109714	Issue Dt:	10/23/2018	Application #:	15694109	Filing Dt:	09/01/2017
Publication #:	US20180254327	Pub Dt:	09/06/2018
Title:	BURIED CONTACT STRUCTURES FOR A VERTICAL FIELD-EFFECT TRANSISTOR

Patent #:	10290549	Issue Dt:	05/14/2019	Application #:	15695229	Filing Dt:	09/05/2017
Publication #:	US20190074224	Pub Dt:	03/07/2019
Title:	INTEGRATED CIRCUIT STRUCTURE, GATE ALL-AROUND INTEGRATED CIRCUIT STRUCTURE AND METHODS OF FORMING SAME

Patent #:	10651136	Issue Dt:	05/12/2020	Application #:	15695391	Filing Dt:	09/05/2017
Publication #:	US20190074257	Pub Dt:	03/07/2019
Title:	TECHNIQUE FOR DECOUPLING PLASMA ANTENNAE FROM ACTUAL CIRCUITRY

Patent #:	10535379	Issue Dt:	01/14/2020	Application #:	15695457	Filing Dt:	09/05/2017
Publication #:	US20170365302	Pub Dt:	12/21/2017
Title:	LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY

Patent #:	10394116	Issue Dt:	08/27/2019	Application #:	15696505	Filing Dt:	09/06/2017
Publication #:	US20190072845	Pub Dt:	03/07/2019
Title:	SEMICONDUCTOR FABRICATION DESIGN RULE LOOPHOLE CHECKING FOR DESIGN FOR MANUFACTURABILITY OPTIMIZATION

Patent #:	10068810	Issue Dt:	09/04/2018	Application #:	15697661	Filing Dt:	09/07/2017
Title:	MULTIPLE FIN HEIGHTS WITH DIELECTRIC ISOLATION

Patent #:	10438902	Issue Dt:	10/08/2019	Application #:	15698027	Filing Dt:	09/07/2017
Publication #:	US20190074253	Pub Dt:	03/07/2019
Title:	ARC-RESISTANT CRACKSTOP

Patent #:	10049985	Issue Dt:	08/14/2018	Application #:	15698793	Filing Dt:	09/08/2017
Publication #:	US20170373007	Pub Dt:	12/28/2017
Title:	CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME

Patent #:	10677855	Issue Dt:	06/09/2020	Application #:	15699094	Filing Dt:	09/08/2017
Publication #:	US20190079128	Pub Dt:	03/14/2019
Title:	STRUCTURE, METHOD AND SYSTEM FOR MEASURING RIE LAG DEPTH

Patent #:	9929049	Issue Dt:	03/27/2018	Application #:	15699322	Filing Dt:	09/08/2017
Publication #:	US20170372959	Pub Dt:	12/28/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	10644654	Issue Dt:	05/05/2020	Application #:	15701672	Filing Dt:	09/12/2017
Publication #:	US20190081597	Pub Dt:	03/14/2019
Title:	HYBRID CASCODE CONSTRUCTIONS WITH MULTIPLE TRANSISTOR TYPES

Patent #:	10290639	Issue Dt:	05/14/2019	Application #:	15702243	Filing Dt:	09/12/2017
Publication #:	US20190081049	Pub Dt:	03/14/2019
Title:	VNW SRAM WITH TRINITY CROSS-COUPLE PD/PU CONTACT AND METHOD FOR PRODUCING THE SAME

Patent #:	10446683	Issue Dt:	10/15/2019	Application #:	15702278	Filing Dt:	09/12/2017
Publication #:	US20190081175	Pub Dt:	03/14/2019
Title:	METHODS, APPARATUS AND SYSTEM FOR FORMING SIGMA SHAPED SOURCE/DRAIN LATTICE

Patent #:	10109600	Issue Dt:	10/23/2018	Application #:	15702316	Filing Dt:	09/12/2017
Title:	CRACKSTOP STRUCTURES

Patent #:	10833153	Issue Dt:	11/10/2020	Application #:	15703220	Filing Dt:	09/13/2017
Publication #:	US20190081138	Pub Dt:	03/14/2019
Title:	SWITCH WITH LOCAL SILICON ON INSULATOR (SOI) AND DEEP TRENCH ISOLATION

Patent #:	10340369	Issue Dt:	07/02/2019	Application #:	15703484	Filing Dt:	09/13/2017
Publication #:	US20180006143	Pub Dt:	01/04/2018
Title:	TUNNELING FIELD EFFECT TRANSISTOR

Patent #:	10366996	Issue Dt:	07/30/2019	Application #:	15704598	Filing Dt:	09/14/2017
Publication #:	US20180012895	Pub Dt:	01/11/2018
Title:	STABLE AND RELIABLE FINFET SRAM WITH IMPROVED BETA RATIO

Patent #:	10290768	Issue Dt:	05/14/2019	Application #:	15704982	Filing Dt:	09/14/2017
Publication #:	US20190081206	Pub Dt:	03/14/2019
Title:	NANOWIRE FORMATION METHODS

Patent #:	10312154	Issue Dt:	06/04/2019	Application #:	15705888	Filing Dt:	09/15/2017
Publication #:	US20190088764	Pub Dt:	03/21/2019
Title:	METHOD OF FORMING VERTICAL FINFET DEVICE HAVING SELF-ALIGNED CONTACTS

Patent #:	10283372	Issue Dt:	05/07/2019	Application #:	15705956	Filing Dt:	09/15/2017
Publication #:	US20190088500	Pub Dt:	03/21/2019
Title:	INTERCONNECTS FORMED BY A METAL REPLACEMENT PROCESS

Patent #:	10340290	Issue Dt:	07/02/2019	Application #:	15706048	Filing Dt:	09/15/2017
Publication #:	US20190088680	Pub Dt:	03/21/2019
Title:	STACKED SOI SEMICONDUCTOR DEVICES WITH BACK BIAS MECHANISM

Patent #:	10053794	Issue Dt:	08/21/2018	Application #:	15708281	Filing Dt:	09/19/2017
Publication #:	US20180016699	Pub Dt:	01/18/2018
Title:	ELECTROPLATING SYSTEM AND METHOD OF USING ELECTROPLATING SYSTEM FOR CONTROLLING CONCENTRATION OF ORGANIC ADDITIVES IN ELECTROPLATING SOLUTION

Patent #:	10665586	Issue Dt:	05/26/2020	Application #:	15708911	Filing Dt:	09/19/2017
Publication #:	US20180006028	Pub Dt:	01/04/2018
Title:	METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE

Patent #:	10283621	Issue Dt:	05/07/2019	Application #:	15709500	Filing Dt:	09/20/2017
Publication #:	US20190088767	Pub Dt:	03/21/2019
Title:	METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED GATES AND GATE EXTENSIONS AND THE RESULTING STRUCTURE

Patent #:	10396155	Issue Dt:	08/27/2019	Application #:	15709671	Filing Dt:	09/20/2017
Publication #:	US20190088742	Pub Dt:	03/21/2019
Title:	SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN CONTACTS AND A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

Patent #:	10170377	Issue Dt:	01/01/2019	Application #:	15709704	Filing Dt:	09/20/2017
Title:	MEMORY CELL WITH RECESSED SOURCE/DRAIN CONTACTS TO REDUCE CAPACITANCE

Patent #:	10366919	Issue Dt:	07/30/2019	Application #:	15709956	Filing Dt:	09/20/2017
Publication #:	US20190088541	Pub Dt:	03/21/2019
Title:	FULLY ALIGNED VIA IN GROUND RULE REGION

Patent #:	10121878	Issue Dt:	11/06/2018	Application #:	15711415	Filing Dt:	09/21/2017
Title:	LDMOS FINFET STRUCTURES WITH MULTIPLE GATE STRUCTURES

Patent #:	10522655	Issue Dt:	12/31/2019	Application #:	15711674	Filing Dt:	09/21/2017
Publication #:	US20180012973	Pub Dt:	01/11/2018
Title:	DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPACER WIDTHS & DUAL RAISED SOURCE DRAIN EXPITAXIAL SILICON AND TRIPLE-NITRIDE SPACER INTEGRATION ENABLING HIGH-VOLTAGE EG DEVICE ON FDSOI

Patent #:	10297452	Issue Dt:	05/21/2019	Application #:	15712301	Filing Dt:	09/22/2017
Publication #:	US20190096677	Pub Dt:	03/28/2019
Title:	METHODS OF FORMING A GATE CONTACT STRUCTURE FOR A TRANSISTOR

Patent #:	10403742	Issue Dt:	09/03/2019	Application #:	15712748	Filing Dt:	09/22/2017
Publication #:	US20190097019	Pub Dt:	03/28/2019
Title:	FIELD-EFFECT TRANSISTORS WITH FINS FORMED BY A DAMASCENE-LIKE PROCESS

Patent #:	10283490	Issue Dt:	05/07/2019	Application #:	15713064	Filing Dt:	09/22/2017
Publication #:	US20180012877	Pub Dt:	01/11/2018
Title:	COMMUNICATING OPTICAL SIGNALS BETWEEN STACKED DIES

Patent #:	10242947	Issue Dt:	03/26/2019	Application #:	15713756	Filing Dt:	09/25/2017
Publication #:	US20180012845	Pub Dt:	01/11/2018
Title:	SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION

Patent #:	10090258	Issue Dt:	10/02/2018	Application #:	15713843	Filing Dt:	09/25/2017
Title:	CRACK-STOP STRUCTURE FOR AN IC PRODUCT AND METHODS OF MAKING SUCH A CRACK-STOP STRUCTURE

Patent #:	10068902	Issue Dt:	09/04/2018	Application #:	15715220	Filing Dt:	09/26/2017
Title:	INTEGRATED CIRCUIT STRUCTURE INCORPORATING NON-PLANAR FIELD EFFECT TRANSISTORS WITH DIFFERENT CHANNEL REGION HEIGHTS AND METHOD

Patent #:	10418455	Issue Dt:	09/17/2019	Application #:	15716287	Filing Dt:	09/26/2017
Publication #:	US20190097015	Pub Dt:	03/28/2019
Title:	METHODS, APPARATUS AND SYSTEM FOR STRINGER DEFECT REDUCTION IN A TRENCH CUT REGION OF A FINFET DEVICE

Patent #:	10096674	Issue Dt:	10/09/2018	Application #:	15717336	Filing Dt:	09/27/2017
Publication #:	US20180019305	Pub Dt:	01/18/2018
Title:	STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)

Patent #:	10276683	Issue Dt:	04/30/2019	Application #:	15718958	Filing Dt:	09/28/2017
Publication #:	US20180019313	Pub Dt:	01/18/2018
Title:	COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIGHTS AND METHODS OF MANUFACTURING SAME

Patent #:	10741556	Issue Dt:	08/11/2020	Application #:	15719014	Filing Dt:	09/28/2017
Publication #:	US20180233505	Pub Dt:	08/16/2018
Title:	SELF-ALIGNED SACRIFICIAL EPITAXIAL CAPPING FOR TRENCH SILICIDE

Patent #:	9953834	Issue Dt:	04/24/2018	Application #:	15723232	Filing Dt:	10/03/2017
Title:	METHOD OF MAKING SELF-ALIGNED CONTINUITY CUTS IN MANDREL AND NON-MANDREL METAL LINES

Patent #:	9984933	Issue Dt:	05/29/2018	Application #:	15723416	Filing Dt:	10/03/2017
Title:	SILICON LINER FOR STI CMP STOP IN FINFET

Patent #:	10249538	Issue Dt:	04/02/2019	Application #:	15723472	Filing Dt:	10/03/2017
Publication #:	US20190103319	Pub Dt:	04/04/2019
Title:	METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE LENGTHS AND A RESULTING STRUCTURE

Patent #:	10347529	Issue Dt:	07/09/2019	Application #:	15724431	Filing Dt:	10/04/2017
Publication #:	US20190103310	Pub Dt:	04/04/2019
Title:	INTERCONNECT STRUCTURES

Patent #:	10388567	Issue Dt:	08/20/2019	Application #:	15724493	Filing Dt:	10/04/2017
Publication #:	US20180047626	Pub Dt:	02/15/2018
Title:	THRU-SILICON-VIA STRUCTURES

Patent #:	10056331	Issue Dt:	08/21/2018	Application #:	15724563	Filing Dt:	10/04/2017
Publication #:	US20180033726	Pub Dt:	02/01/2018
Title:	PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF

Patent #:	NONE	Issue Dt:		Application #:	15725524	Filing Dt:	10/05/2017
Publication #:	US20190107672	Pub Dt:	04/11/2019
Title:	NON-PLANAR WAVEGUIDE STRUCTURES

Patent #:	10475890	Issue Dt:	11/12/2019	Application #:	15728070	Filing Dt:	10/09/2017
Publication #:	US20190109197	Pub Dt:	04/11/2019
Title:	SCALED MEMORY STRUCTURES OR OTHER LOGIC DEVICES WITH MIDDLE OF THE LINE CUTS

Patent #:	10559503	Issue Dt:	02/11/2020	Application #:	15728445	Filing Dt:	10/09/2017
Publication #:	US20180033701	Pub Dt:	02/01/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

Patent #:	10069011	Issue Dt:	09/04/2018	Application #:	15728615	Filing Dt:	10/10/2017
Publication #:	US20180138308	Pub Dt:	05/17/2018
Title:	METHOD FOR FABRICATING A FINFET METALLIZATION ARCHITECTURE USING A SELF-ALIGNED CONTACT ETCH

Patent #:	10290544	Issue Dt:	05/14/2019	Application #:	15728632	Filing Dt:	10/10/2017
Publication #:	US20190109045	Pub Dt:	04/11/2019
Title:	METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES TO SEMICONDUCTOR DEVICES AND THE RESULTING STRUCTURES

Patent #:	10580863	Issue Dt:	03/03/2020	Application #:	15728679	Filing Dt:	10/10/2017
Publication #:	US20190109192	Pub Dt:	04/11/2019
Title:	TRANSISTOR ELEMENT WITH REDUCED LATERAL ELECTRICAL FIELD

Patent #:	10056300	Issue Dt:	08/21/2018	Application #:	15729051	Filing Dt:	10/10/2017
Publication #:	US20180033700	Pub Dt:	02/01/2018
Title:	METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT

Patent #:	10014390	Issue Dt:	07/03/2018	Application #:	15729105	Filing Dt:	10/10/2017
Title:	INNER SPACER FORMATION FOR NANOSHEET FIELD-EFFECT TRANSISTORS WITH TALL SUSPENSIONS

Patent #:	10340229	Issue Dt:	07/02/2019	Application #:	15729774	Filing Dt:	10/11/2017
Publication #:	US20190109097	Pub Dt:	04/11/2019
Title:	SEMICONDUCTOR DEVICE WITH SUPERIOR CRACK RESISTIVITY IN THE METALLIZATION SYSTEM

Patent #:	10388514	Issue Dt:	08/20/2019	Application #:	15729815	Filing Dt:	10/11/2017
Publication #:	US20190108998	Pub Dt:	04/11/2019
Title:	ENGINEERING OF FERROELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY SURFACE POTENTIAL MODULATION

Patent #:	10453605	Issue Dt:	10/22/2019	Application #:	15729992	Filing Dt:	10/11/2017
Publication #:	US20190108942	Pub Dt:	04/11/2019
Title:	INSULATING INDUCTOR CONDUCTORS WITH AIR GAP USING ENERGY EVAPORATION MATERIAL (EEM)

Patent #:	10395752	Issue Dt:	08/27/2019	Application #:	15730078	Filing Dt:	10/11/2017
Publication #:	US20190108894	Pub Dt:	04/11/2019
Title:	MARGIN TEST FOR MULTIPLE-TIME PROGRAMMABLE MEMORY (MTPM) WITH SPLIT WORDLINES

Patent #:	10255987	Issue Dt:	04/09/2019	Application #:	15730107	Filing Dt:	10/11/2017
Publication #:	US20190108895	Pub Dt:	04/11/2019
Title:	MARGIN TEST FOR ONE-TIME PROGRAMMABLE MEMORY (OTPM) ARRAY WITH COMMON MODE CURRENT SOURCE

Patent #:	10177237	Issue Dt:	01/08/2019	Application #:	15782380	Filing Dt:	10/12/2017
Publication #:	US20180053831	Pub Dt:	02/22/2018
Title:	ETCH STOP FOR AIRGAP PROTECTION

Patent #:	10446659	Issue Dt:	10/15/2019	Application #:	15783270	Filing Dt:	10/13/2017
Publication #:	US20190115444	Pub Dt:	04/18/2019
Title:	NEGATIVE CAPACITANCE INTEGRATION THROUGH A GATE CONTACT

Patent #:	10446550	Issue Dt:	10/15/2019	Application #:	15783549	Filing Dt:	10/13/2017
Publication #:	US20190115346	Pub Dt:	04/18/2019
Title:	CUT INSIDE REPLACEMENT METAL GATE TRENCH TO MITIGATE N-P PROXIMITY EFFECT

Patent #:	10802393	Issue Dt:	10/13/2020	Application #:	15784408	Filing Dt:	10/16/2017
Publication #:	US20190113836	Pub Dt:	04/18/2019
Title:	EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY MASK

Patent #:	10236358	Issue Dt:	03/19/2019	Application #:	15784445	Filing Dt:	10/16/2017
Title:	INTEGRATION OF GATE STRUCTURES AND SPACERS WITH AIR GAPS

Patent #:	10141414	Issue Dt:	11/27/2018	Application #:	15784500	Filing Dt:	10/16/2017
Title:	NEGATIVE CAPACITANCE MATCHING IN GATE ELECTRODE STRUCTURES

Patent #:	10103247	Issue Dt:	10/16/2018	Application #:	15785631	Filing Dt:	10/17/2017
Title:	VERTICAL TRANSISTOR HAVING BURIED CONTACT, AND CONTACTS USING WORK FUNCTION METALS AND SILICIDES

Patent #:	10679937	Issue Dt:	06/09/2020	Application #:	15785665	Filing Dt:	10/17/2017
Publication #:	US20180040555	Pub Dt:	02/08/2018
Title:	DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT

Patent #:	10056377	Issue Dt:	08/21/2018	Application #:	15786164	Filing Dt:	10/17/2017
Publication #:	US20180145073	Pub Dt:	05/24/2018
Title:	METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING

Patent #:	10439026	Issue Dt:	10/08/2019	Application #:	15786284	Filing Dt:	10/17/2017
Publication #:	US20190115426	Pub Dt:	04/18/2019
Title:	FINS WITH SINGLE DIFFUSION BREAK FACET IMPROVEMENT USING EPITAXIAL INSULATOR

Patent #:	10170484	Issue Dt:	01/01/2019	Application #:	15787009	Filing Dt:	10/18/2017
Title:	INTEGRATED CIRCUIT STRUCTURE INCORPORATING MULTIPLE GATE-ALL-AROUND FIELD EFFECT TRANSISTORS HAVING DIFFERENT DRIVE CURRENTS AND METHOD

Patent #:	10224276	Issue Dt:	03/05/2019	Application #:	15787146	Filing Dt:	10/18/2017
Publication #:	US20180040556	Pub Dt:	02/08/2018
Title:	INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE

Patent #:	10211103	Issue Dt:	02/19/2019	Application #:	15787257	Filing Dt:	10/18/2017
Title:	ADVANCED STRUCTURE FOR SELF-ALIGNED CONTACT AND METHOD FOR PRODUCING THE SAME

Patent #:	10083891	Issue Dt:	09/25/2018	Application #:	15789108	Filing Dt:	10/20/2017
Title:	MEMORY HAVING THERMOELECTRIC HEAT PUMP AND RELATED IC CHIP PACKAGE AND METHOD

Patent #:	10164041	Issue Dt:	12/25/2018	Application #:	15790216	Filing Dt:	10/23/2017
Title:	METHOD OF FORMING GATE-ALL-AROUND (GAA) FINFET AND GAA FINFET FORMED THEREBY

Patent #:	10177029	Issue Dt:	01/08/2019	Application #:	15790249	Filing Dt:	10/23/2017
Title:	INTEGRATION OF AIR GAPS WITH BACK-END-OF-LINE STRUCTURES

Patent #:	10026494	Issue Dt:	07/17/2018	Application #:	15790543	Filing Dt:	10/23/2017
Publication #:	US20180075921	Pub Dt:	03/15/2018
Title:	WORD LINE VOLTAGE GENERATOR FOR CALCULATING OPTIMUM WORD LINE VOLTAGE LEVEL FOR PROGRAMMABLE MEMORY ARRAY

Patent #:	10164101	Issue Dt:	12/25/2018	Application #:	15790707	Filing Dt:	10/23/2017
Title:	TRANSISTOR WITH IMPROVED CHANNEL MOBILITY

Patent #:	10096557	Issue Dt:	10/09/2018	Application #:	15791568	Filing Dt:	10/24/2017
Publication #:	US20180061777	Pub Dt:	03/01/2018
Title:	TILED-STRESS-ALLEVIATING PAD STRUCTURE

Patent #:	10651284	Issue Dt:	05/12/2020	Application #:	15791650	Filing Dt:	10/24/2017
Publication #:	US20190123162	Pub Dt:	04/25/2019
Title:	METHODS OF FORMING GATE CONTACT STRUCTURES AND CROSS-COUPLED CONTACT STRUCTURES FOR TRANSISTOR DEVICES

Patent #:	10134633	Issue Dt:	11/20/2018	Application #:	15791658	Filing Dt:	10/24/2017
Title:	SELF-ALIGNED CONTACT WITH CMP STOP LAYER

Patent #:	10236215	Issue Dt:	03/19/2019	Application #:	15791711	Filing Dt:	10/24/2017
Title:	METHODS OF FORMING GATE CONTACT STRUCTURES AND CROSS-COUPLED CONTACT STRUCTURES FOR TRANSISTOR DEVICES

Patent #:	10170574	Issue Dt:	01/01/2019	Application #:	15792206	Filing Dt:	10/24/2017
Publication #:	US20180047824	Pub Dt:	02/15/2018
Title:	HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

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100

Patent #:	10096587	Issue Dt:	10/09/2018	Application #:	15794688	Filing Dt:	10/26/2017
Title:	FIN-BASED DIODE STRUCTURES WITH A REALIGNED FEATURE LAYOUT

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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