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Patent Assignment Details
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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 75 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
10481592
Issue Dt:
11/19/2019
Application #:
15795431
Filing Dt:
10/27/2017
Publication #:
US20190129390
Pub Dt:
05/02/2019
Title:
SELECTING MANUFACTURING SETTINGS BASED ON HISTORICAL DATA FROM MANUFACTURING TOOLS
2
Patent #:
10355104
Issue Dt:
07/16/2019
Application #:
15795833
Filing Dt:
10/27/2017
Publication #:
US20190131432
Pub Dt:
05/02/2019
Title:
SINGLE-CURVATURE CAVITY FOR SEMICONDUCTOR EPITAXY
3
Patent #:
10283469
Issue Dt:
05/07/2019
Application #:
15795849
Filing Dt:
10/27/2017
Publication #:
US20190131259
Pub Dt:
05/02/2019
Title:
METHOD OF FORMING A PASSIVATION LAYER
4
Patent #:
10297675
Issue Dt:
05/21/2019
Application #:
15795879
Filing Dt:
10/27/2017
Publication #:
US20190131433
Pub Dt:
05/02/2019
Title:
DUAL-CURVATURE CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH
5
Patent #:
10522679
Issue Dt:
12/31/2019
Application #:
15797380
Filing Dt:
10/30/2017
Publication #:
US20190131452
Pub Dt:
05/02/2019
Title:
SELECTIVE SHALLOW TRENCH ISOLATION (STI) FILL FOR STRESS ENGINEERING IN SEMICONDUCTOR STRUCTURES
6
Patent #:
10026740
Issue Dt:
07/17/2018
Application #:
15797533
Filing Dt:
10/30/2017
Title:
DRAM STRUCTURE WITH A SINGLE DIFFUSION BREAK
7
Patent #:
10290712
Issue Dt:
05/14/2019
Application #:
15797606
Filing Dt:
10/30/2017
Publication #:
US20190131406
Pub Dt:
05/02/2019
Title:
LDMOS FINFET STRUCTURES WITH SHALLOW TRENCH ISOLATION INSIDE THE FIN
8
Patent #:
10204784
Issue Dt:
02/12/2019
Application #:
15797633
Filing Dt:
10/30/2017
Title:
METHODS OF FORMING FEATURES ON INTEGRATED CIRCUIT PRODUCTS
9
Patent #:
10121893
Issue Dt:
11/06/2018
Application #:
15797634
Filing Dt:
10/30/2017
Publication #:
US20180061976
Pub Dt:
03/01/2018
Title:
INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME
10
Patent #:
10164006
Issue Dt:
12/25/2018
Application #:
15797701
Filing Dt:
10/30/2017
Title:
LDMOS FINFET STRUCTURES WITH TRENCH ISOLATION IN THE DRAIN EXTENSION
11
Patent #:
10483369
Issue Dt:
11/19/2019
Application #:
15797723
Filing Dt:
10/30/2017
Publication #:
US20190131428
Pub Dt:
05/02/2019
Title:
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON TRANSISTOR DEVICES
12
Patent #:
10163635
Issue Dt:
12/25/2018
Application #:
15797794
Filing Dt:
10/30/2017
Title:
ASYMMETRIC SPACER FOR PREVENTING EPITAXIAL MERGE BETWEEN ADJACENT DEVICES OF A SEMICONDUCTOR AND RELATED METHOD
13
Patent #:
10453936
Issue Dt:
10/22/2019
Application #:
15797837
Filing Dt:
10/30/2017
Publication #:
US20190131429
Pub Dt:
05/02/2019
Title:
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON TRANSISTOR DEVICES
14
Patent #:
10164010
Issue Dt:
12/25/2018
Application #:
15798546
Filing Dt:
10/31/2017
Title:
FINFET DIFFUSION BREAK HAVING PROTECTIVE LINER IN FIN INSULATOR
15
Patent #:
10026753
Issue Dt:
07/17/2018
Application #:
15799243
Filing Dt:
10/31/2017
Publication #:
US20180053789
Pub Dt:
02/22/2018
Title:
METHOD FOR COMPENSATING FOR TEMPERATURE EFFECTS IN SEMICONDUCTOR DEVICE STRUCTURES USING A DIODE STRUCTURE AND A TUNABLE RESISTOR
16
Patent #:
10461067
Issue Dt:
10/29/2019
Application #:
15799600
Filing Dt:
10/31/2017
Publication #:
US20180068993
Pub Dt:
03/08/2018
Title:
THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
17
Patent #:
10083858
Issue Dt:
09/25/2018
Application #:
15800551
Filing Dt:
11/01/2017
Publication #:
US20180174896
Pub Dt:
06/21/2018
Title:
INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS
18
Patent #:
10283617
Issue Dt:
05/07/2019
Application #:
15800563
Filing Dt:
11/01/2017
Publication #:
US20190131430
Pub Dt:
05/02/2019
Title:
HYBRID SPACER INTEGRATION FOR FIELD-EFFECT TRANSISTORS
19
Patent #:
10211206
Issue Dt:
02/19/2019
Application #:
15800905
Filing Dt:
11/01/2017
Title:
TWO-PORT VERTICAL SRAM CIRCUIT STRUCTURE AND METHOD FOR PRODUCING THE SAME
20
Patent #:
10236291
Issue Dt:
03/19/2019
Application #:
15801023
Filing Dt:
11/01/2017
Publication #:
US20180061832
Pub Dt:
03/01/2018
Title:
METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES
21
Patent #:
10224207
Issue Dt:
03/05/2019
Application #:
15801458
Filing Dt:
11/02/2017
Publication #:
US20180068858
Pub Dt:
03/08/2018
Title:
FORMING A CONTACT FOR A TALL FIN TRANSISTOR
22
Patent #:
10446484
Issue Dt:
10/15/2019
Application #:
15801501
Filing Dt:
11/02/2017
Publication #:
US20180166381
Pub Dt:
06/14/2018
Title:
THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
23
Patent #:
10699973
Issue Dt:
06/30/2020
Application #:
15804165
Filing Dt:
11/06/2017
Publication #:
US20190139841
Pub Dt:
05/09/2019
Title:
SEMICONDUCTOR TEST STRUCTURE AND METHOD FOR FORMING THE SAME
24
Patent #:
10403629
Issue Dt:
09/03/2019
Application #:
15804556
Filing Dt:
11/06/2017
Publication #:
US20190139967
Pub Dt:
05/09/2019
Title:
NOVEL SIX-TRANSISTOR (6T) SRAM CELL STRUCTURE
25
Patent #:
10510662
Issue Dt:
12/17/2019
Application #:
15805282
Filing Dt:
11/07/2017
Publication #:
US20190139892
Pub Dt:
05/09/2019
Title:
VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE AND METHODS OF MAKING SAME
26
Patent #:
10121884
Issue Dt:
11/06/2018
Application #:
15806532
Filing Dt:
11/08/2017
Publication #:
US20180069106
Pub Dt:
03/08/2018
Title:
FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS
27
Patent #:
10197730
Issue Dt:
02/05/2019
Application #:
15806931
Filing Dt:
11/08/2017
Title:
OPTICAL THROUGH SILICON VIA
28
Patent #:
10347543
Issue Dt:
07/09/2019
Application #:
15810557
Filing Dt:
11/13/2017
Publication #:
US20190148245
Pub Dt:
05/16/2019
Title:
FDSOI SEMICONDUCTOR DEVICE WITH CONTACT ENHANCEMENT LAYER AND METHOD OF MANUFACTURING
29
Patent #:
10283365
Issue Dt:
05/07/2019
Application #:
15810638
Filing Dt:
11/13/2017
Publication #:
US20190148149
Pub Dt:
05/16/2019
Title:
TECHNIQUE AND RELATED SEMICONDUCTOR DEVICES BASED ON CRYSTALLINE SEMICONDUCTOR MATERIAL FORMED ON THE BASIS OF DEPOSITED AMORPHOUS SEMICONDUCTOR MATERIAL
30
Patent #:
10170473
Issue Dt:
01/01/2019
Application #:
15811745
Filing Dt:
11/14/2017
Title:
FORMING LONG CHANNEL FinFET WITH SHORT CHANNEL VERTICAL FinFET AND RELATED INTEGRATED CIRCUIT
31
Patent #:
10157796
Issue Dt:
12/18/2018
Application #:
15811953
Filing Dt:
11/14/2017
Title:
FORMING OF MARKING TRENCHES IN STRUCTURE FOR MULTIPLE PATTERNING LITHOGRAPHY
32
Patent #:
10090382
Issue Dt:
10/02/2018
Application #:
15811957
Filing Dt:
11/14/2017
Title:
INTEGRATED CIRCUIT STRUCTURE INCLUDING SINGLE DIFFUSION BREAK AND END ISOLATION REGION, AND METHODS OF FORMING SAME
33
Patent #:
10388652
Issue Dt:
08/20/2019
Application #:
15811961
Filing Dt:
11/14/2017
Publication #:
US20190148373
Pub Dt:
05/16/2019
Title:
INTEGRATED CIRCUIT STRUCTURE INCLUDING SINGLE DIFFUSION BREAK ABUTTING END ISOLATION REGION, AND METHODS OF FORMING SAME
34
Patent #:
10403548
Issue Dt:
09/03/2019
Application #:
15811965
Filing Dt:
11/14/2017
Publication #:
US20190148242
Pub Dt:
05/16/2019
Title:
FORMING SINGLE DIFFUSION BREAK AND END ISOLATION REGION AFTER METAL GATE REPLACEMENT, AND RELATED STRUCTURE
35
Patent #:
10461155
Issue Dt:
10/29/2019
Application #:
15811990
Filing Dt:
11/14/2017
Publication #:
US20190148492
Pub Dt:
05/16/2019
Title:
EPITAXIAL REGION FOR EMBEDDED SOURCE/DRAIN REGION HAVING UNIFORM THICKNESS
36
Patent #:
10224236
Issue Dt:
03/05/2019
Application #:
15813399
Filing Dt:
11/15/2017
Publication #:
US20180076082
Pub Dt:
03/15/2018
Title:
FORMING AIR GAP
37
Patent #:
10096606
Issue Dt:
10/09/2018
Application #:
15813471
Filing Dt:
11/15/2017
Title:
METHODS OF FORMING A GATE STRUCTURE-TO-SOURCE/DRAIN CONDUCTIVE CONTACT ON VERTICAL TRANSISTOR DEVICES AND THE RESULTING TRANSISTOR DEVICES
38
Patent #:
10192819
Issue Dt:
01/29/2019
Application #:
15814435
Filing Dt:
11/16/2017
Title:
INTEGRATED CIRCUIT STRUCTURE INCORPORATING STACKED FIELD EFFECT TRANSISTORS
39
Patent #:
10304832
Issue Dt:
05/28/2019
Application #:
15814440
Filing Dt:
11/16/2017
Publication #:
US20190148376
Pub Dt:
05/16/2019
Title:
INTEGRATED CIRCUIT STRUCTURE INCORPORATING STACKED FIELD EFFECT TRANSISTORS AND METHOD
40
Patent #:
10090193
Issue Dt:
10/02/2018
Application #:
15814445
Filing Dt:
11/16/2017
Title:
INTEGRATED CIRCUIT STRUCTURE INCORPORATING A STACKED PAIR OF FIELD EFFECT TRANSISTORS AND A BURIED INTERCONNECT AND METHOD
41
Patent #:
10269812
Issue Dt:
04/23/2019
Application #:
15814724
Filing Dt:
11/16/2017
Publication #:
US20190148494
Pub Dt:
05/16/2019
Title:
FORMING CONTACTS FOR VFETS
42
Patent #:
10580581
Issue Dt:
03/03/2020
Application #:
15815308
Filing Dt:
11/16/2017
Publication #:
US20190148072
Pub Dt:
05/16/2019
Title:
HIGH-DENSITY METAL-INSULATOR-METAL CAPACITORS
43
Patent #:
10229987
Issue Dt:
03/12/2019
Application #:
15815857
Filing Dt:
11/17/2017
Publication #:
US20180076299
Pub Dt:
03/15/2018
Title:
EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
44
Patent #:
10192887
Issue Dt:
01/29/2019
Application #:
15817362
Filing Dt:
11/20/2017
Publication #:
US20180090516
Pub Dt:
03/29/2018
Title:
METHOD TO IMPROVE CRYSTALLINE REGROWTH
45
Patent #:
10224396
Issue Dt:
03/05/2019
Application #:
15817629
Filing Dt:
11/20/2017
Title:
DEEP TRENCH ISOLATION STRUCTURES
46
Patent #:
10585346
Issue Dt:
03/10/2020
Application #:
15819213
Filing Dt:
11/21/2017
Publication #:
US20190072846
Pub Dt:
03/07/2019
Title:
SEMICONDUCTOR FABRICATION DESIGN RULE LOOPHOLE CHECKING FOR DESIGN FOR MANUFACTURABILITY OPTIMIZATION
47
Patent #:
10930777
Issue Dt:
02/23/2021
Application #:
15819825
Filing Dt:
11/21/2017
Publication #:
US20190157451
Pub Dt:
05/23/2019
Title:
LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICE ON FULLY DEPLETED SILICON ON INSULATOR (FDSOI) ENABLING HIGH INPUT VOLTAGE
48
Patent #:
10256158
Issue Dt:
04/09/2019
Application #:
15820477
Filing Dt:
11/22/2017
Title:
INSULATED EPITAXIAL STRUCTURES IN NANOSHEET COMPLEMENTARY FIELD EFFECT TRANSISTORS
49
Patent #:
10403574
Issue Dt:
09/03/2019
Application #:
15820602
Filing Dt:
11/22/2017
Publication #:
US20180096933
Pub Dt:
04/05/2018
Title:
METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
50
Patent #:
10483377
Issue Dt:
11/19/2019
Application #:
15821091
Filing Dt:
11/22/2017
Publication #:
US20180097089
Pub Dt:
04/05/2018
Title:
DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE
51
Patent #:
10438853
Issue Dt:
10/08/2019
Application #:
15821684
Filing Dt:
11/22/2017
Publication #:
US20190157157
Pub Dt:
05/23/2019
Title:
METHODS, APPARATUS AND SYSTEM FOR FORMING A FINFET DEVICE COMPRISING A FIRST PORTION CAPABLE OF OPERATING AT A FIRST VOLTAGE AND A SECOND PORTION CAPABLE OF OPERATING AT A SECOND VOLTAGE
52
Patent #:
11288430
Issue Dt:
03/29/2022
Application #:
15822661
Filing Dt:
11/27/2017
Publication #:
US20190163853
Pub Dt:
05/30/2019
Title:
PRODUCING MODELS FOR DYNAMICALLY DEPLETED TRANSISTORS USING SYSTEMS HAVING SIMULATION CIRCUITS
53
Patent #:
10879180
Issue Dt:
12/29/2020
Application #:
15823899
Filing Dt:
11/28/2017
Publication #:
US20190164898
Pub Dt:
05/30/2019
Title:
FINFET WITH ETCH-SELECTIVE SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER
54
Patent #:
10353288
Issue Dt:
07/16/2019
Application #:
15824293
Filing Dt:
11/28/2017
Publication #:
US20190163054
Pub Dt:
05/30/2019
Title:
LITHO-LITHO-ETCH DOUBLE PATTERNING METHOD
55
Patent #:
10361311
Issue Dt:
07/23/2019
Application #:
15825409
Filing Dt:
11/29/2017
Publication #:
US20180090327
Pub Dt:
03/29/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL
56
Patent #:
10283487
Issue Dt:
05/07/2019
Application #:
15826799
Filing Dt:
11/30/2017
Publication #:
US20180233488
Pub Dt:
08/16/2018
Title:
Methods of Forming Integrated Circuit Package with Thermally Conductive Pillar
57
Patent #:
10707167
Issue Dt:
07/07/2020
Application #:
15826939
Filing Dt:
11/30/2017
Publication #:
US20180090447
Pub Dt:
03/29/2018
Title:
CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
58
Patent #:
10263122
Issue Dt:
04/16/2019
Application #:
15828386
Filing Dt:
11/30/2017
Title:
METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF CONTACTS IN A VERTICAL FIELD EFFECT TRANSISTOR
59
Patent #:
10047431
Issue Dt:
08/14/2018
Application #:
15828624
Filing Dt:
12/01/2017
Publication #:
US20180087145
Pub Dt:
03/29/2018
Title:
DIRECTED SURFACE FUNCTIONALIZATION ON SELECTED SURFACE AREAS OF TOPOGRAPHICAL FEATURES WITH NANOMETER RESOLUTION
60
Patent #:
10147648
Issue Dt:
12/04/2018
Application #:
15830217
Filing Dt:
12/04/2017
Title:
VERTICAL FIN GATE STRUCTURE FOR RF DEVICE
61
Patent #:
10504906
Issue Dt:
12/10/2019
Application #:
15830671
Filing Dt:
12/04/2017
Title:
FINFET SRAM LAYOUT AND METHOD OF MAKING THE SAME
62
Patent #:
10249633
Issue Dt:
04/02/2019
Application #:
15831833
Filing Dt:
12/05/2017
Publication #:
US20180108668
Pub Dt:
04/19/2018
Title:
FLASH MEMORY DEVICE
63
Patent #:
10170544
Issue Dt:
01/01/2019
Application #:
15833285
Filing Dt:
12/06/2017
Publication #:
US20180102409
Pub Dt:
04/12/2018
Title:
INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTECTION LAYER FORMED ON AN ISOLATION REGION
64
Patent #:
10319626
Issue Dt:
06/11/2019
Application #:
15834151
Filing Dt:
12/07/2017
Publication #:
US20190181040
Pub Dt:
06/13/2019
Title:
INTERCONNECTS WITH CUTS FORMED BY BLOCK PATTERNING
65
Patent #:
10566411
Issue Dt:
02/18/2020
Application #:
15834443
Filing Dt:
12/07/2017
Publication #:
US20190181215
Pub Dt:
06/13/2019
Title:
ON-CHIP RESISTORS WITH DIRECT WIRING CONNECTIONS
66
Patent #:
9966310
Issue Dt:
05/08/2018
Application #:
15837279
Filing Dt:
12/11/2017
Publication #:
US20180108566
Pub Dt:
04/19/2018
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
67
Patent #:
10497612
Issue Dt:
12/03/2019
Application #:
15837671
Filing Dt:
12/11/2017
Publication #:
US20190181042
Pub Dt:
06/13/2019
Title:
METHODS OF FORMING CONTACT STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS
68
Patent #:
10651293
Issue Dt:
05/12/2020
Application #:
15840835
Filing Dt:
12/13/2017
Publication #:
US20180114850
Pub Dt:
04/26/2018
Title:
METHODS OF SIMULTANEOUSLY FORMING BOTTOM AND TOP SPACERS ON A VERTICAL TRANSISTOR DEVICE
69
Patent #:
10211168
Issue Dt:
02/19/2019
Application #:
15841372
Filing Dt:
12/14/2017
Title:
DISSIPATION OF STATIC CHARGE FROM WIRING LAYERS DURING MANUFACTURING
70
Patent #:
10014298
Issue Dt:
07/03/2018
Application #:
15844840
Filing Dt:
12/18/2017
Title:
METHOD OF FORMING FIELD EFFECT TRANSISTORS WITH REPLACEMENT METAL GATES AND CONTACTS AND RESULTING STRUCTURE
71
Patent #:
NONE
Issue Dt:
Application #:
15845313
Filing Dt:
12/18/2017
Publication #:
US20180172609
Pub Dt:
06/21/2018
Title:
METHOD AND SYSTEM FOR NON-DESTRUCTIVE METROLOGY OF THIN LAYERS
72
Patent #:
10304683
Issue Dt:
05/28/2019
Application #:
15845340
Filing Dt:
12/18/2017
Publication #:
US20190131133
Pub Dt:
05/02/2019
Title:
EARLY GATE SILICIDATION IN TRANSISTOR ELEMENTS
73
Patent #:
10229855
Issue Dt:
03/12/2019
Application #:
15846365
Filing Dt:
12/19/2017
Publication #:
US20180122702
Pub Dt:
05/03/2018
Title:
METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES
74
Patent #:
10374029
Issue Dt:
08/06/2019
Application #:
15848324
Filing Dt:
12/20/2017
Publication #:
US20180122891
Pub Dt:
05/03/2018
Title:
SEMICONDUCTOR DEVICE RESISTOR STRUCTURE
75
Patent #:
10163677
Issue Dt:
12/25/2018
Application #:
15848371
Filing Dt:
12/20/2017
Publication #:
US20180138079
Pub Dt:
05/17/2018
Title:
ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS
76
Patent #:
10236343
Issue Dt:
03/19/2019
Application #:
15848591
Filing Dt:
12/20/2017
Publication #:
US20180190768
Pub Dt:
07/05/2018
Title:
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Title:
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Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
10/22/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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