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Patent Assignment Details
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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 78 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
10355646
Issue Dt:
07/16/2019
Application #:
15967172
Filing Dt:
04/30/2018
Publication #:
US20190190453
Pub Dt:
06/20/2019
Title:
POWER AMPLIFIER FOR MILLIMETER WAVE DEVICES
2
Patent #:
10944437
Issue Dt:
03/09/2021
Application #:
15967281
Filing Dt:
04/30/2018
Publication #:
US20190312603
Pub Dt:
10/10/2019
Title:
MULTIBAND RECEIVERS FOR MILLIMETER WAVE DEVICES
3
Patent #:
10559656
Issue Dt:
02/11/2020
Application #:
15968968
Filing Dt:
05/02/2018
Publication #:
US20190341448
Pub Dt:
11/07/2019
Title:
WRAP-ALL-AROUND CONTACT FOR NANOSHEET-FET AND METHOD OF FORMING SAME
4
Patent #:
10429582
Issue Dt:
10/01/2019
Application #:
15968997
Filing Dt:
05/02/2018
Title:
WAVEGUIDE-TO-WAVEGUIDE COUPLERS WITH MULTIPLE TAPERS
5
Patent #:
10586860
Issue Dt:
03/10/2020
Application #:
15970217
Filing Dt:
05/03/2018
Publication #:
US20190341475
Pub Dt:
11/07/2019
Title:
A METHOD OF MANUFACTURING FINFET DEVICES USING NARROW AND WIDE GATE CUT OPENINGS IN CONJUNCTION WITH A REPLACEMENT METAL GATE PROCESS
6
Patent #:
10263418
Issue Dt:
04/16/2019
Application #:
15971265
Filing Dt:
05/04/2018
Publication #:
US20180254630
Pub Dt:
09/06/2018
Title:
METHOD TO PROTECT SENSITIVE DEVICES FROM ELECTROSTATIC DISCHARGE DAMAGE
7
Patent #:
10628551
Issue Dt:
04/21/2020
Application #:
15971280
Filing Dt:
05/04/2018
Publication #:
US20190340326
Pub Dt:
11/07/2019
Title:
PREVENTING CORNER VIOLATIONS IN FILL REGION OF LAYOUT USING EXCLUSION LAYER
8
Patent #:
10170614
Issue Dt:
01/01/2019
Application #:
15971419
Filing Dt:
05/04/2018
Publication #:
US20180254343
Pub Dt:
09/06/2018
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE
9
Patent #:
10332803
Issue Dt:
06/25/2019
Application #:
15973817
Filing Dt:
05/08/2018
Title:
HYBRID GATE-ALL-AROUND (GAA) FIELD EFFECT TRANSISTOR (FET) STRUCTURE AND METHOD OF FORMING
10
Patent #:
10600876
Issue Dt:
03/24/2020
Application #:
15974037
Filing Dt:
05/08/2018
Publication #:
US20190348508
Pub Dt:
11/14/2019
Title:
METHODS FOR CHAMFERING WORK FUNCTION MATERIAL LAYERS IN GATE CAVITIES HAVING VARYING WIDTHS
11
Patent #:
10241269
Issue Dt:
03/26/2019
Application #:
15974252
Filing Dt:
05/08/2018
Title:
GRATING COUPLERS WITH MULTIPLE CONFIGURATIONS
12
Patent #:
10636890
Issue Dt:
04/28/2020
Application #:
15974282
Filing Dt:
05/08/2018
Publication #:
US20190348517
Pub Dt:
11/14/2019
Title:
CHAMFERED REPLACEMENT GATE STRUCTURES
13
Patent #:
10910308
Issue Dt:
02/02/2021
Application #:
15975041
Filing Dt:
05/09/2018
Publication #:
US20190348365
Pub Dt:
11/14/2019
Title:
DUAL THICKNESS FUSE STRUCTURES
14
Patent #:
10438890
Issue Dt:
10/08/2019
Application #:
15976300
Filing Dt:
05/10/2018
Publication #:
US20180261538
Pub Dt:
09/13/2018
Title:
INTERCONNECT STRUCTURE HAVING POWER RAIL STRUCTURE AND RELATED METHOD
15
Patent #:
10418272
Issue Dt:
09/17/2019
Application #:
15976326
Filing Dt:
05/10/2018
Title:
METHODS, APPARATUS, AND SYSTEM FOR A SEMICONDUCTOR DEVICE COMPRISING GATES WITH SHORT HEIGHTS
16
Patent #:
11257672
Issue Dt:
02/22/2022
Application #:
15978334
Filing Dt:
05/14/2018
Publication #:
US20190348280
Pub Dt:
11/14/2019
Title:
SEMICONDUCTOR DEVICES INCLUDING ACTIVE REGIONS IN RAM AREAS WITH DEPOSITION DETERMINED PITCH
17
Patent #:
10574245
Issue Dt:
02/25/2020
Application #:
15979263
Filing Dt:
05/14/2018
Publication #:
US20190296751
Pub Dt:
09/26/2019
Title:
DIGITALLY CONTROLLED OSCILLATOR FOR A MILLIMETER WAVE SEMICONDUCTOR DEVICE
18
Patent #:
10692812
Issue Dt:
06/23/2020
Application #:
15980085
Filing Dt:
05/15/2018
Publication #:
US20190355658
Pub Dt:
11/21/2019
Title:
INTERCONNECTS WITH VARIABLE SPACE MANDREL CUTS FORMED BY BLOCK PATTERNING
19
Patent #:
10804379
Issue Dt:
10/13/2020
Application #:
15980436
Filing Dt:
05/15/2018
Publication #:
US20190355838
Pub Dt:
11/21/2019
Title:
FINFET DEVICE AND METHOD OF MANUFACTURING
20
Patent #:
10388565
Issue Dt:
08/20/2019
Application #:
15982076
Filing Dt:
05/17/2018
Publication #:
US20180269103
Pub Dt:
09/20/2018
Title:
CHAMFERLESS VIA STRUCTURES
21
Patent #:
10573593
Issue Dt:
02/25/2020
Application #:
15983168
Filing Dt:
05/18/2018
Publication #:
US20180269150
Pub Dt:
09/20/2018
Title:
METAL INTERCONNECTS FOR SUPER (SKIP) VIA INTEGRATION
22
Patent #:
10629602
Issue Dt:
04/21/2020
Application #:
15983627
Filing Dt:
05/18/2018
Publication #:
US20190355730
Pub Dt:
11/21/2019
Title:
STATIC RANDOM ACCESS MEMORY CELLS WITH ARRANGED VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS
23
Patent #:
10707175
Issue Dt:
07/07/2020
Application #:
15985838
Filing Dt:
05/22/2018
Publication #:
US20190363053
Pub Dt:
11/28/2019
Title:
ASYMMETRIC OVERLAY MARK FOR OVERLAY MEASUREMENT
24
Patent #:
10373877
Issue Dt:
08/06/2019
Application #:
15986390
Filing Dt:
05/22/2018
Title:
METHODS OF FORMING SOURCE/DRAIN CONTACT STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS
25
Patent #:
10790148
Issue Dt:
09/29/2020
Application #:
15987018
Filing Dt:
05/23/2018
Publication #:
US20190362978
Pub Dt:
11/28/2019
Title:
METHOD TO INCREASE EFFECTIVE GATE HEIGHT
26
Patent #:
10629707
Issue Dt:
04/21/2020
Application #:
15987101
Filing Dt:
05/23/2018
Publication #:
US20190363180
Pub Dt:
11/28/2019
Title:
FINFET STRUCTURE WITH BULBOUS UPPER INSULATIVE CAP PORTION TO PROTECT GATE HEIGHT, AND RELATED METHOD
27
Patent #:
10686450
Issue Dt:
06/16/2020
Application #:
15987257
Filing Dt:
05/23/2018
Publication #:
US20190363719
Pub Dt:
11/28/2019
Title:
TEST AND CHARACTERIZATION OF AN EMBEDDED PLL IN AN SOC DURING STARTUP
28
Patent #:
NONE
Issue Dt:
Application #:
15988145
Filing Dt:
05/24/2018
Publication #:
US20180277427
Pub Dt:
09/27/2018
Title:
STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS
29
Patent #:
10461173
Issue Dt:
10/29/2019
Application #:
15990186
Filing Dt:
05/25/2018
Title:
METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR FORMING SOURCE AND DRAIN REGIONS IN A VERTICAL FIELD EFFECT TRANSISTOR
30
Patent #:
10439064
Issue Dt:
10/08/2019
Application #:
15990956
Filing Dt:
05/29/2018
Title:
DUAL PORT VERTICAL TRANSISTOR MEMORY CELL
31
Patent #:
10192780
Issue Dt:
01/29/2019
Application #:
15991529
Filing Dt:
05/29/2018
Title:
SELF-ALIGNED MULTIPLE PATTERNING PROCESSES USING BI-LAYER MANDRELS AND CUTS FORMED WITH BLOCK MASKS
32
Patent #:
10276659
Issue Dt:
04/30/2019
Application #:
15992431
Filing Dt:
05/30/2018
Publication #:
US20180308930
Pub Dt:
10/25/2018
Title:
AIR GAP ADJACENT A BOTTOM SOURCE/DRAIN REGION OF VERTICAL TRANSISTOR DEVICE
33
Patent #:
10388732
Issue Dt:
08/20/2019
Application #:
15992942
Filing Dt:
05/30/2018
Title:
NANOSHEET FIELD-EFFECT TRANSISTORS INCLUDING A TWO-DIMENSIONAL SEMICONDUCTING MATERIAL
34
Patent #:
10566446
Issue Dt:
02/18/2020
Application #:
15992969
Filing Dt:
05/30/2018
Publication #:
US20190371918
Pub Dt:
12/05/2019
Title:
MITIGATION OF HOT CARRIER DAMAGE IN FIELD-EFFECT TRANSISTORS
35
Patent #:
10276442
Issue Dt:
04/30/2019
Application #:
15993017
Filing Dt:
05/30/2018
Title:
WRAP-AROUND CONTACTS FORMED WITH MULTIPLE SILICIDE LAYERS
36
Patent #:
10418285
Issue Dt:
09/17/2019
Application #:
15993142
Filing Dt:
05/30/2018
Title:
FIN FIELD-EFFECT TRANSISTOR (FINFET) AND METHOD OF PRODUCTION THEREOF
37
Patent #:
10438894
Issue Dt:
10/08/2019
Application #:
15993523
Filing Dt:
05/30/2018
Title:
CHIP-TO-CHIP AND CHIP-TO-SUBSTRATE INTERCONNECTIONS IN MULTI-CHIP SEMICONDUCTOR DEVICES
38
Patent #:
10475791
Issue Dt:
11/12/2019
Application #:
15994231
Filing Dt:
05/31/2018
Publication #:
US20190371796
Pub Dt:
12/05/2019
Title:
TRANSISTOR FINS WITH DIFFERENT THICKNESS GATE DIELECTRIC
39
Patent #:
10461186
Issue Dt:
10/29/2019
Application #:
15994392
Filing Dt:
05/31/2018
Title:
METHODS OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED CONTACTS AND THE RESULTING STRUCTURES
40
Patent #:
10608082
Issue Dt:
03/31/2020
Application #:
15994402
Filing Dt:
05/31/2018
Publication #:
US20190371887
Pub Dt:
12/05/2019
Title:
FIELD-EFFECT TRANSISTORS INCLUDING MULTIPLE GATE LENGTHS
41
Patent #:
10243059
Issue Dt:
03/26/2019
Application #:
15994614
Filing Dt:
05/31/2018
Publication #:
US20180277655
Pub Dt:
09/27/2018
Title:
SOURCE/DRAIN PARASITIC CAPACITANCE REDUCTION IN FINFET-BASED SEMICONDUCTOR STRUCTURE HAVING TUCKED FINS
42
Patent #:
10438955
Issue Dt:
10/08/2019
Application #:
15995896
Filing Dt:
06/01/2018
Publication #:
US20180286873
Pub Dt:
10/04/2018
Title:
DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS
43
Patent #:
10607947
Issue Dt:
03/31/2020
Application #:
15996960
Filing Dt:
06/04/2018
Publication #:
US20180286773
Pub Dt:
10/04/2018
Title:
SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL INCLUDING LONG VIA LINES
44
Patent #:
10784243
Issue Dt:
09/22/2020
Application #:
15997277
Filing Dt:
06/04/2018
Publication #:
US20190371776
Pub Dt:
12/05/2019
Title:
UNIPLANAR (SINGLE LAYER) PASSIVE CIRCUITRY
45
Patent #:
10520679
Issue Dt:
12/31/2019
Application #:
16000011
Filing Dt:
06/05/2018
Publication #:
US20190369339
Pub Dt:
12/05/2019
Title:
Fiber Alignment to Photonics Chip
46
Patent #:
10672710
Issue Dt:
06/02/2020
Application #:
16000174
Filing Dt:
06/05/2018
Publication #:
US20190371736
Pub Dt:
12/05/2019
Title:
INTERCONNECT STRUCTURES WITH REDUCED CAPACITANCE
47
Patent #:
10585219
Issue Dt:
03/10/2020
Application #:
16000249
Filing Dt:
06/05/2018
Publication #:
US20190369309
Pub Dt:
12/05/2019
Title:
GRATING COUPLERS WITH MULTIPLE CONFIGURATIONS
48
Patent #:
10396078
Issue Dt:
08/27/2019
Application #:
16002070
Filing Dt:
06/07/2018
Publication #:
US20180286863
Pub Dt:
10/04/2018
Title:
INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME
49
Patent #:
10658243
Issue Dt:
05/19/2020
Application #:
16002385
Filing Dt:
06/07/2018
Publication #:
US20190378761
Pub Dt:
12/12/2019
Title:
METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED STRUCTURES
50
Patent #:
10475693
Issue Dt:
11/12/2019
Application #:
16002403
Filing Dt:
06/07/2018
Title:
METHOD FOR FORMING SINGLE DIFFUSION BREAKS BETWEEN FINFET DEVICES AND THE RESULTING DEVICES
51
Patent #:
10432325
Issue Dt:
10/01/2019
Application #:
16002837
Filing Dt:
06/07/2018
Title:
TESTING PHASE NOISE IN OUTPUT SIGNAL OF DEVICE UNDER TEST USING TRANSFORMABLE FREQUENCY SIGNALS
52
Patent #:
10326002
Issue Dt:
06/18/2019
Application #:
16004935
Filing Dt:
06/11/2018
Title:
SELF-ALIGNED GATE CONTACT AND CROSS-COUPLING CONTACT FORMATION
53
Patent #:
10366930
Issue Dt:
07/30/2019
Application #:
16005064
Filing Dt:
06/11/2018
Title:
SELF-ALIGNED GATE CUT ISOLATION
54
Patent #:
10586736
Issue Dt:
03/10/2020
Application #:
16005073
Filing Dt:
06/11/2018
Publication #:
US20190378763
Pub Dt:
12/12/2019
Title:
HYBRID FIN CUT WITH IMPROVED FIN PROFILES
55
Patent #:
10374040
Issue Dt:
08/06/2019
Application #:
16005832
Filing Dt:
06/12/2018
Title:
METHOD TO FORM LOW RESISTANCE CONTACT
56
Patent #:
10181915
Issue Dt:
01/15/2019
Application #:
16006028
Filing Dt:
06/12/2018
Title:
PHASE MEASUREMENT FOR PHASED ARRAY DEVICES USING SHARED LOCAL OSCILLATOR AND SYNCHRONIZED DIGITIZER
57
Patent #:
11081398
Issue Dt:
08/03/2021
Application #:
16007023
Filing Dt:
06/13/2018
Publication #:
US20200258789
Pub Dt:
08/13/2020
Title:
METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE
58
Patent #:
10276391
Issue Dt:
04/30/2019
Application #:
16007127
Filing Dt:
06/13/2018
Title:
SELF-ALIGNED GATE CAPS WITH AN INVERTED PROFILE
59
Patent #:
10468104
Issue Dt:
11/05/2019
Application #:
16007445
Filing Dt:
06/13/2018
Title:
ROBUST AND ERROR FREE PHYSICAL UNCLONABLE FUNCTION USING TWIN-CELL CHARGE TRAP TRANSISTOR MEMORY
60
Patent #:
10446654
Issue Dt:
10/15/2019
Application #:
16008711
Filing Dt:
06/14/2018
Title:
GATE CONTACT STRUCTURES AND SELF-ALIGNED CONTACT PROCESS
61
Patent #:
10269735
Issue Dt:
04/23/2019
Application #:
16009329
Filing Dt:
06/15/2018
Title:
IC STRUCTURE WITH ADJUSTABLE INDUCTANCE AND CAPACITANCE AND RELATED METHOD
62
Patent #:
10355101
Issue Dt:
07/16/2019
Application #:
16009331
Filing Dt:
06/15/2018
Publication #:
US20190051733
Pub Dt:
02/14/2019
Title:
VERTICAL FIELD EFFECT TRANSISTOR (VFET) HAVING A SELF-ALIGNED GATE/GATE EXTENSION STRUCTURE AND METHOD
63
Patent #:
10580857
Issue Dt:
03/03/2020
Application #:
16010694
Filing Dt:
06/18/2018
Publication #:
US20190386100
Pub Dt:
12/19/2019
Title:
NOVEL METHOD TO FORM HIGH PERFORMANCE FIN PROFILE FOR 12LP AND ABOVE
64
Patent #:
10468083
Issue Dt:
11/05/2019
Application #:
16010841
Filing Dt:
06/18/2018
Title:
INTEGRATED CIRCUITS WITH LOOK UP TABLES, AND METHODS OF PRODUCING AND OPERATING THE SAME
65
Patent #:
10312356
Issue Dt:
06/04/2019
Application #:
16013363
Filing Dt:
06/20/2018
Title:
HETEROJUNCTION BIPOLAR TRANSISTORS WITH MULTIPLE EMITTER FINGERS AND UNDERCUT EXTRINSIC BASE REGIONS
66
Patent #:
10691865
Issue Dt:
06/23/2020
Application #:
16013403
Filing Dt:
06/20/2018
Publication #:
US20190392110
Pub Dt:
12/26/2019
Title:
MODIFYING LAYOUT BY REMOVING FILL CELL FROM FILL-DENSE REGIONS AND INSERTING DUPLICATE IN TARGET FILL REGION
67
Patent #:
10522644
Issue Dt:
12/31/2019
Application #:
16014076
Filing Dt:
06/21/2018
Publication #:
US20190393321
Pub Dt:
12/26/2019
Title:
DIFFERENT UPPER AND LOWER SPACERS FOR CONTACT
68
Patent #:
10796056
Issue Dt:
10/06/2020
Application #:
16014287
Filing Dt:
06/21/2018
Publication #:
US20190392106
Pub Dt:
12/26/2019
Title:
OPTIMIZING LIBRARY CELLS WITH WIRING IN METALLIZATION LAYERS
69
Patent #:
10483154
Issue Dt:
11/19/2019
Application #:
16015351
Filing Dt:
06/22/2018
Title:
FRONT-END-OF-LINE DEVICE STRUCTURE AND METHOD OF FORMING SUCH A FRONT-END-OF-LINE DEVICE STRUCTURE
70
Patent #:
10546853
Issue Dt:
01/28/2020
Application #:
16016058
Filing Dt:
06/22/2018
Publication #:
US20190393212
Pub Dt:
12/26/2019
Title:
METAL RESISTORS INTEGRATED INTO POLY-OPEN-CHEMICAL-MECHANICAL-POLISHING (POC) MODULE AND METHOD OF PRODUCTION THEREOF
71
Patent #:
10535771
Issue Dt:
01/14/2020
Application #:
16016828
Filing Dt:
06/25/2018
Publication #:
US20190393335
Pub Dt:
12/26/2019
Title:
METHOD FOR FORMING REPLACEMENT AIR GAP
72
Patent #:
10714376
Issue Dt:
07/14/2020
Application #:
16016910
Filing Dt:
06/25/2018
Publication #:
US20190393077
Pub Dt:
12/26/2019
Title:
METHOD OF FORMING SEMICONDUCTOR MATERIAL IN TRENCHES HAVING DIFFERENT WIDTHS, AND RELATED STRUCTURES
73
Patent #:
NONE
Issue Dt:
Application #:
16018304
Filing Dt:
06/26/2018
Publication #:
US20190043956
Pub Dt:
02/07/2019
Title:
LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON
74
Patent #:
10541236
Issue Dt:
01/21/2020
Application #:
16018549
Filing Dt:
06/26/2018
Publication #:
US20190393209
Pub Dt:
12/26/2019
Title:
ELECTROSTATIC DISCHARGE DEVICES WITH REDUCED CAPACITANCE
75
Patent #:
10559686
Issue Dt:
02/11/2020
Application #:
16018970
Filing Dt:
06/26/2018
Publication #:
US20190393342
Pub Dt:
12/26/2019
Title:
METHODS OF FORMING GATE CONTACT OVER ACTIVE REGION FOR VERTICAL FINFET, AND STRUCTURES FORMED THEREBY
76
Patent #:
10453754
Issue Dt:
10/22/2019
Application #:
16021660
Filing Dt:
06/28/2018
Title:
DIFFUSED CONTACT EXTENSION DOPANTS IN A TRANSISTOR DEVICE
77
Patent #:
10782606
Issue Dt:
09/22/2020
Application #:
16022752
Filing Dt:
06/29/2018
Publication #:
US20200004155
Pub Dt:
01/02/2020
Title:
PHOTOLITHOGRAPHY METHODS AND STRUCTURES THAT REDUCE STOCHASTIC DEFECTS
78
Patent #:
NONE
Issue Dt:
Application #:
16023470
Filing Dt:
06/29/2018
Publication #:
US20200002813
Pub Dt:
01/02/2020
Title:
ISOLATED DEPOSITION ZONES FOR ATOMIC LAYER DEPOSITION
79
Patent #:
10818557
Issue Dt:
10/27/2020
Application #:
16026130
Filing Dt:
07/03/2018
Publication #:
US20200013678
Pub Dt:
01/09/2020
Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
FIN CUT LAST METHOD FOR FORMING A VERTICAL FINFET DEVICE
Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
10/22/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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