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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 79 of 85
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Patent #:	10629739	Issue Dt:	04/21/2020	Application #:	16038384	Filing Dt:	07/18/2018
Publication #:	US20200027979	Pub Dt:	01/23/2020
Title:	METHODS OF FORMING SPACERS ADJACENT GATE STRUCTURES OF A TRANSISTOR DEVICE

Patent #:	10297506	Issue Dt:	05/21/2019	Application #:	16038426	Filing Dt:	07/18/2018
Publication #:	US20180323110	Pub Dt:	11/08/2018
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	10373946	Issue Dt:	08/06/2019	Application #:	16038532	Filing Dt:	07/18/2018
Publication #:	US20180323185	Pub Dt:	11/08/2018
Title:	DIODE-TRIGGERED SCHOTTKY SILICON-CONTROLLED RECTIFIER FOR FIN-FET ELECTROSTATIC DISCHARGE CONTROL

Patent #:	10436982	Issue Dt:	10/08/2019	Application #:	16038868	Filing Dt:	07/18/2018
Title:	WAVEGUIDE BENDS WITH FIELD CONFINEMENT

Patent #:	10354928	Issue Dt:	07/16/2019	Application #:	16038977	Filing Dt:	07/18/2018
Publication #:	US20180323113	Pub Dt:	11/08/2018
Title:	INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL

Patent #:	10535606	Issue Dt:	01/14/2020	Application #:	16040752	Filing Dt:	07/20/2018
Publication #:	US20180331040	Pub Dt:	11/15/2018
Title:	DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD

Patent #:	10746921	Issue Dt:	08/18/2020	Application #:	16040896	Filing Dt:	07/20/2018
Publication #:	US20200026000	Pub Dt:	01/23/2020
Title:	STACKED WAVEGUIDE ARRANGEMENTS PROVIDING FIELD CONFINEMENT

Patent #:	11101348	Issue Dt:	08/24/2021	Application #:	16044544	Filing Dt:	07/25/2018
Publication #:	US20200035786	Pub Dt:	01/30/2020
Title:	NANOSHEET FIELD EFFECT TRANSISTOR WITH SPACERS BETWEEN SHEETS

Patent #:	NONE	Issue Dt:		Application #:	16045111	Filing Dt:	07/25/2018
Publication #:	US20200035495	Pub Dt:	01/30/2020
Title:	CHEMICAL-MECHANICAL POLISHING WITH VARIABLE-PRESSURE POLISHING PADS

Patent #:	10593754	Issue Dt:	03/17/2020	Application #:	16045267	Filing Dt:	07/25/2018
Publication #:	US20200035785	Pub Dt:	01/30/2020
Title:	SOI DEVICE STRUCTURES WITH DOPED REGIONS PROVIDING CHARGE SINKING

Patent #:	10707218	Issue Dt:	07/07/2020	Application #:	16045920	Filing Dt:	07/26/2018
Publication #:	US20200035686	Pub Dt:	01/30/2020
Title:	TWO PORT SRAM CELL USING COMPLEMENTARY NANO-SHEET/WIRE TRANSISTOR DEVICES

Patent #:	10636876	Issue Dt:	04/28/2020	Application #:	16046241	Filing Dt:	07/26/2018
Publication #:	US20200035788	Pub Dt:	01/30/2020
Title:	DEVICES WITH CHANNEL EXTENSION REGIONS

Patent #:	10580897	Issue Dt:	03/03/2020	Application #:	16046368	Filing Dt:	07/26/2018
Publication #:	US20180374946	Pub Dt:	12/27/2018
Title:	METHODS OF FORMING A BULK FIELD EFFECT TRANSISTOR (FET) WITH SUB-SOURCE/DRAIN ISOLATION LAYERS AND THE RESULTING STRUCTURES

Patent #:	10553486	Issue Dt:	02/04/2020	Application #:	16047037	Filing Dt:	07/27/2018
Publication #:	US20200035555	Pub Dt:	01/30/2020
Title:	FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED METAL PLUGS AND METHODS

Patent #:	10510620	Issue Dt:	12/17/2019	Application #:	16047043	Filing Dt:	07/27/2018
Title:	WORK FUNCTION METAL PATTERNING FOR N-P SPACE BETWEEN ACTIVE NANOSTRUCTURES

Patent #:	10566248	Issue Dt:	02/18/2020	Application #:	16047044	Filing Dt:	07/27/2018
Publication #:	US20200035567	Pub Dt:	01/30/2020
Title:	WORK FUNCTION METAL PATTERNING FOR N-P SPACES BETWEEN ACTIVE NANOSTRUCTURES USING UNITARY ISOLATION PILLAR

Patent #:	10580685	Issue Dt:	03/03/2020	Application #:	16047078	Filing Dt:	07/27/2018
Publication #:	US20200035543	Pub Dt:	01/30/2020
Title:	INTEGRATED SINGLE DIFFUSION BREAK

Patent #:	10510622	Issue Dt:	12/17/2019	Application #:	16047456	Filing Dt:	07/27/2018
Title:	VERTICALLY STACKED COMPLEMENTARY-FET DEVICE WITH INDEPENDENT GATE CONTROL

Patent #:	10593593	Issue Dt:	03/17/2020	Application #:	16047470	Filing Dt:	07/27/2018
Publication #:	US20200035556	Pub Dt:	01/30/2020
Title:	METHODS, APPARATUS, AND SYSTEM FOR PROTECTING COBALT FORMATIONS FROM OXIDATION DURING SEMICONDUCTOR DEVICE FORMATION

Patent #:	10685705	Issue Dt:	06/16/2020	Application #:	16047529	Filing Dt:	07/27/2018
Publication #:	US20200035295	Pub Dt:	01/30/2020
Title:	PROGRAM AND ERASE MEMORY STRUCTURES

Patent #:	10510392	Issue Dt:	12/17/2019	Application #:	16047882	Filing Dt:	07/27/2018
Title:	INTEGRATED CIRCUITS HAVING MEMORY CELLS WITH SHARED BIT LINES AND SHARED SOURCE LINES

Patent #:	10553478	Issue Dt:	02/04/2020	Application #:	16049303	Filing Dt:	07/30/2018
Publication #:	US20180337126	Pub Dt:	11/22/2018
Title:	IC STRUCTURE WITH INTERFACE LINER AND METHODS OF FORMING SAME

Patent #:	10644157	Issue Dt:	05/05/2020	Application #:	16049849	Filing Dt:	07/31/2018
Publication #:	US20200044069	Pub Dt:	02/06/2020
Title:	FIN-TYPE FIELD EFFECT TRANSISTORS WITH UNIFORM CHANNEL LENGTHS AND BELOW-CHANNEL ISOLATION ON BULK SEMICONDUCTOR SUBSTRATES AND METHODS

Patent #:	10546775	Issue Dt:	01/28/2020	Application #:	16052085	Filing Dt:	08/01/2018
Publication #:	US20200043779	Pub Dt:	02/06/2020
Title:	FIELD-EFFECT TRANSISTORS WITH IMPROVED DIELECTRIC GAP FILL

Patent #:	10680065	Issue Dt:	06/09/2020	Application #:	16052140	Filing Dt:	08/01/2018
Publication #:	US20200044029	Pub Dt:	02/06/2020
Title:	FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL

Patent #:	10790363	Issue Dt:	09/29/2020	Application #:	16054033	Filing Dt:	08/03/2018
Publication #:	US20200044034	Pub Dt:	02/06/2020
Title:	IC STRUCTURE WITH METAL CAP ON COBALT LAYER AND METHODS OF FORMING SAME

Patent #:	10529831	Issue Dt:	01/07/2020	Application #:	16054881	Filing Dt:	08/03/2018
Title:	METHODS, APPARATUS, AND SYSTEM FOR FORMING EPITAXIAL FORMATIONS WITH REDUCED RISK OF MERGING

Patent #:	10741542	Issue Dt:	08/11/2020	Application #:	16055365	Filing Dt:	08/06/2018
Publication #:	US20180342501	Pub Dt:	11/29/2018
Title:	TRANSISTORS PATTERNED WITH ELECTROSTATIC DISCHARGE PROTECTION AND METHODS OF FABRICATION

Patent #:	10460782	Issue Dt:	10/29/2019	Application #:	16055952	Filing Dt:	08/06/2018
Title:	INTEGRATED CIRCUITS HAVING SINGLE STATE MEMORY REFERENCE CELLS AND METHODS FOR OPERATING THE SAME

Patent #:	10529724	Issue Dt:	01/07/2020	Application #:	16056660	Filing Dt:	08/07/2018
Publication #:	US20190027483	Pub Dt:	01/24/2019
Title:	METHOD OF MANUFACTURING A VERTICAL SRAM WITH CROSS-COUPLED CONTACTS PENETRATING THROUGH COMMON GATE STRUCTURES

Patent #:	10593782	Issue Dt:	03/17/2020	Application #:	16056934	Filing Dt:	08/07/2018
Publication #:	US20180374935	Pub Dt:	12/27/2018
Title:	SELF-ALIGNED FINFET FORMATION

Patent #:	10522217	Issue Dt:	12/31/2019	Application #:	16057857	Filing Dt:	08/08/2018
Title:	COLUMN-DEPENDENT POSITIVE VOLTAGE BOOST FOR MEMORY CELL SUPPLY VOLTAGE

Patent #:	10510749	Issue Dt:	12/17/2019	Application #:	16057881	Filing Dt:	08/08/2018
Title:	RESISTOR WITHIN SINGLE DIFFUSION BREAK, AND RELATED METHOD

Patent #:	10790198	Issue Dt:	09/29/2020	Application #:	16058494	Filing Dt:	08/08/2018
Publication #:	US20200051867	Pub Dt:	02/13/2020
Title:	FIN STRUCTURES

Patent #:	11002763	Issue Dt:	05/11/2021	Application #:	16100297	Filing Dt:	08/10/2018
Publication #:	US20200049737	Pub Dt:	02/13/2020
Title:	PROBE FOR PIC DIE WITH RELATED TEST ASSEMBLY AND METHOD

Patent #:	10529826	Issue Dt:	01/07/2020	Application #:	16101876	Filing Dt:	08/13/2018
Title:	FORMING SELF-ALIGNED GATE AND SOURCE/DRAIN CONTACTS USING SACRIFICIAL GATE CAP SPACER AND RESULTING DEVICES

Patent #:	10832967	Issue Dt:	11/10/2020	Application #:	16101963	Filing Dt:	08/13/2018
Publication #:	US20200051868	Pub Dt:	02/13/2020
Title:	TAPERED FIN-TYPE FIELD-EFFECT TRANSISTORS

Patent #:	10559593	Issue Dt:	02/11/2020	Application #:	16102066	Filing Dt:	08/13/2018
Publication #:	US20200051808	Pub Dt:	02/13/2020
Title:	FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL

Patent #:	10665667	Issue Dt:	05/26/2020	Application #:	16103357	Filing Dt:	08/14/2018
Publication #:	US20200058734	Pub Dt:	02/20/2020
Title:	JUNCTIONLESS/ACCUMULATION MODE TRANSISTOR WITH DYNAMIC CONTROL

Patent #:	11233006	Issue Dt:	01/25/2022	Application #:	16103372	Filing Dt:	08/14/2018
Publication #:	US20190006232	Pub Dt:	01/03/2019
Title:	METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS

Patent #:	10790376	Issue Dt:	09/29/2020	Application #:	16105102	Filing Dt:	08/20/2018
Publication #:	US20200058757	Pub Dt:	02/20/2020
Title:	CONTACT STRUCTURES

Patent #:	10497576	Issue Dt:	12/03/2019	Application #:	16105388	Filing Dt:	08/20/2018
Title:	DEVICES WITH SLOTTED ACTIVE REGIONS

Patent #:	11011303	Issue Dt:	05/18/2021	Application #:	16106162	Filing Dt:	08/21/2018
Publication #:	US20200066438	Pub Dt:	02/27/2020
Title:	DUMMY FILL WITH EDDY CURRENT SELF-CANCELING ELEMENT FOR INDUCTOR COMPONENT

Patent #:	10395941	Issue Dt:	08/27/2019	Application #:	16106174	Filing Dt:	08/21/2018
Title:	SADP METHOD WITH MANDREL UNDERCUT SPACER PORTION FOR MANDREL SPACE DIMENSION CONTROL

Patent #:	10636759	Issue Dt:	04/28/2020	Application #:	16106239	Filing Dt:	08/21/2018
Publication #:	US20200066667	Pub Dt:	02/27/2020
Title:	METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

Patent #:	10580696	Issue Dt:	03/03/2020	Application #:	16106246	Filing Dt:	08/21/2018
Publication #:	US20200066585	Pub Dt:	02/27/2020
Title:	INTERCONNECTS FORMED BY A METAL DISPLACEMENT REACTION

Patent #:	10818792	Issue Dt:	10/27/2020	Application #:	16106291	Filing Dt:	08/21/2018
Publication #:	US20200066894	Pub Dt:	02/27/2020
Title:	NANOSHEET FIELD-EFFECT TRANSISTORS FORMED WITH SACRIFICIAL SPACERS

Patent #:	10777668	Issue Dt:	09/15/2020	Application #:	16106344	Filing Dt:	08/21/2018
Publication #:	US20200066885	Pub Dt:	02/27/2020
Title:	BIPOLAR JUNCTION TRANSISTORS WITH A SELF-ALIGNED EMITTER AND BASE

Patent #:	10559490	Issue Dt:	02/11/2020	Application #:	16107563	Filing Dt:	08/21/2018
Publication #:	US20200066573	Pub Dt:	02/27/2020
Title:	DUAL-DEPTH STI CAVITY EXTENSION AND METHOD OF PRODUCTION THEREOF

Patent #:	10553707	Issue Dt:	02/04/2020	Application #:	16108152	Filing Dt:	08/22/2018
Publication #:	US20200066883	Pub Dt:	02/27/2020
Title:	FINFETS HAVING GATES PARALLEL TO FINS

Patent #:	10636893	Issue Dt:	04/28/2020	Application #:	16108753	Filing Dt:	08/22/2018
Publication #:	US20200066879	Pub Dt:	02/27/2020
Title:	REPLACEMENT METAL GATE WITH REDUCED SHORTING AND UNIFORM CHAMFERING

Patent #:	10886178	Issue Dt:	01/05/2021	Application #:	16109258	Filing Dt:	08/22/2018
Publication #:	US20200066593	Pub Dt:	02/27/2020
Title:	DEVICE WITH HIGHLY ACTIVE ACCEPTOR DOPING AND METHOD OF PRODUCTION THEREOF

Patent #:	10770412	Issue Dt:	09/08/2020	Application #:	16109867	Filing Dt:	08/23/2018
Publication #:	US20200066656	Pub Dt:	02/27/2020
Title:	GUARD RING FOR PHOTONIC INTEGRATED CIRCUIT DIE

Patent #:	10727120	Issue Dt:	07/28/2020	Application #:	16111193	Filing Dt:	08/23/2018
Publication #:	US20200066586	Pub Dt:	02/27/2020
Title:	CONTROLLING BACK-END-OF-LINE DIMENSIONS OF SEMICONDUCTOR DEVICES

Patent #:	10418365	Issue Dt:	09/17/2019	Application #:	16111263	Filing Dt:	08/24/2018
Publication #:	US20190035791	Pub Dt:	01/31/2019
Title:	MEMORY ARRAY WITH BURIED BITLINES BELOW VERTICAL FIELD EFFECT TRANSISTORS OF MEMORY CELLS AND A METHOD OF FORMING THE MEMORY ARRAY

Patent #:	10685881	Issue Dt:	06/16/2020	Application #:	16112511	Filing Dt:	08/24/2018
Publication #:	US20200066588	Pub Dt:	02/27/2020
Title:	METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF CONTACTS IN A SEMICONDUCTOR DEVICE

Patent #:	10269811	Issue Dt:	04/23/2019	Application #:	16114596	Filing Dt:	08/28/2018
Publication #:	US20180366470	Pub Dt:	12/20/2018
Title:	SELECTIVE SAC CAPPING ON FIN FIELD EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS

Patent #:	10629516	Issue Dt:	04/21/2020	Application #:	16114600	Filing Dt:	08/28/2018
Publication #:	US20200075456	Pub Dt:	03/05/2020
Title:	HYBRID DUAL DAMASCENE STRUCTURES WITH ENLARGED CONTACTS

Patent #:	10580745	Issue Dt:	03/03/2020	Application #:	16118791	Filing Dt:	08/31/2018
Publication #:	US20200075513	Pub Dt:	03/05/2020
Title:	WAFER LEVEL PACKAGING WITH INTEGRATED ANTENNA STRUCTURES

Patent #:	10522654	Issue Dt:	12/31/2019	Application #:	16120870	Filing Dt:	09/04/2018
Publication #:	US20180374932	Pub Dt:	12/27/2018
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	10741656	Issue Dt:	08/11/2020	Application #:	16121014	Filing Dt:	09/04/2018
Publication #:	US20200075738	Pub Dt:	03/05/2020
Title:	WRAPAROUND CONTACT SURROUNDING SOURCE/DRAIN REGIONS OF INTEGRATED CIRCUIT STRUCTURES AND METHOD OF FORMING SAME

Patent #:	10950692	Issue Dt:	03/16/2021	Application #:	16121058	Filing Dt:	09/04/2018
Publication #:	US20200075715	Pub Dt:	03/05/2020
Title:	METHODS OF FORMING AIR GAPS BETWEEN SOURCE/DRAIN CONTACTS AND THE RESULTING DEVICES

Patent #:	10629532	Issue Dt:	04/21/2020	Application #:	16122259	Filing Dt:	09/05/2018
Publication #:	US20190006280	Pub Dt:	01/03/2019
Title:	INTEGRATED CIRCUIT STRUCTURE HAVING GATE CONTACT AND METHOD OF FORMING SAME

Patent #:	10382049	Issue Dt:	08/13/2019	Application #:	16122993	Filing Dt:	09/06/2018
Title:	ON-CHIP CALIBRATION CIRCUIT AND METHOD WITH HALF-STEP RESOLUTION

Patent #:	10658176	Issue Dt:	05/19/2020	Application #:	16123042	Filing Dt:	09/06/2018
Publication #:	US20200083040	Pub Dt:	03/12/2020
Title:	METHODS OF MITIGATING COBALT DIFFUSION IN CONTACT STRUCTURES AND THE RESULTING DEVICES

Patent #:	10692991	Issue Dt:	06/23/2020	Application #:	16123160	Filing Dt:	09/06/2018
Publication #:	US20200083352	Pub Dt:	03/12/2020
Title:	GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH AIR-GAP INNER SPACERS AND METHODS

Patent #:	10643891	Issue Dt:	05/05/2020	Application #:	16124786	Filing Dt:	09/07/2018
Publication #:	US20200083099	Pub Dt:	03/12/2020
Title:	VIA STRUCTURES AND VIA PATTERNING USING OBLIQUE ANGLE DEPOSITION PROCESSES

Patent #:	10818494	Issue Dt:	10/27/2020	Application #:	16125066	Filing Dt:	09/07/2018
Publication #:	US20200083043	Pub Dt:	03/12/2020
Title:	METAL ON METAL MULTIPLE PATTERNING

Patent #:	10573753	Issue Dt:	02/25/2020	Application #:	16126775	Filing Dt:	09/10/2018
Publication #:	US20200083363	Pub Dt:	03/12/2020
Title:	OXIDE SPACER IN A CONTACT OVER ACTIVE GATE FINFET AND METHOD OF PRODUCTION THEREOF

Patent #:	10325848	Issue Dt:	06/18/2019	Application #:	16127645	Filing Dt:	09/11/2018
Publication #:	US20190013268	Pub Dt:	01/10/2019
Title:	SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY

Patent #:	10593674	Issue Dt:	03/17/2020	Application #:	16129221	Filing Dt:	09/12/2018
Publication #:	US20200083223	Pub Dt:	03/12/2020
Title:	DEEP FENCE ISOLATION FOR LOGIC CELLS

Patent #:	10332897	Issue Dt:	06/25/2019	Application #:	16133176	Filing Dt:	09/17/2018
Publication #:	US20190019798	Pub Dt:	01/17/2019
Title:	METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS

Patent #:	10366931	Issue Dt:	07/30/2019	Application #:	16133850	Filing Dt:	09/18/2018
Publication #:	US20190019733	Pub Dt:	01/17/2019
Title:	NANOSHEET DEVICES WITH CMOS EPITAXY AND METHOD OF FORMING

Patent #:	10937786	Issue Dt:	03/02/2021	Application #:	16134173	Filing Dt:	09/18/2018
Publication #:	US20200091143	Pub Dt:	03/19/2020
Title:	GATE CUT STRUCTURES

Patent #:	10816725	Issue Dt:	10/27/2020	Application #:	16134295	Filing Dt:	09/18/2018
Publication #:	US20200088942	Pub Dt:	03/19/2020
Title:	WAVEGUIDE INTERSECTIONS INCORPORATING A WAVEGUIDE CROSSING

Patent #:	10431499	Issue Dt:	10/01/2019	Application #:	16134650	Filing Dt:	09/18/2018
Publication #:	US20190244865	Pub Dt:	08/08/2019
Title:	INSULATING GATE SEPARATION STRUCTURE

Patent #:	10727133	Issue Dt:	07/28/2020	Application #:	16134708	Filing Dt:	09/18/2018
Publication #:	US20200091005	Pub Dt:	03/19/2020
Title:	METHOD OF FORMING GATE STRUCTURE WITH UNDERCUT REGION AND RESULTING DEVICE

Patent #:	10741685	Issue Dt:	08/11/2020	Application #:	16137739	Filing Dt:	09/21/2018
Publication #:	US20200098909	Pub Dt:	03/26/2020
Title:	SEMICONDUCTOR DEVICES HAVING A FIN CHANNEL ARRANGED BETWEEN SOURCE AND DRIFT REGIONS AND METHODS OF MANUFACTURING THE SAME

Patent #:	10770585	Issue Dt:	09/08/2020	Application #:	16139917	Filing Dt:	09/24/2018
Publication #:	US20200098913	Pub Dt:	03/26/2020
Title:	SELF-ALIGNED BURIED CONTACT FOR VERTICAL FIELD-EFFECT TRANSISTOR AND METHOD OF PRODUCTION THEREOF

Patent #:	10468082	Issue Dt:	11/05/2019	Application #:	16140417	Filing Dt:	09/24/2018
Title:	MRAM SENSE AMPLIFIER HAVING A PRE-AMPLIFIER WITH IMPROVED OUTPUT OFFSET CANCELLATION

Patent #:	10804199	Issue Dt:	10/13/2020	Application #:	16140545	Filing Dt:	09/25/2018
Publication #:	US20200098688	Pub Dt:	03/26/2020
Title:	SELF-ALIGNED CHAMFERLESS INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICES

Patent #:	11233191	Issue Dt:	01/25/2022	Application #:	16142432	Filing Dt:	09/26/2018
Publication #:	US20200098976	Pub Dt:	03/26/2020
Title:	INTEGRATED CIRCUITS WITH EMBEDDED MEMORY STRUCTURES AND METHODS FOR FABRICATING THE SAME

Patent #:	10825913	Issue Dt:	11/03/2020	Application #:	16144275	Filing Dt:	09/27/2018
Publication #:	US20200105905	Pub Dt:	04/02/2020
Title:	METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR FINFET DEVICES WITH REDUCED PARASITIC CAPACITANCE

Patent #:	10957578	Issue Dt:	03/23/2021	Application #:	16146413	Filing Dt:	09/28/2018
Publication #:	US20200105584	Pub Dt:	04/02/2020
Title:	SINGLE DIFFUSION BREAK DEVICE FOR FDSOI

Patent #:	10622463	Issue Dt:	04/14/2020	Application #:	16147072	Filing Dt:	09/28/2018
Publication #:	US20190043965	Pub Dt:	02/07/2019
Title:	METHOD, APPARATUS AND SYSTEM FOR IMPROVED PERFORMANCE USING TALL FINS IN FINFET DEVICES

Patent #:	10790276	Issue Dt:	09/29/2020	Application #:	16147303	Filing Dt:	09/28/2018
Publication #:	US20190035780	Pub Dt:	01/31/2019
Title:	METHODS, APPARATUS, AND SYSTEM FOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Patent #:	10529704	Issue Dt:	01/07/2020	Application #:	16148323	Filing Dt:	10/01/2018
Title:	AUXILIARY GATE ANTENNA DIODES

Patent #:	10714577	Issue Dt:	07/14/2020	Application #:	16149711	Filing Dt:	10/02/2018
Publication #:	US20200105886	Pub Dt:	04/02/2020
Title:	ETCH STOP LAYER FOR USE IN FORMING CONTACTS THAT EXTEND TO MULTIPLE DEPTHS

Patent #:	10937693	Issue Dt:	03/02/2021	Application #:	16150026	Filing Dt:	10/02/2018
Publication #:	US20200105597	Pub Dt:	04/02/2020
Title:	METHODS, APPARATUS AND SYSTEM FOR A LOCAL INTERCONNECT FEATURE OVER AN ACTIVE REGION IN A FINFET DEVICE

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Publication #:	US20200111713	Pub Dt:	04/09/2020
Title:	FINFET HAVING INSULATING LAYERS BETWEEN GATE AND SOURCE/DRAIN CONTACTS

Patent #:	10763328	Issue Dt:	09/01/2020	Application #:	16151938	Filing Dt:	10/04/2018
Publication #:	US20200111870	Pub Dt:	04/09/2020
Title:	EPITAXIAL SEMICONDUCTOR MATERIAL GROWN WITH ENHANCED LOCAL ISOTROPY

Patent #:	10756096	Issue Dt:	08/25/2020	Application #:	16152454	Filing Dt:	10/05/2018
Publication #:	US20200111798	Pub Dt:	04/09/2020
Title:	INTEGRATED CIRCUIT STRUCTURE WITH COMPLEMENTARY FIELD EFFECT TRANSISTOR AND BURIED METAL INTERCONNECT AND METHOD

Patent #:	10651046	Issue Dt:	05/12/2020	Application #:	16154237	Filing Dt:	10/08/2018
Publication #:	US20200111676	Pub Dt:	04/09/2020
Title:	MULTIPLE PATTERNING WITH LATE LITHOGRAPHICALLY-DEFINED MANDREL CUTS

Patent #:	11417525	Issue Dt:	08/16/2022	Application #:	16154284	Filing Dt:	10/08/2018
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Title:	MULTIPLE PATTERNING WITH MANDREL CUTS DEFINED BY BLOCK MASKS

Patent #:	10784119	Issue Dt:	09/22/2020	Application #:	16154306	Filing Dt:	10/08/2018
Publication #:	US20200111677	Pub Dt:	04/09/2020
Title:	MULTIPLE PATTERNING WITH LITHOGRAPHICALLY-DEFINED CUTS

Patent #:	10236292	Issue Dt:	03/19/2019	Application #:	16156082	Filing Dt:	10/10/2018
Title:	COMPLEMENTARY FETs WITH WRAP AROUND CONTACTS AND METHODS OF FORMING SAME

Patent #:	10629701	Issue Dt:	04/21/2020	Application #:	16156325	Filing Dt:	10/10/2018
Publication #:	US20200119163	Pub Dt:	04/16/2020
Title:	SELF-ALIGNED GATE CUT METHOD AND MULTILAYER GATE-CUT PILLAR STRUCTURE

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Publication #:	US20200116823	Pub Dt:	04/16/2020
Title:	APPARATUS AND METHOD FOR INTEGRATING SELF-TEST OSCILLATOR WITH INJECTION LOCKED BUFFER

Patent #:	10678287	Issue Dt:	06/09/2020	Application #:	16159831	Filing Dt:	10/15/2018
Publication #:	US20200117226	Pub Dt:	04/16/2020
Title:	POSITIVE AND NEGATIVE FULL-RANGE BACK-BIAS GENERATOR CIRCUIT STRUCTURE

100

Patent #:	10804398	Issue Dt:	10/13/2020	Application #:	16160701	Filing Dt:	10/15/2018
Publication #:	US20200119180	Pub Dt:	04/16/2020
Title:	METHOD OF FORMING WRAP-AROUND-CONTACT AND THE RESULTING DEVICE

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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