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Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 8 of 85
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Patent #:	6957419	Issue Dt:	10/18/2005	Application #:	10099849	Filing Dt:	03/15/2002
Publication #:	US20030177421	Pub Dt:	09/18/2003
Title:	FACILITATING THE USE OF ALIASES DURING THE DEBUGGING OF APPLICATIONS

Patent #:	6656836	Issue Dt:	12/02/2003	Application #:	10100395	Filing Dt:	03/18/2002
Title:	METHOD OF PERFORMING A TWO STAGE ANNEAL IN THE FORMATION OF AN ALLOY INTERCONNECT

Patent #:	6891227	Issue Dt:	05/10/2005	Application #:	10102365	Filing Dt:	03/20/2002
Publication #:	US20030178617	Pub Dt:	09/25/2003
Title:	SELF-ALIGNED NANOTUBE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME

Patent #:	6639302	Issue Dt:	10/28/2003	Application #:	10103602	Filing Dt:	03/20/2002
Publication #:	US20030178649	Pub Dt:	09/25/2003
Title:	STRESS REDUCTION IN FLIP-CHIP PBGA PACKAGING BY UTILIZING SEGMENTED CHIP CARRIERS

Patent #:	6780686	Issue Dt:	08/24/2004	Application #:	10104319	Filing Dt:	03/21/2002
Publication #:	US20030178678	Pub Dt:	09/25/2003
Title:	DOPING METHODS FOR FULLY-DEPLETED SOI STRUCTURES, AND DEVICE COMPRISING THE RESULTING DOPED REGIONS

Patent #:	6919236	Issue Dt:	07/19/2005	Application #:	10104939	Filing Dt:	03/21/2002
Publication #:	US20030178622	Pub Dt:	09/25/2003
Title:	BIASED, TRIPLE-WELL FULLY DEPLETED SOI STRUCTURE, AND VARIOUS METHODS OF MAKING AND OPERATING SAME

Patent #:	6583016	Issue Dt:	06/24/2003	Application #:	10105522	Filing Dt:	03/26/2002
Title:	DOPED SPACER LINER FOR IMPROVED TRANSISTOR PERFORMANCE

Patent #:	7292593	Issue Dt:	11/06/2007	Application #:	10107151	Filing Dt:	03/28/2002
Title:	ARRANGEMENT IN A CHANNEL ADAPTER FOR SEGREGATING TRANSMIT PACKET DATA IN TRANSMIT BUFFERS BASED ON RESPECTIVE VIRTUAL LANES

Patent #:	6589408	Issue Dt:	07/08/2003	Application #:	10107778	Filing Dt:	03/27/2002
Title:	NON-PLANAR COPPER ALLOY TARGET FOR PLASMA VAPOR DEPOSITION SYSTEMS

Patent #:	7493498	Issue Dt:	02/17/2009	Application #:	10107784	Filing Dt:	03/27/2002
Title:	INPUT/OUTPUT PERMISSION BITMAPS FOR COMPARTMENTALIZED SECURITY

Patent #:	7280484	Issue Dt:	10/09/2007	Application #:	10108157	Filing Dt:	03/26/2002
Title:	NETWORK STATE DIAGNOSTICS FOR A HOME PHONELINE NETWORKING ALLIANCE MEDIA ACCESS CONTROLLER (HPNA MAC)

Patent #:	8135962	Issue Dt:	03/13/2012	Application #:	10108253	Filing Dt:	03/27/2002
Publication #:	US20030188178	Pub Dt:	10/02/2003
Title:	SYSTEM AND METHOD PROVIDING REGION-GRANULAR, HARDWARE-CONTROLLED MEMORY ENCRYPTION

Patent #:	6577476	Issue Dt:	06/10/2003	Application #:	10108688	Filing Dt:	03/28/2002
Title:	FLUX GUIDE STRUCTURE FOR A SPIN VALVE TRANSISTOR WHICH INCLUDES A SLIDER BODY SEMICONDUCTOR LAYERS

Patent #:	6737332	Issue Dt:	05/18/2004	Application #:	10109096	Filing Dt:	03/28/2002
Title:	SEMICONDUCTOR DEVICE FORMED OVER A MULTIPLE THICKNESS BURIED OXIDE LAYER, AND METHODS OF MAKING SAME

Patent #:	6664187	Issue Dt:	12/16/2003	Application #:	10114462	Filing Dt:	04/03/2002
Title:	LASER THERMAL ANNEALING FOR CU SEEDLAYER ENHANCEMENT

Patent #:	6610550	Issue Dt:	08/26/2003	Application #:	10114782	Filing Dt:	04/03/2002
Title:	METHOD AND APPARATUS FOR CORRELATING ERROR MODEL WITH DEFECT DATA

Patent #:	6745086	Issue Dt:	06/01/2004	Application #:	10114785	Filing Dt:	04/03/2002
Title:	METHOD AND APPARATUS FOR DETERMINING CONTROL ACTIONS INCORPORATING DEFECTIVITY EFFECTS

Patent #:	6703269	Issue Dt:	03/09/2004	Application #:	10114829	Filing Dt:	04/02/2002
Publication #:	US20030186492	Pub Dt:	10/02/2003
Title:	METHOD TO FORM GATE CONDUCTOR STRUCTURES OF DUAL DOPED POLYSILICON

Patent #:	6593625	Issue Dt:	07/15/2003	Application #:	10115160	Filing Dt:	04/03/2002
Publication #:	US20020185686	Pub Dt:	12/12/2002
Title:	RELAXED SIGE LAYERS ON SI OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING

Patent #:	6723635	Issue Dt:	04/20/2004	Application #:	10115245	Filing Dt:	04/04/2002
Title:	PROTECTION OF LOW-K ILD DURING DAMASCENE PROCESSING WITH THIN LINER

Patent #:	6687561	Issue Dt:	02/03/2004	Application #:	10115432	Filing Dt:	04/03/2002
Title:	METHOD AND APPARATUS FOR DETERMINING A SAMPLING PLAN BASED ON DEFECTIVITY

Patent #:	6822838	Issue Dt:	11/23/2004	Application #:	10116017	Filing Dt:	04/02/2002
Publication #:	US20030184919	Pub Dt:	10/02/2003
Title:	DUAL MAGNETIC TUNNEL JUNCTION SENSOR WITH A LONGITUDINAL BIAS STACK

Patent #:	6864520	Issue Dt:	03/08/2005	Application #:	10116568	Filing Dt:	04/04/2002
Publication #:	US20030190791	Pub Dt:	10/09/2003
Title:	GERMANIUM FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME

Patent #:	6745377	Issue Dt:	06/01/2004	Application #:	10116584	Filing Dt:	04/04/2002
Publication #:	US20030192017	Pub Dt:	10/09/2003
Title:	APPARATUS AND METHOD FOR REPRESENTING GATED-CLOCK LATCHES FOR PHASE ABSTRACTION

Patent #:	6765227	Issue Dt:	07/20/2004	Application #:	10116791	Filing Dt:	04/04/2002
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) WAFER HAVING A SI/SIGE/SI ACTIVE LAYER AND METHOD OF FABRICATION USING WAFER BONDING

Patent #:	6646285	Issue Dt:	11/11/2003	Application #:	10117789	Filing Dt:	04/05/2002
Publication #:	US20030203168	Pub Dt:	10/30/2003
Title:	MOLECULAR ELECTRONIC DEVICE USING METAL-METAL BONDED COMPLEXES

Patent #:	6677646	Issue Dt:	01/13/2004	Application #:	10117959	Filing Dt:	04/05/2002
Publication #:	US20030189228	Pub Dt:	10/09/2003
Title:	METHOD AND STRUCTURE OF A DISPOSABLE REVERSED SPACER PROCESS FOR HIGH PERFORMANCE RECESSED CHANNEL CMOS

Patent #:	6703277	Issue Dt:	03/09/2004	Application #:	10118437	Filing Dt:	04/08/2002
Title:	REDUCING AGENT FOR HIGH-K GATE DIELECTRIC PARASITIC INTERFACIAL LAYER

Patent #:	7191371	Issue Dt:	03/13/2007	Application #:	10118751	Filing Dt:	04/09/2002
Publication #:	US20030189903	Pub Dt:	10/09/2003
Title:	SYSTEM AND METHOD FOR SEQUENTIAL TESTING OF HIGH SPEED SERIAL LINK CORE

Patent #:	6596384	Issue Dt:	07/22/2003	Application #:	10119458	Filing Dt:	04/09/2002
Title:	SELECTIVELY ROUGHENING CONDUCTORS FOR HIGH FREQUENCY PRINTED WIRING BOARDS

Patent #:	6580132	Issue Dt:	06/17/2003	Application #:	10119799	Filing Dt:	04/10/2002
Title:	DAMASCENE DOUBLE-GATE FET

Patent #:	6671867	Issue Dt:	12/30/2003	Application #:	10121877	Filing Dt:	04/11/2002
Publication #:	US20030196183	Pub Dt:	10/16/2003
Title:	ANALYTICAL CONSTRAINT GENERATION FOR CUT-BASED GLOBAL PLACEMENT

Patent #:	6815802	Issue Dt:	11/09/2004	Application #:	10122857	Filing Dt:	04/15/2002
Publication #:	US20020121676	Pub Dt:	09/05/2002
Title:	INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY

Patent #:	6682860	Issue Dt:	01/27/2004	Application #:	10122876	Filing Dt:	04/12/2002
Publication #:	US20030194568	Pub Dt:	10/16/2003
Title:	ATTENUATED EMBEDDED PHASE SHIFT PHOTOMASK BLANKS

Patent #:	6728123	Issue Dt:	04/27/2004	Application #:	10123493	Filing Dt:	04/15/2002
Publication #:	US20030193822	Pub Dt:	10/16/2003
Title:	REDUNDANT ARRAY ARCHITECTURE FOR WORD REPLACEMENT IN CAM

Patent #:	6518167	Issue Dt:	02/11/2003	Application #:	10123588	Filing Dt:	04/16/2002
Title:	METHOD OF FORMING A METAL OR METAL NITRIDE INTERFACE LAYER BETWEEN SILICON NITRIDE AND COPPER

Patent #:	6730454	Issue Dt:	05/04/2004	Application #:	10124087	Filing Dt:	04/16/2002
Publication #:	US20030198877	Pub Dt:	10/23/2003
Title:	ANTIREFLECTIVE SIO-CONTAINING COMPOSITIONS FOR HARDMASK LAYER

Patent #:	6724096	Issue Dt:	04/20/2004	Application #:	10124216	Filing Dt:	04/16/2002
Publication #:	US20020185753	Pub Dt:	12/12/2002
Title:	DIE CORNER ALIGNMENT STRUCTURE

Patent #:	6710258	Issue Dt:	03/23/2004	Application #:	10125624	Filing Dt:	04/18/2002
Publication #:	US20020180004	Pub Dt:	12/05/2002
Title:	CIRCUITIZED SUBSTRATE FOR HIGH-FREQUENCY APPLICATIONS

Patent #:	6783717	Issue Dt:	08/31/2004	Application #:	10127373	Filing Dt:	04/22/2002
Publication #:	US20030197312	Pub Dt:	10/23/2003
Title:	PROCESS OF FABRICATING A PRECISION MICROCONTACT PRINTING STAMP

Patent #:	6656308	Issue Dt:	12/02/2003	Application #:	10127374	Filing Dt:	04/22/2002
Publication #:	US20030196748	Pub Dt:	10/23/2003
Title:	PROCESS OF FABRICATING A PRECISION MICROCONTACT PRINTING STAMP

Patent #:	6518185	Issue Dt:	02/11/2003	Application #:	10127521	Filing Dt:	04/22/2002
Title:	INTEGRATION SCHEME FOR NON-FEATURE-SIZE-DEPENDENT CU-ALLOY INTRODUCTION

Patent #:	6608352	Issue Dt:	08/19/2003	Application #:	10131904	Filing Dt:	04/25/2002
Title:	DETERMINATION OF THERMAL RESISTANCE FOR FIELD EFFECT TRANSISTOR FORMED IN SOI TECHNOLOGY

Patent #:	6787912	Issue Dt:	09/07/2004	Application #:	10132173	Filing Dt:	04/26/2002
Publication #:	US20030201537	Pub Dt:	10/30/2003
Title:	BARRIER MATERIAL FOR COPPER STRUCTURES

Patent #:	6664185	Issue Dt:	12/16/2003	Application #:	10132235	Filing Dt:	04/25/2002
Title:	SELF-ALIGNED BARRIER FORMED WITH AN ALLOY HAVING AT LEAST TWO DOPANT ELEMENTS FOR MINIMIZED RESISTANCE OF INTERCONNECT

Patent #:	6730617	Issue Dt:	05/04/2004	Application #:	10132530	Filing Dt:	04/24/2002
Publication #:	US20030203649	Pub Dt:	10/30/2003
Title:	METHOD OF FABRICATING ONE OR MORE TIERS OF AN INTEGRATED CIRCUIT

Patent #:	6633040	Issue Dt:	10/14/2003	Application #:	10132896	Filing Dt:	04/25/2002
Title:	SOLENOID ELECTRON BEAM LENSES WITH HIGH DEMAGNIFICATION AND LOW ABERRATIONS

Patent #:	6751518	Issue Dt:	06/15/2004	Application #:	10134244	Filing Dt:	04/29/2002
Title:	DYNAMIC PROCESS STATE ADJUSTMENT OF A PROCESSING TOOL TO REDUCE NON-UNIFORMITY

Patent #:	6528409	Issue Dt:	03/04/2003	Application #:	10134883	Filing Dt:	04/29/2002
Title:	INTERCONNECT STRUCTURE FORMED IN POROUS DIELECTRIC MATERIAL WITH MINIMIZED DEGRADATION AND ELECTROMIGRATION

Patent #:	6624476	Issue Dt:	09/23/2003	Application #:	10134973	Filing Dt:	04/29/2002
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE HAVING SELECTIVE DOPANT IMPLANT IN INSULATOR LAYER AND METHOD OF FABRICATING

Patent #:	6743666	Issue Dt:	06/01/2004	Application #:	10134981	Filing Dt:	04/29/2002
Title:	SELECTIVE THICKENING OF THE SOURCE-DRAIN AND GATE AREAS OF FIELD EFFECT TRANSISTORS

Patent #:	6674128	Issue Dt:	01/06/2004	Application #:	10135008	Filing Dt:	04/29/2002
Title:	SEMICONDUCTOR-ON-INSULATOR DEVICE WITH THERMOELECTRIC COOLER ON SURFACE

Patent #:	6639800	Issue Dt:	10/28/2003	Application #:	10135502	Filing Dt:	04/30/2002
Title:	HEAT SINK SUBASSEMBLY

Patent #:	6701206	Issue Dt:	03/02/2004	Application #:	10138712	Filing Dt:	05/03/2002
Title:	METHOD AND SYSTEM FOR CONTROLLING A PROCESS TOOL

Patent #:	6809955	Issue Dt:	10/26/2004	Application #:	10139746	Filing Dt:	05/07/2002
Publication #:	US20020163829	Pub Dt:	11/07/2002
Title:	ADDRESABLE AND ELECTRICALLY REVERSIBLE MEMORY SWITCH

Patent #:	6826740	Issue Dt:	11/30/2004	Application #:	10140517	Filing Dt:	05/07/2002
Publication #:	US20030212976	Pub Dt:	11/13/2003
Title:	AUTOMATED BUFFER INSERTION INCORPORATING CONGESTION RELIEF FOR USE IN CONNECTION WITH PHYSICAL DESIGN OF INTEGRATED CIRCUIT

Patent #:	6706566	Issue Dt:	03/16/2004	Application #:	10144402	Filing Dt:	05/13/2002
Publication #:	US20020173083	Pub Dt:	11/21/2002
Title:	METHODOLOGY FOR ELECTRICALLY INDUCED SELECTIVE BREAKDOWN OF NANOTUBES

Patent #:	6767584	Issue Dt:	07/27/2004	Application #:	10144510	Filing Dt:	05/13/2002
Publication #:	US20030211365	Pub Dt:	11/13/2003
Title:	DISK SUBSTRATE WITH MONOSIZED MICROBUMPS

Patent #:	6737725	Issue Dt:	05/18/2004	Application #:	10144574	Filing Dt:	05/13/2002
Publication #:	US20020127844	Pub Dt:	09/12/2002
Title:	MULTILEVEL INTERCONNECT STRUCTURE CONTAINING AIR GAPS AND METHOD FOR MAKING

Patent #:	6541321	Issue Dt:	04/01/2003	Application #:	10145519	Filing Dt:	05/14/2002
Title:	METHOD OF MAKING TRANSISTORS WITH GATE INSULATION LAYERS OF DIFFERING THICKNESS

Patent #:	6548361	Issue Dt:	04/15/2003	Application #:	10145915	Filing Dt:	05/15/2002
Title:	SOI MOSFET AND METHOD OF FABRICATION

Patent #:	6815340	Issue Dt:	11/09/2004	Application #:	10145928	Filing Dt:	05/15/2002
Title:	METHOD OF FORMING AN ELECTROLESS NUCLEATION LAYER ON A VIA BOTTOM

Patent #:	6642066	Issue Dt:	11/04/2003	Application #:	10145942	Filing Dt:	05/15/2002
Title:	INTEGRATED PROCESS FOR DEPOSITING LAYER OF HIGH-K DIELECTRIC WITH IN-SITU CONTROL OF K VALUE AND THICKNESS OF HIGH-K DIELECTRIC LAYER

Patent #:	6706614	Issue Dt:	03/16/2004	Application #:	10145953	Filing Dt:	05/15/2002
Title:	SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION

Patent #:	6784101	Issue Dt:	08/31/2004	Application #:	10146029	Filing Dt:	05/16/2002
Title:	FORMATION OF HIGH-K GATE DIELECTRIC LAYERS FOR MOS DEVICES FABRICATED ON STRAINED LATTICE SEMICONDUCTOR SUBSTRATES WITH MINIMIZED STRESS RELAXATION

Patent #:	6618281	Issue Dt:	09/09/2003	Application #:	10146154	Filing Dt:	05/15/2002
Title:	CONTENT ADDRESSABLE MEMORY (CAM) WITH ERROR CHECKING AND CORRECTION (ECC) CAPABILITY

Patent #:	6727539	Issue Dt:	04/27/2004	Application #:	10147150	Filing Dt:	05/16/2002
Publication #:	US20030003651	Pub Dt:	01/02/2003
Title:	EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT

Patent #:	6682992	Issue Dt:	01/27/2004	Application #:	10147270	Filing Dt:	05/15/2002
Publication #:	US20030216013	Pub Dt:	11/20/2003
Title:	METHOD OF CONTROLLING GRAIN SIZE IN A POLYSILICON LAYER AND IN SEMICONDUCTOR DEVICES HAVING POLYSILICONE STRUCTURES

Patent #:	6800494	Issue Dt:	10/05/2004	Application #:	10150320	Filing Dt:	05/17/2002
Title:	METHOD AND APPARATUS FOR CONTROLLING COPPER BARRIER/SEED DEPOSITION PROCESSES

Patent #:	7568228	Issue Dt:	07/28/2009	Application #:	10150783	Filing Dt:	05/17/2002
Publication #:	US20020194469	Pub Dt:	12/19/2002
Title:	INTRUSION DETECTION IN DATA PROCESSING SYSTEMS

Patent #:	6621114	Issue Dt:	09/16/2003	Application #:	10151269	Filing Dt:	05/20/2002
Title:	MOS TRANSISTORS WITH HIGH-K DIELECTRIC GATE INSULATOR FOR REDUCING REMOTE SCATTERING

Patent #:	6689671	Issue Dt:	02/10/2004	Application #:	10151946	Filing Dt:	05/22/2002
Title:	LOW TEMPERATURE SOLID-PHASE EPITAXY FABRICATION PROCESS FOR MOS DEVICES BUILT ON STRAINED SEMICONDUCTOR SUBSTRATE

Patent #:	6787376	Issue Dt:	09/07/2004	Application #:	10154274	Filing Dt:	05/22/2002
Title:	CREATING A PROCESS RECIPE BASED ON A DESIRED RESULT

Patent #:	6879512	Issue Dt:	04/12/2005	Application #:	10154796	Filing Dt:	05/24/2002
Publication #:	US20030218903	Pub Dt:	11/27/2003
Title:	NONVOLATILE MEMORY DEVICE UTILIZING SPIN-VALVE-TYPE DESIGNS AND CURRENT PULSES

Patent #:	6621165	Issue Dt:	09/16/2003	Application #:	10154871	Filing Dt:	05/23/2002
Title:	SEMICONDUCTOR DEVICE FABRICATED BY REDUCING CARBON, SULPHUR, AND OXYGEN IMPURITIES IN A CALCIUM-DOPED COPPER SURFACE

Patent #:	6653737	Issue Dt:	11/25/2003	Application #:	10159181	Filing Dt:	05/31/2002
Publication #:	US20020142581	Pub Dt:	10/03/2002
Title:	INTERCONNECTION STRUCTURE AND METHOD FOR FABRICATING SAME

Patent #:	6826733	Issue Dt:	11/30/2004	Application #:	10159921	Filing Dt:	05/30/2002
Publication #:	US20030226122	Pub Dt:	12/04/2003
Title:	PARAMETER VARIATION TOLERANT METHOD FOR CIRCUIT DESIGN OPTIMIZATION

Patent #:	6662347	Issue Dt:	12/09/2003	Application #:	10160300	Filing Dt:	05/30/2002
Publication #:	US20030097645	Pub Dt:	05/22/2003
Title:	ON-CHIP DIAGNOSTIC SYSTEM, INTEGRATED CIRCUIT AND METHOD

Patent #:	6652665	Issue Dt:	11/25/2003	Application #:	10160627	Filing Dt:	05/31/2002
Title:	METHOD OF REMOVING SILICONE POLYMER DEPOSITS FROM ELECTRONIC COMPONENTS

Patent #:	7451324	Issue Dt:	11/11/2008	Application #:	10161500	Filing Dt:	05/31/2002
Publication #:	US20030226022	Pub Dt:	12/04/2003
Title:	SECURE EXECUTION MODE EXCEPTIONS

Patent #:	6771087	Issue Dt:	08/03/2004	Application #:	10162421	Filing Dt:	06/04/2002
Title:	SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUIT MODULES

Patent #:	7197102	Issue Dt:	03/27/2007	Application #:	10163340	Filing Dt:	06/07/2002
Publication #:	US20030227989	Pub Dt:	12/11/2003
Title:	METHOD AND APPARATUS FOR CLOCK-AND-DATA RECOVERY USING A SECONDARY DELAY-LOCKED LOOP

Patent #:	6589858	Issue Dt:	07/08/2003	Application #:	10163534	Filing Dt:	06/07/2002
Title:	METAL GATE STACK WITH ETCH ENDPOINT TRACER LAYER

Patent #:	6657276	Issue Dt:	12/02/2003	Application #:	10163925	Filing Dt:	06/06/2002
Title:	SHALLOW TRENCH ISOLATION (STI) REGION WITH HIGH-K LINER AND METHOD OF FORMATION

Patent #:	6732007	Issue Dt:	05/04/2004	Application #:	10164133	Filing Dt:	06/05/2002
Title:	METHOD AND APPARATUS FOR IMPLEMENTING DYNAMIC QUALIFICATION RECIPES

Patent #:	6824932	Issue Dt:	11/30/2004	Application #:	10164242	Filing Dt:	06/05/2002
Publication #:	US20030228526	Pub Dt:	12/11/2003
Title:	SELF-ALIGNED ALTERNATING PHASE SHIFT MASK PATTERNING PROCESS

Patent #:	6809027	Issue Dt:	10/26/2004	Application #:	10165264	Filing Dt:	06/06/2002
Publication #:	US20030228752	Pub Dt:	12/11/2003
Title:	SELF-ALIGNED BORDERLESS CONTACTS

Patent #:	6789099	Issue Dt:	09/07/2004	Application #:	10167170	Filing Dt:	06/10/2002
Publication #:	US20040073592	Pub Dt:	04/15/2004
Title:	SENSE-AMP BASED ADDER WITH SOURCE FOLLOWER EVALUATION TREE

Patent #:	7129142	Issue Dt:	10/31/2006	Application #:	10167184	Filing Dt:	06/11/2002
Publication #:	US20030228722	Pub Dt:	12/11/2003
Title:	METHOD OF FORMING DOPED REGIONS IN THE BULK SUBSTRATE OF AN SOI SUBSTRATE TO CONTROL THE OPERATIONAL CHARACTERISTICS OF TRANSISTORS FORMED THEREABOVE, AND AN INTEGRATED CIRCUIT DEVICE COMPRISING SAME

Patent #:	6559017	Issue Dt:	05/06/2003	Application #:	10170909	Filing Dt:	06/13/2002
Title:	METHOD OF USING AMORPHOUS CARBON AS SPACER MATERIAL IN A DISPOSABLE SPACER PROCESS

Patent #:	6809043	Issue Dt:	10/26/2004	Application #:	10173611	Filing Dt:	06/19/2002
Title:	MULTI-STAGE, LOW DEPOSITION RATE PECVD OXIDE

Patent #:	6686232	Issue Dt:	02/03/2004	Application #:	10173717	Filing Dt:	06/19/2002
Title:	ULTRA LOW DEPOSITION RATE PECVD SILICON NITRIDE

Patent #:	6764908	Issue Dt:	07/20/2004	Application #:	10173770	Filing Dt:	06/19/2002
Title:	NARROW WIDTH CMOS DEVICES FABRICATED ON STRAINED LATTICE SEMICONDUCTOR SUBSTRATES WITH MAXIMIZED NMOS AND PMOS DRIVE CURRENTS

Patent #:	6833587	Issue Dt:	12/21/2004	Application #:	10174328	Filing Dt:	06/18/2002
Title:	HEAT REMOVAL IN SOI DEVICES USING A BURIED OXIDE LAYER/CONDUCTIVE LAYER COMBINATION

Patent #:	6764774	Issue Dt:	07/20/2004	Application #:	10174748	Filing Dt:	06/19/2002
Publication #:	US20030235710	Pub Dt:	12/25/2003
Title:	STRUCTURES WITH IMPROVED ADHESION TO SI AND C CONTAINING DIELECTRICS AND METHOD FOR PREPARING THE SAME

Patent #:	6667791	Issue Dt:	12/23/2003	Application #:	10177243	Filing Dt:	06/21/2002
Publication #:	US20020196402	Pub Dt:	12/26/2002
Title:	PASSIVE DRIVE MATRIX DISPLAY

Patent #:	6680240	Issue Dt:	01/20/2004	Application #:	10178542	Filing Dt:	06/25/2002
Publication #:	US20040018668	Pub Dt:	01/29/2004
Title:	SILICON-ON-INSULATOR DEVICE WITH STRAINED DEVICE FILM AND METHOD FOR MAKING THE SAME WITH PARTIAL REPLACEMENT OF ISOLATION OXIDE

Patent #:	7043679	Issue Dt:	05/09/2006	Application #:	10180207	Filing Dt:	06/27/2002
Title:	PIGGYBACKING OF ECC CORRECTIONS BEHIND LOADS

Patent #:	6799311	Issue Dt:	09/28/2004	Application #:	10183265	Filing Dt:	06/27/2002
Title:	BATCH/LOT ORGANIZATION BASED ON QUALITY CHARACTERISTICS

100

Patent #:	7158590	Issue Dt:	01/02/2007	Application #:	10184408	Filing Dt:	06/27/2002
Publication #:	US20030161417	Pub Dt:	08/28/2003
Title:	GAIN CONTROL IN WIRELESS LAN DEVICES

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

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