|
|
Patent #:
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|
Issue Dt:
|
06/08/2021
|
Application #:
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16436925
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Filing Dt:
|
06/11/2019
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Publication #:
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|
Pub Dt:
|
12/17/2020
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES OVER ACTIVE REGION AND METHODS OF FORMING THE STRUCTURES
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Patent #:
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|
Issue Dt:
|
05/18/2021
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Application #:
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16437440
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Filing Dt:
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06/11/2019
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Publication #:
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|
Pub Dt:
|
09/26/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN CONTACTS AND A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION
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Patent #:
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|
Issue Dt:
|
10/13/2020
|
Application #:
|
16438863
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Filing Dt:
|
06/12/2019
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Publication #:
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|
Pub Dt:
|
09/26/2019
| | | | |
Title:
|
INTEGRATED GRAPHENE DETECTORS WITH WAVEGUIDES
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Patent #:
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|
Issue Dt:
|
06/21/2022
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Application #:
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16439101
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Filing Dt:
|
06/12/2019
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Publication #:
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|
Pub Dt:
|
12/17/2020
| | | | |
Title:
|
VERTICAL MEMORY DEVICES
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|
Patent #:
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|
Issue Dt:
|
07/07/2020
|
Application #:
|
16440179
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Filing Dt:
|
06/13/2019
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Title:
|
ADAPTIVE NOISE CANCELLATION
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|
Patent #:
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|
Issue Dt:
|
10/27/2020
|
Application #:
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16441678
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Filing Dt:
|
06/14/2019
|
Title:
|
MULTIMODE WAVEGUIDE BENDS WITH FEATURES TO REDUCE BENDING LOSS
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|
Patent #:
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|
Issue Dt:
|
09/07/2021
|
Application #:
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16441726
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Filing Dt:
|
06/14/2019
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Publication #:
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Pub Dt:
|
12/05/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH REDUCED GATE HEIGHT BUDGET
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Patent #:
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|
Issue Dt:
|
07/21/2020
|
Application #:
|
16441755
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Filing Dt:
|
06/14/2019
|
Title:
|
WAVEGUIDE CROSSINGS WITH A NON-CONTACTING ARRANGEMENT
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|
Patent #:
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|
Issue Dt:
|
06/15/2021
|
Application #:
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16441911
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Filing Dt:
|
06/14/2019
|
Publication #:
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|
Pub Dt:
|
09/26/2019
| | | | |
Title:
|
SEMICONDUCTOR FABRICATION DESIGN RULE LOOPHOLE CHECKING FOR DESIGN FOR MANUFACTURABILITY OPTIMIZATION
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Patent #:
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|
Issue Dt:
|
11/17/2020
|
Application #:
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16443252
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Filing Dt:
|
06/17/2019
|
Title:
|
STRUCTURES AND SRAM BIT CELLS WITH A BURIED CROSS-COUPLE INTERCONNECT
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Patent #:
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|
Issue Dt:
|
03/02/2021
|
Application #:
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16446588
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Filing Dt:
|
06/19/2019
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Publication #:
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|
Pub Dt:
|
12/24/2020
| | | | |
Title:
|
DIFFUSION BREAK STRUCTURES IN SEMICONDUCTOR DEVICES
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|
Patent #:
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|
Issue Dt:
|
10/20/2020
|
Application #:
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16446906
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Filing Dt:
|
06/20/2019
|
Publication #:
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|
Pub Dt:
|
10/17/2019
| | | | |
Title:
|
HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS
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Patent #:
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Issue Dt:
|
06/15/2021
|
Application #:
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16447335
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Filing Dt:
|
06/20/2019
|
Publication #:
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|
Pub Dt:
|
10/03/2019
| | | | |
Title:
|
3D IC PACKAGE WITH RDL INTERPOSER AND RELATED METHOD
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|
Patent #:
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|
Issue Dt:
|
06/15/2021
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Application #:
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16448544
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Filing Dt:
|
06/21/2019
|
Publication #:
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|
Pub Dt:
|
10/17/2019
| | | | |
Title:
|
FIN-BASED DEVICES BASED ON THE THERMOELECTRIC EFFECT
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|
|
Patent #:
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|
Issue Dt:
|
04/20/2021
|
Application #:
|
16451797
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Filing Dt:
|
06/25/2019
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Publication #:
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|
Pub Dt:
|
12/31/2020
| | | | |
Title:
|
N-WELL RESISTOR
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|
Patent #:
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|
Issue Dt:
|
05/11/2021
|
Application #:
|
16454016
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Filing Dt:
|
06/26/2019
|
Publication #:
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|
Pub Dt:
|
12/31/2020
| | | | |
Title:
|
MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE
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|
|
Patent #:
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Issue Dt:
|
07/27/2021
|
Application #:
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16454238
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Filing Dt:
|
06/27/2019
|
Publication #:
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|
Pub Dt:
|
12/31/2020
| | | | |
Title:
|
LDMOS INTEGRATED CIRCUIT PRODUCT
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|
Patent #:
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|
Issue Dt:
|
04/12/2022
|
Application #:
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16454242
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Filing Dt:
|
06/27/2019
|
Publication #:
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|
Pub Dt:
|
12/31/2020
| | | | |
Title:
|
PROCESS CONTROL OF SEMICONDUCTOR FABRICATION BASED ON SPECTRA QUALITY METRICS
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|
Patent #:
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|
Issue Dt:
|
05/17/2022
|
Application #:
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16455071
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Filing Dt:
|
06/27/2019
|
Publication #:
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|
Pub Dt:
|
12/31/2020
| | | | |
Title:
|
DIODE TRIGGERED SILICON CONTROLLED RECTIFIER (SCR) WITH HYBRID DIODES
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|
|
Patent #:
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|
Issue Dt:
|
06/08/2021
|
Application #:
|
16456268
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Filing Dt:
|
06/28/2019
|
Publication #:
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|
Pub Dt:
|
12/31/2020
| | | | |
Title:
|
SILICIDED GATE STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
12/31/2019
|
Application #:
|
16458056
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Filing Dt:
|
06/29/2019
|
Publication #:
|
|
Pub Dt:
|
10/24/2019
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR STRINGER DEFECT REDUCTION IN A TRENCH CUT REGION OF A FINFET DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
04/06/2021
|
Application #:
|
16458178
|
Filing Dt:
|
06/30/2019
|
Publication #:
|
|
Pub Dt:
|
12/31/2020
| | | | |
Title:
|
EPITAXIAL STRUCTURES OF A SEMICONDUCTOR DEVICE HAVING A WIDE GATE PITCH
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|
|
Patent #:
|
|
Issue Dt:
|
10/20/2020
|
Application #:
|
16459678
|
Filing Dt:
|
07/02/2019
|
Title:
|
FIN-TYPE FIELD EFFECT TRANSISTOR WITH REDUCED FIN BULGE AND METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
08/04/2020
|
Application #:
|
16502163
|
Filing Dt:
|
07/03/2019
|
Title:
|
ANALOG-TO-DIGITAL INVERTER CIRCUIT STRUCTURE WITH FDSOI TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
04/20/2021
|
Application #:
|
16502266
|
Filing Dt:
|
07/03/2019
|
Publication #:
|
|
Pub Dt:
|
01/07/2021
| | | | |
Title:
|
INTEGRATED III-V DEVICE AND DRIVER DEVICE PACKAGES WITH IMPROVED HEAT REMOVAL AND METHODS FOR FABRICATING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
12/22/2020
|
Application #:
|
16502667
|
Filing Dt:
|
07/03/2019
|
Publication #:
|
|
Pub Dt:
|
01/07/2021
| | | | |
Title:
|
TRANSVERSE-ELECTRIC (TE) PASS POLARIZER
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|
Patent #:
|
|
Issue Dt:
|
08/02/2022
|
Application #:
|
16503982
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Filing Dt:
|
07/05/2019
|
Publication #:
|
|
Pub Dt:
|
01/07/2021
| | | | |
Title:
|
STACKED-GATE TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
04/27/2021
|
Application #:
|
16507642
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Filing Dt:
|
07/10/2019
|
Publication #:
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|
Pub Dt:
|
01/14/2021
| | | | |
Title:
|
NON-PLANAR WAVEGUIDE STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
08/17/2021
|
Application #:
|
16508815
|
Filing Dt:
|
07/11/2019
|
Publication #:
|
|
Pub Dt:
|
01/14/2021
| | | | |
Title:
|
MULTIPLE THRESHOLD VOLTAGE DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
08/25/2020
|
Application #:
|
16508816
|
Filing Dt:
|
07/11/2019
|
Title:
|
METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES ON AN IC PRODUCT
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|
|
Patent #:
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|
Issue Dt:
|
08/10/2021
|
Application #:
|
16508940
|
Filing Dt:
|
07/11/2019
|
Publication #:
|
|
Pub Dt:
|
01/14/2021
| | | | |
Title:
|
SENSING SCHEME FOR STT-MRAM USING LOW-BARRIER NANOMAGNETS
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|
Patent #:
|
|
Issue Dt:
|
08/24/2021
|
Application #:
|
16509947
|
Filing Dt:
|
07/12/2019
|
Publication #:
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|
Pub Dt:
|
10/31/2019
| | | | |
Title:
|
DUAL AIRGAP STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
11/17/2020
|
Application #:
|
16510966
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Filing Dt:
|
07/14/2019
|
Title:
|
SEMICONDUCTOR DEVICE WITH REDUCED PARASITIC CAPACITANCE
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|
Patent #:
|
|
Issue Dt:
|
03/30/2021
|
Application #:
|
16515638
|
Filing Dt:
|
07/18/2019
|
Publication #:
|
|
Pub Dt:
|
01/21/2021
| | | | |
Title:
|
METHODS OF FORMING SOURCE/DRAIN REGIONS OF A FINFET DEVICE AND THE RESULTING STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
02/16/2021
|
Application #:
|
16515779
|
Filing Dt:
|
07/18/2019
|
Publication #:
|
|
Pub Dt:
|
01/21/2021
| | | | |
Title:
|
GRATING COUPLERS WITH A SILICIDE MIRROR
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|
|
Patent #:
|
|
Issue Dt:
|
03/16/2021
|
Application #:
|
16515913
|
Filing Dt:
|
07/18/2019
|
Publication #:
|
|
Pub Dt:
|
01/21/2021
| | | | |
Title:
|
ASYMMETRIC GATE CUT ISOLATION FOR SRAM
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|
|
Patent #:
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|
Issue Dt:
|
10/27/2020
|
Application #:
|
16516623
|
Filing Dt:
|
07/19/2019
|
Title:
|
FIN-TYPE FIELD-EFFECT TRANSISTORS INCLUDING A TWO-DIMENSIONAL MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
10/27/2020
|
Application #:
|
16516658
|
Filing Dt:
|
07/19/2019
|
Title:
|
TUNABLE GRATING COUPLERS
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|
|
Patent #:
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|
Issue Dt:
|
07/06/2021
|
Application #:
|
16517827
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Filing Dt:
|
07/22/2019
|
Publication #:
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|
Pub Dt:
|
01/28/2021
| | | | |
Title:
|
FORMING INTERCONNECT WITHOUT GATE CUT ISOLATION BLOCKING OPENING FORMATION
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|
|
Patent #:
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|
Issue Dt:
|
11/10/2020
|
Application #:
|
16519135
|
Filing Dt:
|
07/23/2019
|
Title:
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METAL RESISTOR STRUCTURE IN AT LEAST ONE CAVITY IN DIELECTRIC OVER TS CONTACT AND GATE STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
10/27/2020
|
Application #:
|
16520670
|
Filing Dt:
|
07/24/2019
|
Publication #:
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|
Pub Dt:
|
11/14/2019
| | | | |
Title:
|
POLY GATE EXTENSION SOURCE TO BODY CONTACT
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|
|
Patent #:
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|
Issue Dt:
|
02/15/2022
|
Application #:
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16522270
|
Filing Dt:
|
07/25/2019
|
Publication #:
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|
Pub Dt:
|
01/28/2021
| | | | |
Title:
|
ENERGY RECOVERY SYSTEM FOR A SEMICONDUCTOR FABRICATION FACILITY
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|
Patent #:
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|
Issue Dt:
|
12/06/2022
|
Application #:
|
16523340
|
Filing Dt:
|
07/26/2019
|
Publication #:
|
|
Pub Dt:
|
11/21/2019
| | | | |
Title:
|
IC PRODUCT COMPRISING AN INSULATING GATE SEPARATION STRUCTURE POSITIONED BETWEEN END SURFACES OF ADJACENT GATE STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
05/05/2020
|
Application #:
|
16524870
|
Filing Dt:
|
07/29/2019
|
Title:
|
OPTICAL BEAM STEERING WITH DIRECTIONALITY PROVIDED BY SWITCHED GRATING COUPLERS
|
|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
16525601
|
Filing Dt:
|
07/30/2019
|
Publication #:
|
|
Pub Dt:
|
11/21/2019
| | | | |
Title:
|
METHODS, APPARATUS, AND SYSTEM FOR A SEMICONDUCTOR DEVICE COMPRISING GATES WITH SHORT HEIGHTS
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|
|
Patent #:
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|
Issue Dt:
|
08/10/2021
|
Application #:
|
16525878
|
Filing Dt:
|
07/30/2019
|
Publication #:
|
|
Pub Dt:
|
02/04/2021
| | | | |
Title:
|
LASER WITH A GAIN MEDIUM LAYER DOPED WITH A RARE EARTH METAL WITH UPPER AND LOWER LIGHT-CONFINING FEATURES
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|
|
Patent #:
|
|
Issue Dt:
|
08/11/2020
|
Application #:
|
16526196
|
Filing Dt:
|
07/30/2019
|
Title:
|
SENSE AMPLIFIER REUSING SAME ELEMENTS FOR EVALUATING REFERENCE DEVICE AND MEMORY CELLS
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|
|
Patent #:
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|
Issue Dt:
|
09/21/2021
|
Application #:
|
16526529
|
Filing Dt:
|
07/30/2019
|
Publication #:
|
|
Pub Dt:
|
02/04/2021
| | | | |
Title:
|
HIGH VOLTAGE TRANSISTOR WITH FIN SOURCE/DRAIN REGIONS AND TRENCH GATE STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
03/17/2020
|
Application #:
|
16526778
|
Filing Dt:
|
07/30/2019
|
Title:
|
METHODS, APPARATUS, AND SYSTEM FOR HIGH-BANDWIDTH ON-MOLD ANTENNAS
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|
|
Patent #:
|
|
Issue Dt:
|
06/21/2022
|
Application #:
|
16527146
|
Filing Dt:
|
07/31/2019
|
Publication #:
|
|
Pub Dt:
|
02/04/2021
| | | | |
Title:
|
ENABLING OF FUNCTIONAL LOGIC IN IC USING THERMAL SEQUENCE ENABLING TEST
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|
|
Patent #:
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|
Issue Dt:
|
03/30/2021
|
Application #:
|
16529162
|
Filing Dt:
|
08/01/2019
|
Publication #:
|
|
Pub Dt:
|
11/21/2019
| | | | |
Title:
|
MULTI-STEP INSULATOR FORMATION IN TRENCHES TO AVOID SEAMS IN INSULATORS
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|
|
Patent #:
|
|
Issue Dt:
|
11/02/2021
|
Application #:
|
16531114
|
Filing Dt:
|
08/04/2019
|
Publication #:
|
|
Pub Dt:
|
02/04/2021
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES IN A WIDE GATE PITCH REGION OF SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
12/07/2021
|
Application #:
|
16531617
|
Filing Dt:
|
08/05/2019
|
Publication #:
|
|
Pub Dt:
|
11/28/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH NOVEL SPACER STRUCTURES HAVING NOVEL CONFIGURATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
08/03/2021
|
Application #:
|
16531819
|
Filing Dt:
|
08/05/2019
|
Publication #:
|
|
Pub Dt:
|
02/11/2021
| | | | |
Title:
|
WAVEGUIDE ABSORBERS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
16533835
|
Filing Dt:
|
08/07/2019
|
Publication #:
|
|
Pub Dt:
|
02/11/2021
| | | | |
Title:
|
STRUCTURE WITH COUNTER DOPING REGION BETWEEN N AND P WELLS UNDER GATE STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
01/26/2021
|
Application #:
|
16534317
|
Filing Dt:
|
08/07/2019
|
Publication #:
|
|
Pub Dt:
|
02/11/2021
| | | | |
Title:
|
GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH ROBUST INNER SPACERS AND METHODS
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|
|
Patent #:
|
|
Issue Dt:
|
11/02/2021
|
Application #:
|
16534361
|
Filing Dt:
|
08/07/2019
|
Publication #:
|
|
Pub Dt:
|
02/11/2021
| | | | |
Title:
|
FIN-TYPE FIELD-EFFECT TRANSISTORS OVER ONE OR MORE BURIED POLYCRYSTALLINE LAYERS
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|
|
Patent #:
|
|
Issue Dt:
|
07/26/2022
|
Application #:
|
16535338
|
Filing Dt:
|
08/08/2019
|
Publication #:
|
|
Pub Dt:
|
02/11/2021
| | | | |
Title:
|
TRANSISTOR DEVICE WITH A PLURALITY OF ACTIVE GATES THAT CAN BE INDIVIDUALLY MODULATED TO CHANGE PERFORMANCE CHARACTERISTICS OF THE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2020
|
Application #:
|
16537095
|
Filing Dt:
|
08/09/2019
|
Publication #:
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|
Pub Dt:
|
11/28/2019
| | | | |
Title:
|
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
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|
|
Patent #:
|
|
Issue Dt:
|
04/21/2020
|
Application #:
|
16538041
|
Filing Dt:
|
08/12/2019
|
Publication #:
|
|
Pub Dt:
|
01/09/2020
| | | | |
Title:
|
PRODUCT THAT INCLUDES A PLURALITY OF VERTICAL TRANSISTORS WITH A SHARED CONDUCTIVE GATE PLUG
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|
|
Patent #:
|
|
Issue Dt:
|
08/31/2021
|
Application #:
|
16538062
|
Filing Dt:
|
08/12/2019
|
Publication #:
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|
Pub Dt:
|
11/28/2019
| | | | |
Title:
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SEALED CAVITY STRUCTURES WITH A PLANAR SURFACE
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Patent #:
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Issue Dt:
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05/25/2021
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Application #:
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16538785
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Filing Dt:
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08/12/2019
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Publication #:
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Pub Dt:
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02/18/2021
| | | | |
Title:
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AIR GAP REGIONS OF A SEMICONDUCTOR DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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16540042
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Filing Dt:
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08/13/2019
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Publication #:
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Pub Dt:
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02/18/2021
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH REDUCED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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10/06/2020
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Application #:
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16540452
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Filing Dt:
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08/14/2019
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Title:
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BRAGG GRATINGS WITH AIRGAP CLADDING
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Patent #:
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Issue Dt:
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07/27/2021
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Application #:
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16541600
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Filing Dt:
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08/15/2019
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Publication #:
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Pub Dt:
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02/18/2021
| | | | |
Title:
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TRANSISTORS WITH SEPARATELY-FORMED SOURCE AND DRAIN
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Patent #:
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|
Issue Dt:
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05/11/2021
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Application #:
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16544074
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Filing Dt:
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08/19/2019
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Publication #:
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Pub Dt:
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02/25/2021
| | | | |
Title:
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PHOTODIODES INTEGRATED INTO A BICMOS PROCESS
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Patent #:
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|
Issue Dt:
|
02/02/2021
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Application #:
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16544866
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Filing Dt:
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08/19/2019
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Publication #:
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Pub Dt:
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02/25/2021
| | | | |
Title:
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SEMICONDUCTOR DETECTORS WITH BUTT-END COUPLED WAVEGUIDE AND METHOD OF FORMING THE SAME
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Patent #:
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|
Issue Dt:
|
03/09/2021
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Application #:
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16547474
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Filing Dt:
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08/21/2019
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Publication #:
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Pub Dt:
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02/25/2021
| | | | |
Title:
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ETCH STOP MEMBER IN BURIED INSULATOR OF SOI SUBSTRATE TO REDUCE CONTACT EDGE PUNCH THROUGH
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Patent #:
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|
Issue Dt:
|
09/14/2021
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Application #:
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16548192
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Filing Dt:
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08/22/2019
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Publication #:
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Pub Dt:
|
12/12/2019
| | | | |
Title:
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FINFET DEVICE COMPRISING A SINGLE DIFFUSION BREAK WITH AN UPPER SURFACE THAT IS SUBSTANTIALLY COPLANAR WITH AN UPPER SURFACE OF A FIN
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|
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Patent #:
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|
Issue Dt:
|
07/28/2020
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Application #:
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16548335
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Filing Dt:
|
08/22/2019
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Publication #:
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|
Pub Dt:
|
12/12/2019
| | | | |
Title:
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GATE CONTACT STRUCTURE FOR A TRANSISTOR
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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16548355
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Filing Dt:
|
08/22/2019
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Publication #:
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Pub Dt:
|
12/12/2019
| | | | |
Title:
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THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
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|
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Patent #:
|
|
Issue Dt:
|
02/14/2023
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Application #:
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16548518
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Filing Dt:
|
08/22/2019
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Publication #:
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|
Pub Dt:
|
02/25/2021
| | | | |
Title:
|
PLANAR TRANSISTOR DEVICE COMPRISING AT LEAST ONE LAYER OF A TWO-DIMENSIONAL (2D) MATERIAL AND METHODS FOR MAKING SUCH TRANSISTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
06/15/2021
|
Application #:
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16549197
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Filing Dt:
|
08/23/2019
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Publication #:
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|
Pub Dt:
|
02/25/2021
| | | | |
Title:
|
WAVEGUIDE COUPLERS PROVIDING CONVERSION BETWEEN WAVEGUIDES
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|
|
Patent #:
|
|
Issue Dt:
|
10/27/2020
|
Application #:
|
16549415
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Filing Dt:
|
08/23/2019
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Title:
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EDGE COUPLERS FOR PHOTONICS APPLICATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
11/02/2021
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Application #:
|
16549466
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Filing Dt:
|
08/23/2019
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Publication #:
|
|
Pub Dt:
|
02/25/2021
| | | | |
Title:
|
WAVEGUIDE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2022
|
Application #:
|
16549478
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Filing Dt:
|
08/23/2019
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Publication #:
|
|
Pub Dt:
|
12/12/2019
| | | | |
Title:
|
IC PRODUCT COMPRISING A NOVEL INSULATING GATE SEPARATION STRUCTURE FOR TRANSISTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
09/29/2020
|
Application #:
|
16550385
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Filing Dt:
|
08/26/2019
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Publication #:
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|
Pub Dt:
|
12/12/2019
| | | | |
Title:
|
INJECTION LOCK POWER AMPLIFIER WITH BACK-GATE BIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2020
|
Application #:
|
16550431
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Filing Dt:
|
08/26/2019
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Publication #:
|
|
Pub Dt:
|
01/09/2020
| | | | |
Title:
|
INSULATING INDUCTOR CONDUCTORS WITH AIR GAP USING ENERGY EVAPORATION MATERIAL (EEM)
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|
|
Patent #:
|
|
Issue Dt:
|
07/14/2020
|
Application #:
|
16550999
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Filing Dt:
|
08/26/2019
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Title:
|
ANALOG-TO-DIGITAL CONVERTERS WITH RESISTOR DIGITAL-TO-ANALOG CONVERTERS FOR REFERENCE VOLTAGE TUNING
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|
|
Patent #:
|
|
Issue Dt:
|
08/25/2020
|
Application #:
|
16551038
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Filing Dt:
|
08/26/2019
|
Title:
|
ACROSS-WAFER PROFILE CONTROL IN SEMICONDUCTOR PROCESSES
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|
|
Patent #:
|
|
Issue Dt:
|
04/06/2021
|
Application #:
|
16551061
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Filing Dt:
|
08/26/2019
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Publication #:
|
|
Pub Dt:
|
03/04/2021
| | | | |
Title:
|
SELF-ALIGNED BASE AND EMITTER FOR A BIPOLAR JUNCTION TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2022
|
Application #:
|
16551794
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Filing Dt:
|
08/27/2019
|
Publication #:
|
|
Pub Dt:
|
03/04/2021
| | | | |
Title:
|
BODY-CONTACTED FIELD EFFECT TRANSISTORS CONFIGURED FOR TEST AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2022
|
Application #:
|
16553737
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Filing Dt:
|
08/28/2019
|
Publication #:
|
|
Pub Dt:
|
03/04/2021
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES INCLUDING STACKED DEPLETED AND HIGH RESISTIVITY REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2023
|
Application #:
|
16555734
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Filing Dt:
|
08/29/2019
|
Publication #:
|
|
Pub Dt:
|
12/19/2019
| | | | |
Title:
|
GATE CONTACT STRUCTURE FOR A TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2022
|
Application #:
|
16556465
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Filing Dt:
|
08/30/2019
|
Publication #:
|
|
Pub Dt:
|
03/04/2021
| | | | |
Title:
|
CONDUCTIVE STRUCTURES FOR CONTACTING A TOP ELECTRODE OF AN EMBEDDED MEMORY DEVICE AND METHODS OF MAKING SUCH CONTACT STRUCTURES ON AN IC PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2023
|
Application #:
|
16556796
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Filing Dt:
|
08/30/2019
|
Publication #:
|
|
Pub Dt:
|
03/04/2021
| | | | |
Title:
|
STRESS LAYOUT OPTIMIZATION FOR DEVICE PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2020
|
Application #:
|
16557128
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Filing Dt:
|
08/30/2019
|
Publication #:
|
|
Pub Dt:
|
12/19/2019
| | | | |
Title:
|
METHOD TO RECESS COBALT FOR GATE METAL APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2020
|
Application #:
|
16557195
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Filing Dt:
|
08/30/2019
|
Publication #:
|
|
Pub Dt:
|
12/19/2019
| | | | |
Title:
|
METHOD TO RECESS COBALT FOR GATE METAL APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2023
|
Application #:
|
16558095
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Filing Dt:
|
08/31/2019
|
Publication #:
|
|
Pub Dt:
|
03/04/2021
| | | | |
Title:
|
TRANSMITTER UNIT SUITABLE FOR MILLIMETER WAVE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2024
|
Application #:
|
16558106
|
Filing Dt:
|
08/31/2019
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2020
|
Application #:
|
16558599
|
Filing Dt:
|
09/03/2019
|
Title:
|
CIRCUIT STRUCTURE FOR ADJUSTING PTAT CURRENT TO COMPENSATE FOR PROCESS VARIATIONS IN DEVICE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2021
|
Application #:
|
16559979
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Filing Dt:
|
09/04/2019
|
Publication #:
|
|
Pub Dt:
|
03/04/2021
| | | | |
Title:
|
HYBRID WAVELENGTH-DIVISION MULTIPLEXING FILTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2021
|
Application #:
|
16560591
|
Filing Dt:
|
09/04/2019
|
Title:
|
ANTI-FUSE FOR AN INTEGRATED CIRCUIT (IC) PRODUCT AND METHOD OF MAKING SUCH AN ANTI-FUSE FOR AN IC PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2020
|
Application #:
|
16561702
|
Filing Dt:
|
09/05/2019
|
Title:
|
OVERLAY CONTROL WITH CORRECTIONS FOR LENS ABERRATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2021
|
Application #:
|
16561956
|
Filing Dt:
|
09/05/2019
|
Publication #:
|
|
Pub Dt:
|
03/11/2021
| | | | |
Title:
|
VERTICALLY STACKED FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2020
|
Application #:
|
16562481
|
Filing Dt:
|
09/06/2019
|
Publication #:
|
|
Pub Dt:
|
12/26/2019
| | | | |
Title:
|
CUT INSIDE REPLACEMENT METAL GATE TRENCH TO MITIGATE N-P PROXIMITY EFFECT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2022
|
Application #:
|
16568242
|
Filing Dt:
|
09/11/2019
|
Publication #:
|
|
Pub Dt:
|
03/11/2021
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH GATE CUT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2021
|
Application #:
|
16568591
|
Filing Dt:
|
09/12/2019
|
Publication #:
|
|
Pub Dt:
|
03/18/2021
| | | | |
Title:
|
EXTENDED-DRAIN FIELD-EFFECT TRANSISTORS INCLUDING A FLOATING GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2022
|
Application #:
|
16568902
|
Filing Dt:
|
09/12/2019
|
Publication #:
|
|
Pub Dt:
|
01/02/2020
| | | | |
Title:
|
SELF ALIGNED BURIED POWER RAIL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2020
|
Application #:
|
16570575
|
Filing Dt:
|
09/13/2019
|
Title:
|
METAL RESISTORS WITH A NON-PLANAR CONFIGURATION
|
|