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04/29/2008
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10184422
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06/27/2002
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09/11/2003
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05/29/2007
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06/27/2002
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10/09/2003
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09/30/2003
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06/27/2002
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05/15/2003
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09/30/2003
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10185146
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06/27/2002
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05/15/2003
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12/16/2003
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10185320
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06/28/2002
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08/24/2004
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07/01/2002
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01/01/2004
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02/24/2004
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10192386
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07/09/2002
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12/05/2002
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06/17/2003
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07/16/2002
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01/11/2005
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10196611
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07/16/2002
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01/22/2004
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09/06/2005
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07/17/2002
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01/22/2004
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07/20/2004
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07/18/2002
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01/22/2004
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09/14/2004
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07/19/2002
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01/22/2004
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08/31/2004
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07/22/2002
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01/22/2004
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08/31/2004
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07/25/2002
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12/05/2002
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11/16/2004
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07/25/2002
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01/29/2004
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09/28/2004
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07/24/2002
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11/28/2002
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12/09/2003
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07/24/2002
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05/25/2004
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10207352
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07/29/2002
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01/29/2004
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07/27/2004
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07/29/2002
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01/29/2004
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05/25/2004
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07/29/2002
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01/02/2003
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11/23/2004
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07/30/2002
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08/28/2003
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12/30/2003
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07/31/2002
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12/14/2004
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08/01/2002
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03/27/2003
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12/09/2003
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07/30/2002
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06/15/2004
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07/30/2002
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02/05/2004
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01/06/2004
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10210637
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07/31/2002
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08/28/2003
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05/18/2004
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07/31/2002
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11/11/2003
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10213646
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08/06/2002
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12/19/2002
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09/07/2004
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10213882
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08/07/2002
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02/12/2004
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METHODOLOGY AND APPARATUS USING REAL-TIME OPTICAL SIGNAL FOR WAFER-LEVEL DEVICE DIELECTRICAL RELIABILITY STUDIES
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11/30/2004
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08/07/2002
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02/12/2004
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11/08/2005
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08/07/2002
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02/12/2004
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06/15/2004
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08/08/2002
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11/04/2003
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08/08/2002
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06/24/2003
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08/09/2002
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01/20/2004
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08/12/2002
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09/09/2003
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08/14/2002
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08/31/2004
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08/14/2002
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09/23/2003
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08/13/2002
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12/23/2003
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08/16/2002
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12/14/2004
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08/22/2002
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01/02/2003
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04/27/2004
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08/23/2002
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02/26/2004
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11/23/2004
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08/26/2002
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02/26/2004
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01/16/2007
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08/26/2002
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02/26/2004
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05/18/2004
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08/26/2002
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02/26/2004
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08/31/2004
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08/29/2002
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10/10/2006
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08/29/2002
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09/02/2003
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08/30/2002
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02/07/2006
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08/30/2002
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06/27/2006
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08/30/2002
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09/30/2008
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08/28/2002
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03/04/2004
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10/12/2004
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08/30/2002
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03/06/2012
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08/30/2002
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03/30/2004
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09/05/2002
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06/08/2004
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09/03/2002
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03/04/2004
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11/02/2004
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09/05/2002
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03/11/2004
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12/16/2003
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09/05/2002
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08/12/2003
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09/09/2002
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04/13/2004
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09/10/2002
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01/16/2003
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09/13/2005
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10241979
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Filing Dt:
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09/11/2002
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Publication #:
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Pub Dt:
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03/20/2003
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Title:
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DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD
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Patent #:
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Issue Dt:
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07/27/2004
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10242235
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Filing Dt:
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09/12/2002
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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METHOD AND SYSTEM FOR POWER NODE CURRENT WAVEFORM MODELING
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10244204
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Filing Dt:
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09/16/2002
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Title:
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PREPARATION OF HIGH-K NITRIDE SILICATE LAYERS BY CYCLIC MOLECULAR LAYER DEPOSITION
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Patent #:
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Issue Dt:
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07/13/2004
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Application #:
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10246147
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Filing Dt:
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09/17/2002
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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METHOD TO OBTAIN HIGH DENSITY SIGNAL WIRES WITH LOW RESISTANCE IN AN ELECTRONIC PACKAGE
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10246252
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Filing Dt:
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09/18/2002
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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OXYNITRIDE SHALLOW TRENCH ISOLATION AND METHOD OF FORMATION
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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10246267
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Filing Dt:
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09/18/2002
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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SEMICONDUCTOR DEVICE WITH METAL GATE ELECTRODE AND SILICON OXYNITRIDE SPACER
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10246572
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Filing Dt:
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09/18/2002
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Title:
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METHODS OF CONTROLLING GATE ELECTRODE DOPING, AND SYSTEMS FOR ACCOMPLISHING SAME
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10247415
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Filing Dt:
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09/19/2002
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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SYSTEM FOR PROGRAMMING FUSE STRUCTURE BY ELECTROMIGRATION OF SILICIDE ENHANCED BY CREATING TEMPERATURE GRADIENT
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10248019
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Filing Dt:
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12/11/2002
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Title:
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SUBLITHOGRAPHIC PATTERNING USING MICROTRENCHING
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10248696
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Filing Dt:
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02/10/2003
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Publication #:
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Pub Dt:
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08/12/2004
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Title:
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POWER SWITCH CIRCUIT SIZING TECHNIQUE
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10248819
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Filing Dt:
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02/21/2003
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Publication #:
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Pub Dt:
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08/26/2004
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Title:
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CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS
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Patent #:
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Issue Dt:
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01/31/2006
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10249291
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Filing Dt:
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03/28/2003
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Publication #:
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Pub Dt:
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09/30/2004
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Title:
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HIGH SPEED CLOCK DIVIDER WITH SYNCHRONOUS PHASE START-UP OVER PHYSICALLY DISTRIBUTED SPACE
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Patent #:
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Issue Dt:
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09/14/2004
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10249296
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Filing Dt:
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03/28/2003
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Publication #:
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Pub Dt:
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09/30/2004
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Title:
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PRESERVING TEOS HARD MASK USING COR FOR RAISED SOURCE-DRAIN INCLUDING REMOVABLE/DISPOSABLE SPACER
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10249509
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
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10/21/2004
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Title:
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METHOD OF VERIFYING THE PLACEMENT OF SUB-RESOLUTION ASSIST FEATURES IN A PHOTOMASK LAYOUT
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10249550
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Filing Dt:
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04/17/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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PREVENTION OF TA2O5 MIM CAP SHORTING IN THE BEOL ANNEAL CYCLES
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10249563
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Filing Dt:
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04/18/2003
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Title:
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BICMOS INTEGRATION SCHEME WITH RAISED EXTRINSIC BASE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10249821
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Filing Dt:
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05/09/2003
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Pub Dt:
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11/11/2004
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Title:
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METHOD TO FABRICATE HIGH-PERFORMANCE NPN TRANSISTORS IN A BICMOS PROCESS
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10249944
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Filing Dt:
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05/21/2003
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Title:
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METHOD FOR EVALUATING THE EFFECTS OF MULTIPLE EXPOSURE PROCESSES IN LITHOGRAPHY
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10249997
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Filing Dt:
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05/27/2003
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL FABRICATION
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10250100
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Filing Dt:
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06/04/2003
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Title:
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NITRIDE PEDESTAL FOR RAISED EXTRINSIC BASE HBT PROCESS
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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10250157
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Filing Dt:
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06/09/2003
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Publication #:
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Pub Dt:
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12/09/2004
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Title:
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SOI TRENCH CAPACITOR CELL INCORPORATING A LOW-LEAKAGE FLOATING BODY ARRAY TRANSISTOR
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10250159
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Filing Dt:
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06/09/2003
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Publication #:
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Pub Dt:
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12/09/2004
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Title:
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LEVEL SHIFT CIRCUITRY HAVING DELAY BOOST
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10250259
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Filing Dt:
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06/18/2003
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Title:
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TRENCH CAPACITOR DRAM CELL USING BURIED OXIDE AS ARRAY TOP OXIDE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10254209
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Filing Dt:
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09/25/2002
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Pub Dt:
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03/25/2004
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Title:
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CORRELATING AN INLINE PARAMETER TO A DEVICE OPERATION PARAMETER
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10254239
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Filing Dt:
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09/25/2002
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Title:
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LAND GRID ARRAY CONNECTOR AND METHOD FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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10254391
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Filing Dt:
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09/25/2002
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Title:
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STRESS REDUCING STIFFENER RING
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Patent #:
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Issue Dt:
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06/29/2004
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10254414
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Filing Dt:
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09/25/2002
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Pub Dt:
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03/25/2004
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Title:
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SEMICONDUCTOR CHIP MODULE AND METHOD OF MANUFACTURE OF SAME
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Issue Dt:
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11/25/2003
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Application #:
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10254432
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Filing Dt:
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09/24/2002
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Title:
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MAGNETIC MEMORY WITH TUNNEL JUNCTION MEMORY CELLS AND PHASE TRANSITION MATERIAL FOR CONTROLLING CURRENT TO THE CELLS
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Issue Dt:
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10/03/2006
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10255351
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09/26/2002
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04/01/2004
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Title:
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SYSTEM AND METHOD FOR MOLECULAR OPTICAL EMISSION
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Issue Dt:
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01/13/2004
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10255457
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09/26/2002
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Title:
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PACKAGE FOR ELECTRONIC COMPONENT
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Issue Dt:
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07/05/2005
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10255469
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09/26/2002
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Pub Dt:
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04/01/2004
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Title:
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APPARATUS AND METHOD FOR INCORPORATING DRIVER SIZING INTO BUFFER INSERTION USING A DELAY PENALTY ESTIMATION TECHNIQUE
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Issue Dt:
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09/23/2003
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10255509
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09/26/2002
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Title:
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METHOD FOR CALIBRATING OPTICAL-BASED METROLOGY TOOLS
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06/01/2004
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10256881
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09/27/2002
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Pub Dt:
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04/01/2004
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Title:
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NON-VOLATILE MEMORY USING FERROELECTRIC GATE FIELD-EFFECT TRANSISTORS
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08/22/2006
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10256970
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09/27/2002
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Title:
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COMPUTER SYSTEM WITH PROCESSOR CACHE THAT STORES REMOTE CACHE PRESENCE INFORMATION
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Issue Dt:
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10/03/2006
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10259016
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09/27/2002
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09/04/2003
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Title:
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SEMICONDUCTOR DEVICE HAVING DIFFERENT METAL-SEMICONDUCTOR PORTIONS FORMED IN A SEMICONDUCTOR REGION AND A METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
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Issue Dt:
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08/22/2006
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10259665
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09/27/2002
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10/02/2003
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Title:
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ON-CHIP HIGH SPEED DATA INTERFACE
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Issue Dt:
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02/27/2007
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10259708
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09/27/2002
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10/30/2003
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Title:
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DIGITAL AUTOMATIC GAIN CONTROL FOR TRANSCEIVER DEVICES
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Issue Dt:
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07/26/2005
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10259710
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09/27/2002
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Pub Dt:
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10/09/2003
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Title:
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ATA/SATA COMBINED CONTROLLER
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Issue Dt:
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02/22/2005
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Application #:
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10260087
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09/27/2002
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Pub Dt:
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04/01/2004
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Title:
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METHOD AND APPARATUS FOR DLL LOCK LATENCY DETECTION
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Issue Dt:
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08/12/2003
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Application #:
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10261219
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09/30/2002
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Title:
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PROCESS FLOW FOR THICK ISOLATION COLLAR WITH REDUCED LENGTH
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Issue Dt:
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07/06/2004
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Application #:
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10261559
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Filing Dt:
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09/30/2002
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Pub Dt:
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04/01/2004
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Title:
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MEMORY CELL WITH VERTICAL TRANSISTOR AND TRENCH CAPACITOR WITH REDUCED BURRIED STRAP
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Patent #:
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Issue Dt:
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06/15/2010
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Application #:
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10261613
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Filing Dt:
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09/30/2002
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Title:
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RESIST TRIM PROCESS TO DEFINE SMALL OPENINGS IN DIELECTRIC LAYERS
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