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Reel/Frame:038954/0001   Pages: 961
Recorded: 06/02/2016
Attorney Dkt #:065664/0012
Conveyance: PATENT SECURITY AGREEMENT
Total properties: 18021
Page 90 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
7457978
Issue Dt:
11/25/2008
Application #:
11124744
Filing Dt:
05/09/2005
Publication #:
US20060253721
Pub Dt:
11/09/2006
Title:
ADJUSTABLE BYTE LANE OFFSET FOR MEMORY MODULE TO REDUCE SKEW
2
Patent #:
7075856
Issue Dt:
07/11/2006
Application #:
11124784
Filing Dt:
05/09/2005
Publication #:
US20050206420
Pub Dt:
09/22/2005
Title:
APPARATUS FOR LATENCY SPECIFIC DUTY CYCLE CORRECTION
3
Patent #:
7368696
Issue Dt:
05/06/2008
Application #:
11125096
Filing Dt:
05/10/2005
Publication #:
US20060231734
Pub Dt:
10/19/2006
Title:
GENERATION AND STORAGE OF COLUMN OFFSETS FOR A COLUMN PARALLEL IMAGE SENSOR
4
Patent #:
7872682
Issue Dt:
01/18/2011
Application #:
11125097
Filing Dt:
05/10/2005
Publication #:
US20060256220
Pub Dt:
11/16/2006
Title:
ECLIPSE ELIMINATION BY MONITORING THE PIXEL SIGNAL LEVEL
5
Patent #:
7405455
Issue Dt:
07/29/2008
Application #:
11126455
Filing Dt:
05/10/2005
Publication #:
US20050205900
Pub Dt:
09/22/2005
Title:
SEMICONDUCTOR CONSTRUCTIONS AND TRANSISTOR GATES
6
Patent #:
7391654
Issue Dt:
06/24/2008
Application #:
11126682
Filing Dt:
05/11/2005
Publication #:
US20060256622
Pub Dt:
11/16/2006
Title:
MEMORY BLOCK ERASING IN A FLASH MEMORY DEVICE
7
Patent #:
7480195
Issue Dt:
01/20/2009
Application #:
11126747
Filing Dt:
05/11/2005
Publication #:
US20060256631
Pub Dt:
11/16/2006
Title:
INTERNAL DATA COMPARISON FOR MEMORY TESTING
8
Patent #:
7443009
Issue Dt:
10/28/2008
Application #:
11126826
Filing Dt:
05/11/2005
Publication #:
US20060255393
Pub Dt:
11/16/2006
Title:
N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE
9
Patent #:
7221603
Issue Dt:
05/22/2007
Application #:
11127465
Filing Dt:
05/12/2005
Publication #:
US20060256629
Pub Dt:
11/16/2006
Title:
DEFECTIVE BLOCK HANDLING IN A FLASH MEMORY DEVICE
10
Patent #:
7203092
Issue Dt:
04/10/2007
Application #:
11127466
Filing Dt:
05/12/2005
Publication #:
US20060256618
Pub Dt:
11/16/2006
Title:
FLASH MEMORY ARRAY USING ADJACENT BIT LINE AS SOURCE
11
Patent #:
7227789
Issue Dt:
06/05/2007
Application #:
11127526
Filing Dt:
05/12/2005
Publication #:
US20060098497
Pub Dt:
05/11/2006
Title:
METHOD AND APPARATUS FOR FILTERING OUTPUT DATA
12
Patent #:
7113435
Issue Dt:
09/26/2006
Application #:
11127599
Filing Dt:
05/12/2005
Publication #:
US20050213397
Pub Dt:
09/29/2005
Title:
DATA COMPRESSION READ MODE FOR MEMORY TESTING
13
Patent #:
7279740
Issue Dt:
10/09/2007
Application #:
11127618
Filing Dt:
05/12/2005
Publication #:
US20060258090
Pub Dt:
11/16/2006
Title:
BAND-ENGINEERED MULTI-GATED NON-VOLATILE MEMORY DEVICE WITH ENHANCED ATTRIBUTES
14
Patent #:
7434152
Issue Dt:
10/07/2008
Application #:
11127810
Filing Dt:
05/12/2005
Publication #:
US20060044880
Pub Dt:
03/02/2006
Title:
MULTIPLE-LEVEL DATA COMPRESSION READ MODE FOR MEMORY TESTING
15
Patent #:
7767129
Issue Dt:
08/03/2010
Application #:
11127942
Filing Dt:
05/11/2005
Publication #:
US20060255505
Pub Dt:
11/16/2006
Title:
IMPRINT TEMPLATES FOR IMPRINT LITHOGRAPHY, AND METHODS OF PATTERNING A PLURALITY OF SUBSTRATES
16
Patent #:
7407885
Issue Dt:
08/05/2008
Application #:
11127943
Filing Dt:
05/11/2005
Publication #:
US20060258155
Pub Dt:
11/16/2006
Title:
METHODS OF FORMING ELECTRICALLY CONDUCTIVE PLUGS
17
Patent #:
7713885
Issue Dt:
05/11/2010
Application #:
11127944
Filing Dt:
05/11/2005
Publication #:
US20060258169
Pub Dt:
11/16/2006
Title:
METHODS OF ETCHING OXIDE, REDUCING ROUGHNESS, AND FORMING CAPACITOR CONSTRUCTIONS
18
Patent #:
7407892
Issue Dt:
08/05/2008
Application #:
11127945
Filing Dt:
05/11/2005
Publication #:
US20060258157
Pub Dt:
11/16/2006
Title:
DEPOSITION METHODS
19
Patent #:
7224009
Issue Dt:
05/29/2007
Application #:
11128176
Filing Dt:
05/13/2005
Publication #:
US20050205905
Pub Dt:
09/22/2005
Title:
METHOD FOR FORMING A LOW LEAKAGE CONTACT IN A CMOS IMAGER
20
Patent #:
7120046
Issue Dt:
10/10/2006
Application #:
11128585
Filing Dt:
05/13/2005
Title:
MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES
21
Patent #:
7419852
Issue Dt:
09/02/2008
Application #:
11129105
Filing Dt:
05/13/2005
Publication #:
US20060043569
Pub Dt:
03/02/2006
Title:
LOW TEMPERATURE METHODS OF FORMING BACK SIDE REDISTRIBUTION LAYERS IN ASSOCIATION WITH THROUGH WAFER INTERCONNECTS, SEMICONDUCTOR DEVICES INCLUDING SAME, AND ASSEMBLIES
22
Patent #:
7320049
Issue Dt:
01/15/2008
Application #:
11129150
Filing Dt:
05/13/2005
Publication #:
US20050207254
Pub Dt:
09/22/2005
Title:
DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION
23
Patent #:
7269079
Issue Dt:
09/11/2007
Application #:
11129315
Filing Dt:
05/16/2005
Publication #:
US20060256640
Pub Dt:
11/16/2006
Title:
POWER CIRCUITS FOR REDUCING A NUMBER OF POWER SUPPLY VOLTAGE TAPS REQUIRED FOR SENSING A RESISTIVE MEMORY
24
Patent #:
7371627
Issue Dt:
05/13/2008
Application #:
11129502
Filing Dt:
05/13/2005
Title:
MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES
25
Patent #:
7683456
Issue Dt:
03/23/2010
Application #:
11129630
Filing Dt:
05/13/2005
Publication #:
US20050207256
Pub Dt:
09/22/2005
Title:
SEMICONDUCTOR DEVICES, CAPACITOR ANTIFUSES, DYNAMIC RANDOM ACCESS MEMORIES, AND CELL PLATE BIAS CONNECTION METHODS
26
Patent #:
7439157
Issue Dt:
10/21/2008
Application #:
11129884
Filing Dt:
05/16/2005
Publication #:
US20050287731
Pub Dt:
12/29/2005
Title:
ISOLATION TRENCHES FOR MEMORY DEVICES
27
Patent #:
7236387
Issue Dt:
06/26/2007
Application #:
11130598
Filing Dt:
05/17/2005
Publication #:
US20050231996
Pub Dt:
10/20/2005
Title:
WRITING TO FERROELECTRIC MEMORY DEVICES
28
Patent #:
7123503
Issue Dt:
10/17/2006
Application #:
11130663
Filing Dt:
05/17/2005
Publication #:
US20050213365
Pub Dt:
09/29/2005
Title:
WRITING TO FERROELECTRIC MEMORY DEVICES
29
Patent #:
7470628
Issue Dt:
12/30/2008
Application #:
11130760
Filing Dt:
05/17/2005
Publication #:
US20050218373
Pub Dt:
10/06/2005
Title:
ETCHING METHODS
30
Patent #:
7612403
Issue Dt:
11/03/2009
Application #:
11131006
Filing Dt:
05/17/2005
Publication #:
US20060261401
Pub Dt:
11/23/2006
Title:
NOVEL LOW POWER NON-VOLATILE MEMORY AND GATE STACK
31
Patent #:
7273566
Issue Dt:
09/25/2007
Application #:
11131070
Filing Dt:
07/07/2005
Publication #:
US20060011579
Pub Dt:
01/19/2006
Title:
GAS COMPOSITIONS
32
Patent #:
7052584
Issue Dt:
05/30/2006
Application #:
11131078
Filing Dt:
05/17/2005
Publication #:
US20050208219
Pub Dt:
09/22/2005
Title:
METHOD OF FORMING A CAPACITOR
33
Patent #:
7333370
Issue Dt:
02/19/2008
Application #:
11131081
Filing Dt:
05/17/2005
Publication #:
US20050213410
Pub Dt:
09/29/2005
Title:
METHOD TO PREVENT BIT LINE CAPACITIVE COUPLING
34
Patent #:
7473662
Issue Dt:
01/06/2009
Application #:
11131165
Filing Dt:
05/17/2005
Publication #:
US20050221006
Pub Dt:
10/06/2005
Title:
METAL-DOPED ALUMINA AND LAYERS THEREOF
35
Patent #:
7517753
Issue Dt:
04/14/2009
Application #:
11131552
Filing Dt:
05/18/2005
Publication #:
US20060263968
Pub Dt:
11/23/2006
Title:
METHODS OF FORMING PLURALITIES OF CAPACITORS
36
Patent #:
7443022
Issue Dt:
10/28/2008
Application #:
11131553
Filing Dt:
05/18/2005
Publication #:
US20050205973
Pub Dt:
09/22/2005
Title:
BOARD-ON-CHIP PACKAGES
37
Patent #:
7544563
Issue Dt:
06/09/2009
Application #:
11131575
Filing Dt:
05/18/2005
Publication #:
US20060261440
Pub Dt:
11/23/2006
Title:
METHODS OF FORMING A PLURALITY OF CAPACITORS
38
Patent #:
7341906
Issue Dt:
03/11/2008
Application #:
11132472
Filing Dt:
05/19/2005
Publication #:
US20060263969
Pub Dt:
11/23/2006
Title:
METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME
39
Patent #:
7471130
Issue Dt:
12/30/2008
Application #:
11132502
Filing Dt:
05/19/2005
Publication #:
US20060261869
Pub Dt:
11/23/2006
Title:
GRADUATED DELAY LINE FOR INCREASED CLOCK SKEW CORRECTION CIRCUIT OPERATING RANGE
40
Patent #:
7289363
Issue Dt:
10/30/2007
Application #:
11132602
Filing Dt:
05/19/2005
Publication #:
US20060262601
Pub Dt:
11/23/2006
Title:
MEMORY CELL REPAIR USING FUSE PROGRAMMING METHOD IN A FLASH MEMORY DEVICE
41
Patent #:
7239549
Issue Dt:
07/03/2007
Application #:
11132979
Filing Dt:
05/19/2005
Publication #:
US20050213379
Pub Dt:
09/29/2005
Title:
SEMICONDUCTOR DEVICE
42
Patent #:
7235448
Issue Dt:
06/26/2007
Application #:
11133061
Filing Dt:
05/19/2005
Publication #:
US20050215015
Pub Dt:
09/29/2005
Title:
DIELECTRIC LAYER FORMING METHOD AND DEVICES FORMED THEREWITH
43
Patent #:
7393770
Issue Dt:
07/01/2008
Application #:
11133085
Filing Dt:
05/19/2005
Publication #:
US20060261446
Pub Dt:
11/23/2006
Title:
BACKSIDE METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH CONDUCTIVE INTERCONNECTS
44
Patent #:
7082045
Issue Dt:
07/25/2006
Application #:
11133236
Filing Dt:
05/20/2005
Publication #:
US20050219928
Pub Dt:
10/06/2005
Title:
OFFSET COMPENSATED SENSING FOR MAGNETIC RANDOM ACCESS MEMORY
45
Patent #:
7274201
Issue Dt:
09/25/2007
Application #:
11133843
Filing Dt:
05/19/2005
Publication #:
US20060261836
Pub Dt:
11/23/2006
Title:
METHOD AND SYSTEM FOR STRESSING SEMICONDUCTOR WAFERS DURING BURN-IN
46
Patent #:
7402879
Issue Dt:
07/22/2008
Application #:
11134321
Filing Dt:
05/23/2005
Publication #:
US20050207217
Pub Dt:
09/22/2005
Title:
LAYERED MAGNETIC STRUCTURES HAVING IMPROVED SURFACE PLANARITY FOR BIT MATERIAL DEPOSITION
47
Patent #:
7429536
Issue Dt:
09/30/2008
Application #:
11134982
Filing Dt:
05/23/2005
Publication #:
US20060263699
Pub Dt:
11/23/2006
Title:
METHODS FOR FORMING ARRAYS OF A SMALL, CLOSELY SPACED FEATURES
48
Patent #:
7250663
Issue Dt:
07/31/2007
Application #:
11135558
Filing Dt:
05/24/2005
Publication #:
US20050285265
Pub Dt:
12/29/2005
Title:
FRAME SCALE PACKAGE USING CONTACT LINES THROUGH THE ELEMENTS
49
Patent #:
7006382
Issue Dt:
02/28/2006
Application #:
11136145
Filing Dt:
05/24/2005
Publication #:
US20050219908
Pub Dt:
10/06/2005
Title:
PROGRAMMING FLASH MEMORIES
50
Patent #:
7752381
Issue Dt:
07/06/2010
Application #:
11136152
Filing Dt:
05/24/2005
Publication #:
US20060271725
Pub Dt:
11/30/2006
Title:
VERSION BASED NON-VOLATILE MEMORY TRANSLATION LAYER
51
Patent #:
7179717
Issue Dt:
02/20/2007
Application #:
11136823
Filing Dt:
05/25/2005
Publication #:
US20060270181
Pub Dt:
11/30/2006
Title:
METHODS OF FORMING INTEGRATED CIRCUIT DEVICES
52
Patent #:
7276951
Issue Dt:
10/02/2007
Application #:
11136893
Filing Dt:
05/25/2005
Publication #:
US20060267648
Pub Dt:
11/30/2006
Title:
DELAY LINE CIRCUIT
53
Patent #:
7321160
Issue Dt:
01/22/2008
Application #:
11137034
Filing Dt:
05/25/2005
Publication #:
US20050224928
Pub Dt:
10/13/2005
Title:
MULTI-PART LEAD FRAME
54
Patent #:
7313273
Issue Dt:
12/25/2007
Application #:
11137393
Filing Dt:
05/26/2005
Publication #:
US20050237550
Pub Dt:
10/27/2005
Title:
AUTOMATIC COLOR CONSTANCY FOR IMAGE SENSORS
55
Patent #:
7808063
Issue Dt:
10/05/2010
Application #:
11137446
Filing Dt:
05/26/2005
Publication #:
US20060268143
Pub Dt:
11/30/2006
Title:
STRUCTURE AND METHOD FOR FPN REDUCTION IN IMAGING DEVICES
56
Patent #:
7353349
Issue Dt:
04/01/2008
Application #:
11137700
Filing Dt:
05/24/2005
Publication #:
US20050248579
Pub Dt:
11/10/2005
Title:
METHOD AND APPARATUS FOR REORDERING MEMORY REQUESTS FOR PAGE COHERENCY
57
Patent #:
7365570
Issue Dt:
04/29/2008
Application #:
11137978
Filing Dt:
05/25/2005
Publication #:
US20060267633
Pub Dt:
11/30/2006
Title:
PSEUDO-DIFFERENTIAL OUTPUT DRIVER WITH HIGH IMMUNITY TO NOISE AND JITTER
58
Patent #:
7378707
Issue Dt:
05/27/2008
Application #:
11138527
Filing Dt:
05/26/2005
Publication #:
US20060267072
Pub Dt:
11/30/2006
Title:
SCALABLE HIGH DENSITY NON-VOLATILE MEMORY CELLS IN A CONTACTLESS MEMORY ARRAY
59
Patent #:
7109068
Issue Dt:
09/19/2006
Application #:
11138544
Filing Dt:
05/26/2005
Publication #:
US20060046468
Pub Dt:
03/02/2006
Title:
THROUGH-SUBSTRATE INTERCONNECT FABRICATION METHODS
60
Patent #:
7547599
Issue Dt:
06/16/2009
Application #:
11138575
Filing Dt:
05/26/2005
Publication #:
US20060267075
Pub Dt:
11/30/2006
Title:
MULTI-STATE MEMORY CELL
61
Patent #:
7366012
Issue Dt:
04/29/2008
Application #:
11138884
Filing Dt:
05/25/2005
Publication #:
US20050270892
Pub Dt:
12/08/2005
Title:
SYNCHRONOUS MEMORY DEVICE WITH REDUCED POWER CONSUMPTION
62
Patent #:
7894563
Issue Dt:
02/22/2011
Application #:
11138910
Filing Dt:
05/27/2005
Publication #:
US20050265504
Pub Dt:
12/01/2005
Title:
CLOCK RECOVERY CIRCUIT AND A METHOD OF GENERATING A RECOVERED CLOCK SIGNAL
63
Patent #:
7219418
Issue Dt:
05/22/2007
Application #:
11138920
Filing Dt:
05/26/2005
Publication #:
US20050225341
Pub Dt:
10/13/2005
Title:
METHOD TO PREVENT DAMAGE TO PROBE CARD
64
Patent #:
8954687
Issue Dt:
02/10/2015
Application #:
11139274
Filing Dt:
05/27/2005
Publication #:
US20050223161
Pub Dt:
10/06/2005
Title:
MEMORY HUB AND ACCESS METHOD HAVING A SEQUENCER AND INTERNAL ROW CACHING
65
Patent #:
7598167
Issue Dt:
10/06/2009
Application #:
11140402
Filing Dt:
05/27/2005
Publication #:
US20060046463
Pub Dt:
03/02/2006
Title:
METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES WITHOUT DAMAGING ACTIVE REGIONS THEREOF AND RESULTING STRUCTURES
66
Patent #:
7918383
Issue Dt:
04/05/2011
Application #:
11140420
Filing Dt:
05/27/2005
Publication #:
US20060043154
Pub Dt:
03/02/2006
Title:
METHODS FOR PLACING SUBSTRATES IN CONTACT WITH MOLTEN SOLDER
67
Patent #:
7573136
Issue Dt:
08/11/2009
Application #:
11140422
Filing Dt:
05/27/2005
Publication #:
US20050218518
Pub Dt:
10/06/2005
Title:
SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING MULTIPLE SEMICONDUCTOR DEVICE COMPONENTS
68
Patent #:
7572695
Issue Dt:
08/11/2009
Application #:
11140643
Filing Dt:
05/27/2005
Publication #:
US20060270147
Pub Dt:
11/30/2006
Title:
HAFNIUM TITANIUM OXIDE FILMS
69
Patent #:
7532532
Issue Dt:
05/12/2009
Application #:
11140791
Filing Dt:
05/31/2005
Publication #:
US20060268643
Pub Dt:
11/30/2006
Title:
SYSTEM AND METHOD FOR HIDDEN-REFRESH RATE MODIFICATION
70
Patent #:
7315074
Issue Dt:
01/01/2008
Application #:
11140859
Filing Dt:
05/31/2005
Publication #:
US20050218474
Pub Dt:
10/06/2005
Title:
USE OF DAR COATING TO MODULATE THE EFFICIENCY OF LASER FUSE BLOWS
71
Patent #:
7279770
Issue Dt:
10/09/2007
Application #:
11141387
Filing Dt:
06/01/2005
Publication #:
US20060043525
Pub Dt:
03/02/2006
Title:
ISOLATION TECHNIQUES FOR REDUCING DARK CURRENT IN CMOS IMAGE SENSORS
72
Patent #:
7119563
Issue Dt:
10/10/2006
Application #:
11142226
Filing Dt:
06/01/2005
Publication #:
US20050206400
Pub Dt:
09/22/2005
Title:
INTEGRATED CIRCUIT CHARACTERIZATION PRINTED CIRCUIT BOARD
73
Patent #:
7339811
Issue Dt:
03/04/2008
Application #:
11142447
Filing Dt:
06/02/2005
Publication #:
US20050226037
Pub Dt:
10/13/2005
Title:
STACKED COLUMNAR 1T-NMTJ MRAM STRUCTURE AND ITS METHOD OF FORMATION AND OPERATION
74
Patent #:
7440339
Issue Dt:
10/21/2008
Application #:
11142448
Filing Dt:
06/02/2005
Publication #:
US20050226038
Pub Dt:
10/13/2005
Title:
STACKED COLUMNAR 1T-NMTJ MRAM STRUCTURE AND ITS METHOD OF FORMATION AND OPERATION
75
Patent #:
7291543
Issue Dt:
11/06/2007
Application #:
11142578
Filing Dt:
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Title:
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Title:
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Pub Dt:
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Title:
DLL MEASURE INITIALIZATION CIRCUIT FOR HIGH FREQUENCY OPERATION
Assignor
1
MICRON TECHNOLOGY, INC.
Exec Dt:
04/26/2016
Assignee
1
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
1300 THAMES STREET, 4TH FLOOR
BALTIMORE, MARYLAND 21231
Correspondence name and address
GENEVIEVE DORMENT, ESQ.
SIMPSON THACHER & BARTLETT LLP
425 LEXINGTON AVENUE
NEW YORK, NY 10017

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