Patent Assignment Details
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Reel/Frame: | 026657/0012 | |
| Pages: | 2 |
| | Recorded: | 07/26/2011 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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10063119
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Filing Dt:
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03/22/2002
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Title:
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CAPACITORLESS DRAM GAIN CELL
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10063450
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Filing Dt:
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04/24/2002
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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DATA-BASED CONTROL OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10065955
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Filing Dt:
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12/04/2002
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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ION IMPLANTATION METHODS AND TRANSISTOR CELL LAYOUT FOR FIN TYPE TRANSISTORS
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10604339
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Filing Dt:
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07/13/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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COMPLEMENTARY SOURCE FOLLOWER CIRCUIT CONTROLLED BY BACK BIAS VOLTAGE
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10707450
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Filing Dt:
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12/15/2003
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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INTEGRATED CIRCUITS HAVING POST-SILICON ADJUSTMENT CONTROL
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10709481
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Filing Dt:
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05/08/2004
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Publication #:
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Pub Dt:
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01/13/2005
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Title:
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RESISTANCE LOAD SOURCE FOLLOWER CIRCUIT
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Assignee
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NISHI 3-2-62 |
KUNITACHI-SHI |
TOKYO, JAPAN 186-0005 |
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Correspondence name and address
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PAUL J. LERNER
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75 MONTEBELLO ROAD
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SUFFERN, NY 10901
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