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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 10 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
Issue Dt:
09/11/2001
Application #:
09062205
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR LOCAL OPTIMIZATION OF THE GLOBAL ROUTING
2
Patent #:
Issue Dt:
01/16/2001
Application #:
09062217
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR HIERARCHICAL GLOBAL ROUTING DESCEND
3
Patent #:
Issue Dt:
06/26/2001
Application #:
09062218
Filing Dt:
04/17/1998
Title:
NET ROUTING USING BASIS ELEMENT DECOMPOSITION
4
Patent #:
Issue Dt:
11/28/2000
Application #:
09062219
Filing Dt:
04/17/1998
Title:
MEMORY-SAVING METHOD AND APPARATUS FOR PARTITIONING HIGH FANOUT NETS
5
Patent #:
Issue Dt:
07/10/2001
Application #:
09062246
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR COARSE GLOBAL ROUTING
6
Patent #:
Issue Dt:
05/02/2000
Application #:
09062254
Filing Dt:
04/17/1998
Title:
METHOD FOR I/O DEVICE LAYOUT DURING INTEGRATED CIRCUIT DESIGN
7
Patent #:
Issue Dt:
11/27/2001
Application #:
09062309
Filing Dt:
04/17/1998
Publication #:
Pub Dt:
08/30/2001
Title:
METHOD AND APPARATUS FOR PARALLEL SIMULTANEOUS GLOBAL AND DETAIL ROUTING
8
Patent #:
Issue Dt:
05/08/2001
Application #:
09062310
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR MINIMIZATION OF PROCESS DEFECTS WHILE ROUTING
9
Patent #:
Issue Dt:
07/31/2001
Application #:
09062418
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR PARALLEL ROUTING LOCKING MECHANISM
10
Patent #:
Issue Dt:
06/12/2001
Application #:
09062432
Filing Dt:
04/17/1998
Title:
METHOD AND APPARATUS FOR PARALLEL STEINER TREE ROUTING
11
Patent #:
Issue Dt:
04/27/1999
Application #:
09062606
Filing Dt:
04/17/1998
Title:
BONDING SILICON WAFERS
12
Patent #:
Issue Dt:
05/09/2000
Application #:
09063801
Filing Dt:
04/21/1998
Title:
TEST CIRCUITRY FOR DETERMINING THE DEFECT DENSITY OF A SEMICONDUCTOR PROCESS AS A FUNCTION OF INDIVIDUAL METAL LAYERS
13
Patent #:
Issue Dt:
07/09/2002
Application #:
09064802
Filing Dt:
04/22/1998
Title:
AUTOMATING PHOTOLITHOGRAPHY IN THE FABRICATION OF INTEGRATED CIRCUITS
14
Patent #:
Issue Dt:
01/18/2000
Application #:
09067545
Filing Dt:
04/27/1998
Title:
MULTISTEP TUNGSTEN CVD PROCESS WITH AMORPHIZATION STEP
15
Patent #:
Issue Dt:
03/14/2000
Application #:
09069027
Filing Dt:
04/27/1998
Title:
METAL-ENCAPSULATED POLYSILICON GATE AND INTERCONNECT
16
Patent #:
Issue Dt:
10/16/2001
Application #:
09069215
Filing Dt:
04/29/1998
Title:
IMPROVED COMPLEMENTARY SEMICONDUCTOR DEVICES
17
Patent #:
Issue Dt:
07/06/1999
Application #:
09070188
Filing Dt:
04/30/1998
Title:
ANTIFUSE DEVICE FOR USE ON A FIELD PROGRAMMABLE INTERCONNECT CHIP
18
Patent #:
Issue Dt:
11/02/1999
Application #:
09070387
Filing Dt:
04/30/1998
Title:
ELECTRODEPOSITION APPARATUS FOR COATING WAFERS
19
Patent #:
Issue Dt:
05/11/1999
Application #:
09070671
Filing Dt:
04/30/1998
Title:
SEMICONDUCTOR PACKAGE HAVING CAPACITIVE EXTENSION SPOKES AND METHOD FOR MAKING THE SAME
20
Patent #:
Issue Dt:
05/25/1999
Application #:
09071006
Filing Dt:
05/01/1998
Title:
METHOD FOR MAKING INP HETEROSTRUCTURE DEVICES
21
Patent #:
Issue Dt:
12/04/2001
Application #:
09072248
Filing Dt:
05/04/1998
Title:
LOW THERMAL EXPANSION COMPOSITE COMPRISING BODIES OF NEGATIVE CTE MATERIAL DISPOSED WITHIN A POSITIVE CTE MATRIX
22
Patent #:
Issue Dt:
11/16/1999
Application #:
09072369
Filing Dt:
05/04/1998
Title:
BOND PAD DESIGN FOR INTEGRATED CIRCUITS
23
Patent #:
Issue Dt:
07/04/2000
Application #:
09072566
Filing Dt:
05/05/1998
Title:
METHOD AND APPARATUS FOR SPECIFYING MULTIPLE POWER DOMAINS IN ELECTRONIC CIRCUIT DESIGNS
24
Patent #:
Issue Dt:
12/04/2001
Application #:
09072570
Filing Dt:
05/05/1998
Title:
METHOD AND APPARATUS FOR ZERO SKEW ROUTING FROM A FIXED H TRUNK
25
Patent #:
Issue Dt:
05/23/2000
Application #:
09072705
Filing Dt:
05/05/1998
Title:
NON-LINEAR CIRCUIT ELEMENTS ON INTEGRATED CIRCUITS
26
Patent #:
Issue Dt:
11/30/1999
Application #:
09072915
Filing Dt:
05/04/1998
Title:
SILICON WAFER OR DIE STRENGTH TEST FIXTURE USING HIGH PRESSURE FLUID
27
Patent #:
Issue Dt:
05/02/2000
Application #:
09073279
Filing Dt:
05/06/1998
Title:
PRESSURE CONTROLLED ALIGNMENT FIXTURE
28
Patent #:
Issue Dt:
02/22/2000
Application #:
09073556
Filing Dt:
05/06/1998
Title:
INTEGRATED CIRCUIT HAVING AMORPHOUS SILICIDE LAYER IN CONTACTS AND VIAS AND METHOD OF MANUFACTURE THEREFOR
29
Patent #:
Issue Dt:
06/06/2000
Application #:
09074298
Filing Dt:
05/07/1998
Title:
PROCESS FOR DEPOSITING TITANIUM NITRIDE FILMS
30
Patent #:
Issue Dt:
07/18/2000
Application #:
09074837
Filing Dt:
05/08/1998
Title:
LINEAR CAPACITOR AND PROCESS FOR MAKING SAME
31
Patent #:
Issue Dt:
07/25/2000
Application #:
09075029
Filing Dt:
05/08/1998
Title:
HIGH VOLTAGE TOLERANT THIN FILM TRANSISTOR TRANSISTOR
32
Patent #:
Issue Dt:
09/12/2000
Application #:
09075300
Filing Dt:
05/08/1998
Title:
APPARATUS AND METHOD FOR TESTING A FLIP CHIP INTEGRATED CIRCUIT PACKAGE ADHESIVE LAYER
33
Patent #:
Issue Dt:
12/18/2001
Application #:
09076399
Filing Dt:
05/11/1998
Title:
FORMATION OF INTEGRATED CIRCUIT STRUCTURE USING ONE OR MORE SILICON LAYERS FOR IMPLANTATION AND OUT-DIFFUSION IN FORMATION OF DEFECT-FREE SOURCE/DRAIN REGIONS AND ALSO FOR SUBSEQUENT FORMATION OF SILICON NITRIDE SPACERS
34
Patent #:
Issue Dt:
10/03/2000
Application #:
09076502
Filing Dt:
05/11/1998
Title:
APPARATUS AND PROCESS FOR DEPOSITION OF THIN FILM ON SEMICONDUCTOR SUBSTRATE WHILE INHIBITING PARTICLE FORMATION AND DEPOSITION
35
Patent #:
Issue Dt:
05/30/2000
Application #:
09078093
Filing Dt:
05/13/1998
Title:
APPARATUS AND METHOD FOR SEPARATING A STIFFENER MEMBER FROM A FLIP CHIP INTEGRATED CIRCUIT PACKAGE SUBSTRATE
36
Patent #:
Issue Dt:
12/26/2000
Application #:
09079413
Filing Dt:
05/13/1998
Title:
INDUCTOR WITH COBALT/NICKEL CORE FOR INTEGRATED CIRCUIT STRUCTURE WITH HIGH INDUCTANCE AND HIGH Q-FACTOR,
37
Patent #:
Issue Dt:
12/14/1999
Application #:
09080430
Filing Dt:
05/18/1998
Title:
APPARATUS FOR PROCESSING SILICON DEVICE WITH IMPROVED TEMPERATURE CONTROL
38
Patent #:
Issue Dt:
04/18/2000
Application #:
09080992
Filing Dt:
05/19/1998
Title:
DEVICE AND METHOD FOR POLISHING A SEMICONDUCTOR SUBSTRATE
39
Patent #:
Issue Dt:
06/13/2000
Application #:
09081337
Filing Dt:
05/19/1998
Title:
TECHNIQUE AND APPARATUS FOR EXTERNALLY MONITORING RPM OF SPIN RINSE DRYER
40
Patent #:
Issue Dt:
07/11/2000
Application #:
09081387
Filing Dt:
05/18/1998
Title:
METHOD AND SYSTEM FOR IMPROVING A PLACEMENT OF CELLS USING ENERGETIC PLACEMENT WITH ALTERNATING CONTRACTION AND EXPANSION OPERATIONS
41
Patent #:
Issue Dt:
05/29/2001
Application #:
09081403
Filing Dt:
05/18/1998
Title:
INTEGRATED CIRCUIT STRUCTURE WITH THIN DIELECTRIC BETWEEN AT LEAST LOCAL INTERCONNECT LEVEL AND FIRST METAL INTERCONNECT LEVEL
42
Patent #:
Issue Dt:
05/02/2000
Application #:
09081406
Filing Dt:
05/19/1998
Title:
POLISHING APPARATUS WITH CARRIER HEAD PIVOTING DEVICE
43
Patent #:
Issue Dt:
04/09/2002
Application #:
09081448
Filing Dt:
05/19/1998
Title:
PACKAGING SILICON ON SILICON MULTICHIP MODULES
44
Patent #:
Issue Dt:
10/10/2000
Application #:
09081475
Filing Dt:
05/19/1998
Title:
SIMPLE BICMOS PROCESS FOR CREATION OF LOW TRIGGER VOLTAGE SCR AND ZENER DIODE PAD PROTECTION
45
Patent #:
Issue Dt:
07/04/2000
Application #:
09082162
Filing Dt:
05/20/1998
Title:
METHOD OF PLANARIZING A SURFACE ON A SEMICONDUCTOR WAFER
46
Patent #:
Issue Dt:
03/27/2001
Application #:
09082810
Filing Dt:
05/21/1998
Title:
HIGH RELIABILITY BEARING STRUCTURE
47
Patent #:
Issue Dt:
02/20/2001
Application #:
09082924
Filing Dt:
05/21/1998
Title:
SYSTEM AND METHOD OF MANUFACTURING SEMICUSTOM INTEGRATED CIRCUITS USING RETICLE PRIMITIVES FROM A LIBRARY AND INTERCONNECT RETICLES
48
Patent #:
Issue Dt:
02/15/2000
Application #:
09083072
Filing Dt:
05/21/1998
Title:
METHOD OF ELIMINATING AGGLOMERATE PARTICLES IN A POLISHING SLURRY
49
Patent #:
Issue Dt:
12/07/1999
Application #:
09083168
Filing Dt:
05/22/1998
Title:
ENERGY-SENSITIVE RESIST MATERIAL AND A PROCESS FOR DEVICE FABRICATION USING AN ENERGY-SENSITIVE RESIST MATERIAL
50
Patent #:
Issue Dt:
02/03/2004
Application #:
09085143
Filing Dt:
05/26/1998
Title:
UTILIZING A TECHNOLOGY-INDEPENDENT SYSTEM DESCRIPTION INCORPORATING A METAL LAYER DEPENDENT ATTRIBUTE
51
Patent #:
Issue Dt:
05/28/2002
Application #:
09085717
Filing Dt:
05/28/1998
Title:
DISTRIBUTED COMPUTER AIDED DESIGN SYSTEM AND METHOD
52
Patent #:
Issue Dt:
09/07/1999
Application #:
09085913
Filing Dt:
05/28/1998
Title:
INTEGRATED CIRCUITS WITH TUB-TIES
53
Patent #:
Issue Dt:
05/09/2000
Application #:
09086252
Filing Dt:
05/28/1998
Title:
MOS TRANSISTORS WITH IMPROVED GATE DIELECTRICS
54
Patent #:
Issue Dt:
04/03/2001
Application #:
09088801
Filing Dt:
06/02/1998
Title:
ELECTRON BEAM FAULT DETECTION OF SEMICONDUCTOR DEVICES
55
Patent #:
Issue Dt:
08/01/2000
Application #:
09088852
Filing Dt:
06/02/1998
Title:
METHODS AND APPARATUS FOR INCREASING METAL DENSITY IN AN INTEGRATED CIRCUIT WHILE ALSO REDUCING PARASITIC CAPACITANCE
56
Patent #:
Issue Dt:
10/10/2000
Application #:
09089461
Filing Dt:
06/02/1998
Title:
LASER FAULT CORRECTION OF SEMICONDUCTOR DEVICES
57
Patent #:
Issue Dt:
05/01/2001
Application #:
09089703
Filing Dt:
06/03/1998
Title:
FLIP-CHIP INTEGRATED CIRCUIT ROUTING TO I/O DEVICES
58
Patent #:
Issue Dt:
07/18/2000
Application #:
09089792
Filing Dt:
06/03/1998
Title:
DEVICE AND METHOD OF DECREASING CIRCULAR DEFECTS AND CHARGE BUILDUP IN INTEGRATED CIRCUIT FABRICATION
59
Patent #:
Issue Dt:
07/25/2000
Application #:
09090295
Filing Dt:
06/04/1998
Title:
DIELECTRIC MATERIALS OF AMORPHOUS COMPOSITIONS OF TI-O2 DOPED WITH RARE EARTH ELEMENTS AND DEVICES EMPLOYING SAME
60
Patent #:
Issue Dt:
01/03/2006
Application #:
09092158
Filing Dt:
06/05/1998
Title:
A METHOD OF FABRICATING A CONTACT WITH A POST CONTACT PLUG ANNEAL
61
Patent #:
Issue Dt:
10/05/1999
Application #:
09093557
Filing Dt:
06/08/1998
Title:
ARTICLE COMPRISING AN OXIDE LAYER ON A GAAS-BASED SEMICONDUCTOR BODY, AND METHOD OF MAKING THE ARTICLE
62
Patent #:
Issue Dt:
03/13/2001
Application #:
09094920
Filing Dt:
06/15/1998
Title:
METHOD FOR FABRICATING SEMICONDUCTOR DEVICES
63
Patent #:
Issue Dt:
05/14/2002
Application #:
09095468
Filing Dt:
06/10/1998
Title:
SINGLE CRYSTAL SILICON ON POLYCRYSTALLINE SILLICON INTEGRATED CIRCUITS
64
Patent #:
Issue Dt:
11/27/2001
Application #:
09096998
Filing Dt:
06/13/1998
Title:
PASSIVATED COPPER SURFACES
65
Patent #:
Issue Dt:
02/06/2001
Application #:
09097081
Filing Dt:
06/12/1998
Title:
IMPROVED PERFORMANCE MONITORING CIRCUITRY FOR INTEGRATED CIRCUITS
66
Patent #:
Issue Dt:
07/03/2001
Application #:
09097488
Filing Dt:
06/15/1998
Title:
HYBRID ALGORITHM FOR TEST POINT SELECTION FOR SCAN-BASED BIST
67
Patent #:
Issue Dt:
11/07/2000
Application #:
09097882
Filing Dt:
06/15/1998
Title:
ELECTROSTATIC PROTECTED SUBSTRATE
68
Patent #:
Issue Dt:
12/14/1999
Application #:
09097883
Filing Dt:
06/15/1998
Title:
THERMALLY ENHANCED TAPE BALL GRID ARRAY PACKAGE
69
Patent #:
Issue Dt:
11/14/2000
Application #:
09098019
Filing Dt:
06/15/1998
Title:
MODIFIED MULTIPLE LAYER METAL LINE STRUCTURE FOR USE WITH TUNGSTEN- FILLED VIAS IN INTEGRATED CIRCUIT STRUCTURES
70
Patent #:
Issue Dt:
03/14/2000
Application #:
09098032
Filing Dt:
06/15/1998
Title:
PROCESS FOR FORMING VIAS, AND TRENCHES FOR METAL LINES, IN MULTIPLE DIELECTRIC LAYERS OF INTEGRATED CIRCUIT STRUCTURE
71
Patent #:
Issue Dt:
10/03/2000
Application #:
09098172
Filing Dt:
06/16/1998
Title:
LOW VOLTAGE SCREEN FOR IMPROVING THE FAULT COVERAGE OF INTEGRATED CIRCUIT PRODUCTION TEST PROGRAMS
72
Patent #:
Issue Dt:
05/09/2000
Application #:
09098635
Filing Dt:
06/16/1998
Title:
AN IMPROVED METHOD FOR SHALLOW TRENCH ISOLATIONS WITH CHEMICAL- MECHANICAL POLISHING
73
Patent #:
Issue Dt:
10/16/2001
Application #:
09099287
Filing Dt:
06/18/1998
Title:
CLOCK DISTRIBUTION NETWORK PLANNING AND METHOD THEREFOR
74
Patent #:
Issue Dt:
09/19/2000
Application #:
09099715
Filing Dt:
06/18/1998
Title:
PROCESS FOR FABRICATING INTEGRATED CIRCUITS WITH DUAL GATE DEVICES THEREIN
75
Patent #:
Issue Dt:
06/13/2000
Application #:
09099827
Filing Dt:
06/18/1998
Title:
INTEGRATED CIRCUIT DEVICE IN WHICH GATE OXIDE THICKNESS IS SELECTED TO CONTROL PLASMA DAMAGE DURING DEVICE FABRICATION
76
Patent #:
Issue Dt:
05/16/2000
Application #:
09100665
Filing Dt:
06/19/1998
Title:
DEVICE AND METHOD FOR REMOVING HEATSPREADER FROM AN INTEGRATED CIRCUIT PACKAGE
77
Patent #:
Issue Dt:
08/29/2000
Application #:
09103291
Filing Dt:
06/23/1998
Title:
ELECTROPLATING FIXTURE FOR HIGH DENSITY SUBSTRATES
78
Patent #:
Issue Dt:
11/09/1999
Application #:
09104838
Filing Dt:
06/25/1998
Title:
PROCESS FOR USING A REMOVEABLE PLATING BUS LAYER FOR HIGH DENSITY SUBSTRATES
79
Patent #:
Issue Dt:
10/26/1999
Application #:
09105546
Filing Dt:
06/26/1998
Title:
OFF-AXIS ILLUMINATOR LENS MASK FOR PHOTOLITHOGRAPHIC PROJECTION SYSTEM
80
Patent #:
Issue Dt:
06/13/2000
Application #:
09105712
Filing Dt:
06/26/1998
Title:
OPTICAL MONITORING SYSTEM FOR III-V WAFER PROCESSING
81
Patent #:
Issue Dt:
11/12/2002
Application #:
09106890
Filing Dt:
06/29/1998
Publication #:
Pub Dt:
12/06/2001
Title:
AN INTEGRATED CIRCUIT DESIGN INCORPORATING A POWER MESH
82
Patent #:
Issue Dt:
06/05/2001
Application #:
09107342
Filing Dt:
06/30/1998
Title:
METHOD AND APPARATUS FOR DETECTING A POLISHING ENDPOINT BASED UPON INFRARED SIGNALS
83
Patent #:
Issue Dt:
11/16/1999
Application #:
09107767
Filing Dt:
06/30/1998
Title:
LOW THRESHOLD VOLTAGE MOS TRANSISTOR AND METHOD OF MANUFACTURE
84
Patent #:
Issue Dt:
07/31/2001
Application #:
09108091
Filing Dt:
06/30/1998
Title:
METHOD AND APPARATUS FOR DETECTING AN ION-IMPLANTED POLISHING ENDPOINT LAYER WITHIN A SEMICONDUCTOR WAFER
85
Patent #:
Issue Dt:
01/16/2001
Application #:
09108092
Filing Dt:
06/30/1998
Title:
A WAFER SCALE INTEGRATED CIRCUIT SYSTEM
86
Patent #:
Issue Dt:
09/04/2001
Application #:
09108848
Filing Dt:
07/01/1998
Title:
SYSTEM AND METHOD OF MANUFACTURING SEMICUSTOM RETICLES USING RETICLE PRIMITIVES
87
Patent #:
Issue Dt:
06/06/2000
Application #:
09109331
Filing Dt:
06/30/1998
Title:
ENDPOINT DETECTION METHOD AND APPARATUS WHICH UTILIZE AN ENDPOINT POLISHING LAYER OF CATALYST MATERIAL
88
Patent #:
Issue Dt:
06/20/2000
Application #:
09109335
Filing Dt:
06/30/1998
Title:
METHOD AND APPARATUS FOR DETECTING A POLISHING ENDPOINT BASED UPON HEAT CONDUCTED THROUGH A SEMICONDUCTOR WAFER
89
Patent #:
Issue Dt:
12/19/2000
Application #:
09109963
Filing Dt:
07/02/1998
Title:
MICROMAGNETIC DEVICE FOR DATA TRANSMISSION APPLICATIONS AND METHOD OF MANUFACTURE THEREFOR
90
Patent #:
Issue Dt:
09/05/2000
Application #:
09111271
Filing Dt:
07/06/1998
Title:
GENERATING NON-PLANAR TOPOLOGY ON THE SURFACE OF PLANAR AND NEAR-PLANAR SUBSTRATES
91
Patent #:
Issue Dt:
09/04/2001
Application #:
09111529
Filing Dt:
07/08/1998
Title:
APPARATUS FOR DETECTTING AN ENDPOINT POLISHING LAYER OF A SEMICONDUCTOR WAFER HAVING A WAFER CARRIER WITH INDEPENDENT CONCENTRIC SUB-CARRIERS AND ASSOCIATED METHOD
92
Patent #:
Issue Dt:
03/28/2000
Application #:
09111534
Filing Dt:
07/08/1998
Title:
ALIGNMENT TECHNIQUES FOR PHOTOLITHOGRAPHY UTILIZING MULTIPLE PHOTORESIST LAYERS
93
Patent #:
Issue Dt:
06/13/2000
Application #:
09112222
Filing Dt:
07/08/1998
Title:
METHOD AND APPARATUS FOR DETECTING AN ENDPOINT POLISHING LAYER BY TRANSMITTING INFRARED LIGHT SIGNALS THROUGH A SEMICONDUCTOR WAFER
94
Patent #:
Issue Dt:
05/23/2000
Application #:
09112403
Filing Dt:
07/08/1998
Title:
IN-SITU CHEMICAL-MECHANICAL POLISHING SLURRY FORMULATION FOR COMPENSATION OF POLISH PAD DEGRADATION
95
Patent #:
Issue Dt:
11/14/2000
Application #:
09113583
Filing Dt:
07/10/1998
Title:
SHALLOW TRENCH ISOLATION
96
Patent #:
Issue Dt:
04/16/2002
Application #:
09113594
Filing Dt:
07/10/1998
Title:
SONIC ASSISTED STRENGTHENING OF GATE OXIDES
97
Patent #:
Issue Dt:
03/30/2004
Application #:
09113995
Filing Dt:
07/10/1998
Title:
PLACEMENT AND ROUTING OF A BUFFER CIRCUIT FOR BUFFERING A SIGNAL EXTERNAL TO THE INTEGRATED CIRCUIT BEARING THE SINGLE CELL
98
Patent #:
Issue Dt:
10/10/2000
Application #:
09114345
Filing Dt:
07/13/1998
Title:
IMPROVED ENHANCED LAMINATION PROCESS BETWEEN HEATSPREADER TO PRESSURE SENSITIVE ADHESIVE (PSA) INTERFACE AS A STEP IN THE SEMICONDUCTOR ASSEMBLY PROCESS
99
Patent #:
Issue Dt:
05/29/2001
Application #:
09115464
Filing Dt:
07/14/1998
Title:
POLY ROUTING FOR CHIP INTERCONNECTS WITH MINIMAL IMPACT ON CHIP PERFORMANCE
100
Patent #:
Issue Dt:
04/18/2000
Application #:
09116158
Filing Dt:
07/16/1998
Title:
ELLICIENT THREE DIMENSIONAL EXTRACTION
Assignors
1
Exec Dt:
01/24/2018
2
Exec Dt:
01/24/2018
3
Exec Dt:
01/24/2018
Assignee
1
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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