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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 11 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
Issue Dt:
01/30/2001
Application #:
09118661
Filing Dt:
07/16/1998
Title:
METAL LAYER ASSIGNMENT
2
Patent #:
Issue Dt:
11/28/2000
Application #:
09120148
Filing Dt:
07/21/1998
Title:
RECESSED FLIP-CHIP PACKAGE
3
Patent #:
Issue Dt:
12/19/2000
Application #:
09120396
Filing Dt:
07/22/1998
Title:
BUILT-IN SELF-TEST CIRCUIT FOR READ CHANNEL DEVICE
4
Patent #:
Issue Dt:
06/25/2002
Application #:
09120617
Filing Dt:
07/22/1998
Title:
WIRE ROUTING OPTIMIZATION
5
Patent #:
Issue Dt:
04/18/2000
Application #:
09121266
Filing Dt:
07/23/1998
Title:
PROCESS FOR FABRICATING A LITHOGRAPHIC MASK
6
Patent #:
Issue Dt:
12/05/2000
Application #:
09121283
Filing Dt:
07/22/1998
Title:
ISOLATION TRENCH IN SEMICONDUCTOR SUBSTRATE WITH NITROGEN-CONTAINING BARRIER REGION, AND PROCESS FOR FORMING SAME
7
Patent #:
Issue Dt:
01/11/2000
Application #:
09121284
Filing Dt:
07/23/1998
Title:
APPARATUS AND METHOD FOR INTEGRATED CIRCUIT WITH VARIABLE CAPACITOR
8
Patent #:
Issue Dt:
12/05/2000
Application #:
09122335
Filing Dt:
07/24/1998
Title:
LASER MARKING OF SEMICONDUCTOR WAFER SUBSTRATE WHILE INHIBITING ADHERENCE TO SUBSTRATE SURFACE OF PARTICLES GENERATED DURING LASER MARKING
9
Patent #:
Issue Dt:
08/10/1999
Application #:
09123370
Filing Dt:
07/27/1998
Title:
TEXT FIXTURE RETAINER FOR AN INTEGRATED CIRCUIT PACKAGE
10
Patent #:
Issue Dt:
01/02/2001
Application #:
09123380
Filing Dt:
07/27/1998
Title:
METHOD FOR OPTIMIZING TEST FIXTURES TO MINIMIZE VECTOR LOAD TIME FOR AUTOMATED TEST EQUIPMENT
11
Patent #:
Issue Dt:
11/28/2000
Application #:
09126013
Filing Dt:
07/29/1998
Title:
SYSTEM AND METHOD FOR SIMULATING ELECTRONIC CIRCUITS
12
Patent #:
Issue Dt:
03/14/2000
Application #:
09126032
Filing Dt:
07/29/1998
Title:
ON-CHIP CAPACITOR STRUCTURE
13
Patent #:
Issue Dt:
07/11/2000
Application #:
09127373
Filing Dt:
07/31/1998
Title:
SILICON GERMANIUM HETEROSTRUCTURE BIPOLAR TRANSISTOR WITH INDIUM DOPED BASE
14
Patent #:
Issue Dt:
06/05/2001
Application #:
09127486
Filing Dt:
07/31/1998
Title:
UNIVERSAL I/O PAD STRUCTURE FOR IN-LINE OR STAGGERED WIRE BONDING OR ARRAYED FLIP-CHIP ASSEMBLY
15
Patent #:
Issue Dt:
08/17/1999
Application #:
09127707
Filing Dt:
07/31/1998
Title:
SYSTEM AND METHOD FOR EMPIRICALLY DETERMINING SHRINKAGE STRESSES IN A MOLDED PACKAGE AND POWER MODULE EMPLOYING THE SAME
16
Patent #:
Issue Dt:
07/25/2000
Application #:
09128041
Filing Dt:
08/03/1998
Title:
SPEED-SIGNALING TESTING FOR INTEGRATED CIRCUITS
17
Patent #:
Issue Dt:
10/24/2000
Application #:
09131860
Filing Dt:
08/10/1998
Title:
PROCESS FOR DEVICE FABRICATION USING A HIGH-ENERGY BORON IMPLANT
18
Patent #:
Issue Dt:
06/27/2000
Application #:
09131921
Filing Dt:
08/10/1998
Title:
METHOD OF DETECTING A POLISHING ENDPOINT LAYER OF A SEMICONDUCTOR WAFER WHICH INCLUDES A NON-REACTIVE REPORTING SPECIE
19
Patent #:
Issue Dt:
02/22/2000
Application #:
09133606
Filing Dt:
08/13/1998
Title:
ELECTRONIC ASSEMBLY HAVING IMPROVED RESISTANCE TO DELAMINATION
20
Patent #:
Issue Dt:
01/18/2000
Application #:
09135260
Filing Dt:
08/17/1998
Title:
METHOD OF FORMING PLANARIZED LAYERS IN AN INTEGRATED CIRCUIT
21
Patent #:
Issue Dt:
01/30/2001
Application #:
09135969
Filing Dt:
08/18/1998
Title:
ARRANGEMENT FOR REDUCING BENDING STRESS IN AN ELECTRONICS PACKAGE
22
Patent #:
Issue Dt:
06/27/2000
Application #:
09136095
Filing Dt:
08/18/1998
Title:
PROCESS OF CHEMICAL-MECHANICAL POLISHING AND MANUFACTURING AN INTEGRATED CIRCUIT
23
Patent #:
Issue Dt:
04/10/2001
Application #:
09137920
Filing Dt:
08/20/1998
Title:
THIN FILM TRANSISTORS
24
Patent #:
Issue Dt:
04/04/2006
Application #:
09138146
Filing Dt:
08/21/1998
Title:
INTEGRATED CIRCUIT CARRIER AND METHOD OF MANUFACTURING AND INTERGRATED CIRCUIT
25
Patent #:
Issue Dt:
11/20/2001
Application #:
09138701
Filing Dt:
08/24/1998
Title:
DEVICE AND METHOD FOR PARALLEL SIMULATION
26
Patent #:
Issue Dt:
02/05/2002
Application #:
09138702
Filing Dt:
08/24/1998
Title:
DEVICE AND METHOD FOR PARALLEL SIMULATION TASK GENERATION AND DISTRIBUTION
27
Patent #:
Issue Dt:
09/19/2000
Application #:
09138741
Filing Dt:
08/24/1998
Title:
METHOD FOR CONTROLLED IMPLANTATION OF ELEMENTS INTO THE SURFACE OR NEAR SURFACE OF A SUBSTRATE
28
Patent #:
Issue Dt:
02/19/2002
Application #:
09140270
Filing Dt:
08/26/1998
Title:
CAPACITOR IN AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
29
Patent #:
Issue Dt:
06/27/2000
Application #:
09140275
Filing Dt:
08/26/1998
Title:
METHOD FOR MAKING DUAL-POLYSILICON STRUCTURES IN INTEGRATED CIRCUITS
30
Patent #:
Issue Dt:
04/02/2002
Application #:
09140276
Filing Dt:
08/26/1998
Publication #:
Pub Dt:
11/29/2001
Title:
METHOD FOR FORMING DUAL-POLYSILICON STRUCTURES USING A BUILT- IN STOP LAYER
31
Patent #:
Issue Dt:
10/10/2000
Application #:
09140564
Filing Dt:
08/27/1998
Title:
SYSTEM AND METHOD FOR TESTING OF EMBEDDED PROCESSOR
32
Patent #:
Issue Dt:
10/02/2001
Application #:
09143037
Filing Dt:
08/28/1998
Title:
PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION HAVING COPPER INTERCONNECTS
33
Patent #:
Issue Dt:
07/17/2001
Application #:
09143083
Filing Dt:
08/28/1998
Title:
BACKSIDE FAILURE ANALYSIS CAPABLE INTEGRATED CIRCUIT PACKAGING
34
Patent #:
Issue Dt:
02/22/2000
Application #:
09143274
Filing Dt:
08/28/1998
Title:
PROCESS FOR FABRICATING VERTICAL TRANSISTORS
35
Patent #:
Issue Dt:
02/03/2004
Application #:
09144799
Filing Dt:
09/01/1998
Title:
APPARATUS AND METHOD FOR REDUCED-ORDER MODELING OF TIME-VARYING SYSTEMS AND COMPUTER STORAGE MEDIUM CONTAINING THE SAME
36
Patent #:
Issue Dt:
06/12/2001
Application #:
09146418
Filing Dt:
09/03/1998
Title:
SYSTEM AND METHOD FOR FORMING A UNIFORM THIN GATE OXIDE LAYER
37
Patent #:
Issue Dt:
01/22/2002
Application #:
09148028
Filing Dt:
09/03/1998
Title:
METHOD AND APPARATUS FOR CHEMICAL-MECHANICAL POLISHING
38
Patent #:
Issue Dt:
01/16/2001
Application #:
09149803
Filing Dt:
09/08/1998
Title:
INTERPOSER FOR RECESSED FLIP-CHIP PACKAGE
39
Patent #:
Issue Dt:
12/12/2000
Application #:
09149804
Filing Dt:
09/08/1998
Title:
TRANSLATOR FOR RECESSED FLIP-CHIP PACKAGE
40
Patent #:
Issue Dt:
04/24/2001
Application #:
09150076
Filing Dt:
09/09/1998
Title:
ON-CHIP MISALIGNMENT INDICATION
41
Patent #:
Issue Dt:
06/19/2001
Application #:
09150220
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR REMOVING PARTICLES FROM A SEMICONDUCTOR WAFER
42
Patent #:
Issue Dt:
04/10/2001
Application #:
09150529
Filing Dt:
09/10/1998
Title:
DEVICE AND METHOD FOR FORMING SEMICONDUCTOR INTERCONNECTIONS IN AN INTEGRATED CIRCUIT SUBSTRATE
43
Patent #:
Issue Dt:
11/21/2000
Application #:
09151077
Filing Dt:
09/10/1998
Title:
DIFFERENTIAL TEMPERATURE CONTROL IN CHEMICAL MECHANICAL POLISHING PROCESSES
44
Patent #:
Issue Dt:
04/09/2002
Application #:
09151228
Filing Dt:
09/10/1998
Title:
SIMULATION FORMAT CREATION SYSTEM AND METHOD
45
Patent #:
Issue Dt:
08/07/2001
Application #:
09151900
Filing Dt:
09/11/1998
Title:
EXTRACTOR AND SCHEMATIC VIEWER FOR A DESIGN REPRESENTATION, AND ASSOCIATED METHOD
46
Patent #:
Issue Dt:
06/05/2001
Application #:
09152185
Filing Dt:
09/12/1998
Title:
ARTICLE COMPRISING A MULTI-PORT VARIABLE CAPACITOR
47
Patent #:
Issue Dt:
08/08/2000
Application #:
09152189
Filing Dt:
09/12/1998
Title:
ARTICLE COMPRISING AN INDUCTOR
48
Patent #:
Issue Dt:
08/15/2000
Application #:
09153522
Filing Dt:
09/15/1998
Title:
MANUFACTURE OF MOSFET DEVICES
49
Patent #:
Issue Dt:
12/17/2002
Application #:
09156719
Filing Dt:
09/18/1998
Title:
METHOD OF MAKING AN ARTICLE COMPRISING AN OXIDE LAYER ON A GAAS-BASED SEMICONDUCTOR BODY
50
Patent #:
Issue Dt:
07/11/2000
Application #:
09162247
Filing Dt:
09/28/1998
Title:
BOND PAD FOR A FLIP-CHIP PACKAGE, AND METHOD OF FORMING THE SAME
51
Patent #:
Issue Dt:
04/03/2001
Application #:
09162407
Filing Dt:
09/29/1998
Title:
SEMICONDUCTOR DEVICE WITH A [AIR OF TRANSISTORS HAVING DUAL WORK FUNCTION GATE ELECTRODES
52
Patent #:
Issue Dt:
01/23/2001
Application #:
09162542
Filing Dt:
09/29/1998
Title:
METHOD FOR FORMING A NITRIDE LAYER SUITABLE FOR USE IN ADVANCED GATE DIELECTRIC MATERIALS
53
Patent #:
Issue Dt:
05/30/2000
Application #:
09163623
Filing Dt:
09/30/1998
Title:
REDUCTION OF SILICON DEFECT INDUCED FAILURES AS A RESULT OF IMPLANTS IN CMOS AND OTHER INTEGRATED CIRCUITS
54
Patent #:
Issue Dt:
09/02/2003
Application #:
09164069
Filing Dt:
09/30/1998
Title:
METHOD FOR COMPOSING A DIELECTRIC LAYER WITHIN AN INTERCONNECT STRUCTURE OF A MULTILAYER SEMICONDUCTOR DEVICE
55
Patent #:
Issue Dt:
04/04/2000
Application #:
09164283
Filing Dt:
10/01/1998
Title:
METHOD FOR REMOVING ETCHING RESIDUES AND CONTAMINANTS
56
Patent #:
Issue Dt:
12/05/2000
Application #:
09166832
Filing Dt:
10/05/1998
Title:
SEMICONDUCTOR DEVICE HAVING ALUMINUM CONTACTS OR VIAS AND METHOD OF MANUFACTURE THEREFOR
57
Patent #:
Issue Dt:
04/10/2001
Application #:
09168409
Filing Dt:
10/08/1998
Title:
METHOD AND SYSTEM FOR TESTING MULTIPORT MEMORIES
58
Patent #:
Issue Dt:
03/28/2000
Application #:
09168638
Filing Dt:
10/08/1998
Title:
METHOD AND APPARATUS FOR DETECTING A SOLDER BRIDGE IN A BALL GRID ARRAY
59
Patent #:
Issue Dt:
09/21/1999
Application #:
09169117
Filing Dt:
10/08/1998
Title:
METHOD AND APPARATUS FOR DETECTING A SOLDER BRIDGE IN A BALL GRID ARRAY
60
Patent #:
Issue Dt:
11/13/2001
Application #:
09170351
Filing Dt:
10/13/1998
Title:
SYSTEM AND METHOD FOR DETECTING FAULTS IN COMPUTER MEMORIES USING A LOOK UP TABLE
61
Patent #:
Issue Dt:
05/28/2002
Application #:
09170353
Filing Dt:
10/13/1998
Publication #:
Pub Dt:
02/14/2002
Title:
BUILT-IN-SELF-TEST AND SELF-REPAIR METHODS AND DEVICES FOR COMPUTER MEMORIES COMPRISING A RECONFIGURATION MEMORY DEVICE
62
Patent #:
Issue Dt:
05/08/2001
Application #:
09172456
Filing Dt:
10/14/1998
Title:
ETCH ENDPOINT DETECTION
63
Patent #:
Issue Dt:
10/10/2000
Application #:
09172467
Filing Dt:
10/14/1998
Title:
FLIP CHIP METALLIZATION
64
Patent #:
Issue Dt:
08/29/2000
Application #:
09173502
Filing Dt:
10/16/1998
Title:
ARTICLE COMPRISING MOLDED CIRCUIT
65
Patent #:
Issue Dt:
04/02/2002
Application #:
09174503
Filing Dt:
10/16/1998
Title:
PROCESS FOR FORMING INTEGRATED STRUCTURES USING THREE DIMENSIONAL PRINTING TECHNIQUES
66
Patent #:
Issue Dt:
03/13/2001
Application #:
09177335
Filing Dt:
10/22/1998
Title:
METHOD AND APPARATUS FOR DETECTING A PLANARIZED OUTER LAYER OF A SEMICONDUCTOR WAFER WITH A CONFOCAL OPTICAL SYSTEM
67
Patent #:
Issue Dt:
04/17/2001
Application #:
09178720
Filing Dt:
10/26/1998
Title:
METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT USING A SCANNING SYSTEM AND A SCANNING SYSTEM
68
Patent #:
Issue Dt:
04/09/2002
Application #:
09182543
Filing Dt:
10/29/1998
Title:
METHOD AND APARATUS FOR PARTITIONING LONG SCAN CHAINS IN SCAN BASED BIST ARCHITECHTURE
69
Patent #:
Issue Dt:
01/16/2001
Application #:
09183292
Filing Dt:
10/30/1998
Title:
OFF-GRID METAL LAYER UTILIZATION
70
Patent #:
Issue Dt:
08/14/2001
Application #:
09183637
Filing Dt:
10/30/1998
Title:
INTEGRATED CIRCUIT DESIGN WITH DELAYED CELL SELECTION
71
Patent #:
Issue Dt:
11/06/2001
Application #:
09187505
Filing Dt:
11/06/1998
Title:
QUADRATURE SOLUTIONS FOR 3D CAPACITANCE EXTRACTION
72
Patent #:
Issue Dt:
10/12/1999
Application #:
09187885
Filing Dt:
11/06/1998
Title:
ARTICLE COMPRISING FINE-GRAINED SOLDER COMPOSITIONS WITH DISPERSOID PARTICLES
73
Patent #:
Issue Dt:
01/18/2000
Application #:
09190351
Filing Dt:
11/12/1998
Title:
PROCESS FOR DEVICE FABRICATION USING A VARIABLE TRANSMISSION APERTURE
74
Patent #:
Issue Dt:
09/12/2000
Application #:
09193832
Filing Dt:
11/17/1998
Title:
HEATSPREADER FOR A FLIP CHIP DEVICE, AND METHOD FOR CONNECTING THE HEATSPREADER
75
Patent #:
Issue Dt:
11/21/2000
Application #:
09196486
Filing Dt:
11/19/1998
Title:
ARTICLE COMPRISING FLUORINATED AMORPHOUS CARBON AND METHOD FOR FABRICATING ARTICLE
76
Patent #:
Issue Dt:
01/29/2002
Application #:
09197074
Filing Dt:
11/20/1998
Title:
KINETICALLY CONTROLLED SOLDER BONDING
77
Patent #:
Issue Dt:
06/12/2001
Application #:
09197351
Filing Dt:
11/20/1998
Title:
APPARATUS FOR HOLDING AND ALIGNING A SCANNING ELECTRON MICROSCOPE SAMPLE
78
Patent #:
Issue Dt:
11/14/2000
Application #:
09197412
Filing Dt:
11/21/1998
Title:
DETECTING TRACE LEVELS OF COPPER
79
Patent #:
Issue Dt:
08/29/2000
Application #:
09197833
Filing Dt:
11/23/1998
Title:
PROCESS FOR MAKING COMPOUND FILMS
80
Patent #:
Issue Dt:
12/26/2000
Application #:
09197977
Filing Dt:
11/23/1998
Title:
ARRANGEMENT FOR FAULT DETECTION IN CIRCUIT INTERCONNECTIONS
81
Patent #:
Issue Dt:
05/29/2001
Application #:
09198208
Filing Dt:
11/23/1998
Title:
CONSISTENT ALIGNMENT MARK PROFILES ON SEMICONDUCTOR WAFERS USING PVD SHADOWING
82
Patent #:
Issue Dt:
10/09/2001
Application #:
09199018
Filing Dt:
11/24/1998
Title:
INSERTION OF TEST POINTS IN RTL DESIGNS
83
Patent #:
Issue Dt:
11/21/2000
Application #:
09204002
Filing Dt:
12/01/1998
Title:
METHOD OF MAKING AN ORGANIC THIN FILM TRANSISTOR AND ARTICLE MADE BY THE METHOD
84
Patent #:
Issue Dt:
01/16/2001
Application #:
09204767
Filing Dt:
12/03/1998
Title:
APPARATUS AND METHOD FOR DETECTING AN ENDPOINT OF AN ETCHING PROCESS BY TRANSMITTING INFRARED LIGHT SIGNALS THROUGH A SEMICONDUCTOR WAFER
85
Patent #:
Issue Dt:
09/19/2000
Application #:
09204813
Filing Dt:
12/03/1998
Title:
APPARATUS AND METHOD FOR BLOCKING THE DEPOSITION OF OXIDE ON A WAFER
86
Patent #:
Issue Dt:
09/05/2000
Application #:
09204815
Filing Dt:
12/03/1998
Title:
METHOD FOR FORMING AN ION IMPLANTED ELECTROSTATIC CHUCK
87
Patent #:
Issue Dt:
04/30/2002
Application #:
09205413
Filing Dt:
12/02/1998
Title:
LOCOS ISOLATION PROCESS USING A LAYERED PAD NITRIDE AND DRY FIELD OXIDATION STACK AND SEMICONDUCTOR DEVICE EMPLOYING THE SAME
88
Patent #:
Issue Dt:
10/31/2000
Application #:
09205414
Filing Dt:
12/02/1998
Title:
PROCESS FOR FORMING METAL OXIDE SEMICONDUCTORS INCLUDING AN IN SITU FURNACE GATE STACK WITH VARYING SILICON NITRIDE DEPOSITION RATE
89
Patent #:
Issue Dt:
11/06/2001
Application #:
09205840
Filing Dt:
12/04/1998
Title:
ARTICLE COMPRISING FLUORINATED DIAMOND-LIKE CARBON AND METHOD FOR FABRICATING ARTICLE
90
Patent #:
Issue Dt:
10/23/2001
Application #:
09207191
Filing Dt:
12/08/1998
Title:
FILE DRIVEN MASK INSERTION FOR AUTOMATIC TEST EQUIPMENT TEST PATTERN GENERATION
91
Patent #:
Issue Dt:
11/07/2000
Application #:
09207395
Filing Dt:
12/08/1998
Title:
NOVEL WELL FORMATION FOR CMOS DEVICES INTEGRATED CIRCUIT STRUCTURES
92
Patent #:
Issue Dt:
04/09/2002
Application #:
09207878
Filing Dt:
12/08/1998
Title:
MODIFIED DESIGN REPRESENTATION FOR FAST FAULT SIMULATION OF AN INTEGRATED CIRCUIT
93
Patent #:
Issue Dt:
09/19/2000
Application #:
09209704
Filing Dt:
12/11/1998
Title:
APPARATUS AND METHOD OF DETECTING A POLISHING ENDPOINT LAYER OF A SEMICONDUCTOR WAFER WHICH INCLUDES A METALLIC REPORTING SUBSTANCE
94
Patent #:
Issue Dt:
01/15/2002
Application #:
09209787
Filing Dt:
12/11/1998
Title:
TUNGSTEN SILICIDE NITRIDE AS AN ELECTRODE FOR TANTALUM PENTOXIDE DEVICES
95
Patent #:
Issue Dt:
10/16/2001
Application #:
09209855
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR SCRIBING A CODE IN AN INACTIVE OUTER CLEAR OUT AREA OF A SEMICONDUCTOR WAFER
96
Patent #:
Issue Dt:
09/11/2001
Application #:
09210184
Filing Dt:
12/11/1998
Publication #:
Pub Dt:
05/24/2001
Title:
METHOD AND APPARATUS FOR REMOVING RESIDUAL MATERIAL FROM AN ALIGNMENT MARK OF A SEMICONDUCTOR WAFER
97
Patent #:
Issue Dt:
01/02/2001
Application #:
09211024
Filing Dt:
12/14/1998
Title:
SUBSONIC TO SUPERSONIC AND ULTRASONIC CONDITIONING OF A POLISHING PAD IN A CHEMICAL MECHANICAL POLISHING APPARATUS
98
Patent #:
Issue Dt:
01/01/2002
Application #:
09211481
Filing Dt:
12/14/1998
Title:
METHOD AND SYSTEM FOR ANALYZING WAFER PROCESSING ORDER
99
Patent #:
Issue Dt:
07/18/2000
Application #:
09211922
Filing Dt:
12/15/1998
Title:
METHOD FOR COMPOSING A THERMALLY CONDUCTIVE THIN FILM HAVING A LOW DIELECTRIC PROPERTY
100
Patent #:
Issue Dt:
02/27/2001
Application #:
09212228
Filing Dt:
12/16/1998
Title:
DEEP SUB-MICRON METAL ETCH WITH IN-SITU HARD MASK ETCH
Assignors
1
Exec Dt:
01/24/2018
2
Exec Dt:
01/24/2018
3
Exec Dt:
01/24/2018
Assignee
1
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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