|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09212315
|
Filing Dt:
|
12/15/1998
|
|
Title:
|
IMPROVED DUAL GATE OXIDE PROCESS FOR DEEP SUBMICRON ICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09212366
|
Filing Dt:
|
12/15/1998
|
|
Title:
|
COPPER CONTAMINATION CONTROL OF IN-LINE PROBE INSTRUMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09212450
|
Filing Dt:
|
12/16/1998
|
|
Title:
|
TUNGSTEN LOCAL INTERCONNECT FOR SILICON INTEGRATED CIRCUIT STRUCTURES, AND METHOD OF MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09212503
|
Filing Dt:
|
12/15/1998
|
|
Title:
|
ENDPOINT DETECTION METHOD AND APPARATUS WHICH UTILIZE A CHELATING AGENT TO DETECT A POLISHING ENDPOINT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09212769
|
Filing Dt:
|
12/16/1998
|
|
Title:
|
INTEGRATED CIRCUIT DESIGN USING A FREQUENCY SYNTHESIZER THAT AUTOMATICALLY ENSURES TESTABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09212931
|
Filing Dt:
|
12/16/1998
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A RECESSED GATE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09213803
|
Filing Dt:
|
12/17/1998
|
|
Title:
|
APPARATUS AND METHOD OF PLANARIZING A SEMICONDUCTOR WAFER THAT INCLUDES A FIRST REFLECTIVE SUBSTANCE AND A SECOND REFLECTIVE SUBSTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09213847
|
Filing Dt:
|
12/17/1998
|
|
Title:
|
FABRICATION OF METAL-INSULATOR-METAL CAPACITIVE STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09213948
|
Filing Dt:
|
12/17/1998
|
|
Title:
|
SUBSTRATE PLANARIZATION WITH A CHEMICAL MECHANICAL POLISHING STOP LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09216394
|
Filing Dt:
|
12/18/1998
|
|
Title:
|
FABRICATION OF DIFFERENTIAL GATE OXIDE THICKNESSES ON A SINGLE INTEGRATED CIRCUIT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09218574
|
Filing Dt:
|
12/22/1998
|
|
Title:
|
MULTI-LAYERED TITANIUM NITRIDE BARRIER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09218649
|
Filing Dt:
|
12/22/1998
|
|
Title:
|
BARRIER FOR COPPER METALLIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09218780
|
Filing Dt:
|
12/22/1998
|
|
Title:
|
METHOD TO OBTAIN A LOW RESISTIVITY AND CONFORMITY CHEMICAL VAPOR DEPOSITION TITANIUM FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09219655
|
Filing Dt:
|
12/23/1998
|
|
Title:
|
VERTICAL INTERDIGITATED METAL-INSULATOR-MATAL CAPACITOR FOR AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09220417
|
Filing Dt:
|
12/24/1998
|
|
Title:
|
CHEMICAL-MECHANICAL POLISHING APPARATUS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09221023
|
Filing Dt:
|
12/23/1998
|
|
Title:
|
METHOD OF FORMING AND ELECTRICALLY CONNECTING A VERTICAL INTERDIGITATED METAL-INSULATOR- METAL CAPACITOR EXTENDING BETWEEN INTERCONNECT LAYERS IN AN INTERGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09221726
|
Filing Dt:
|
12/29/1998
|
|
Title:
|
MEASUREMENT OF MECHANICAL FASTENER CLAMPING FORCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09222110
|
Filing Dt:
|
12/29/1998
|
|
Title:
|
LOW TEMPERATURE COEFFICIENT DIELECTRIC MATERIALS AND DEVICES COMPRISING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09222587
|
Filing Dt:
|
12/28/1998
|
|
Title:
|
VERTICAL PNP BIPOLAR TRANSISTOR AND ITS METHOD OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09223354
|
Filing Dt:
|
12/30/1998
|
|
Title:
|
N-PROFILE ENGINEERING AT THE POLY/GATE OXIDE AND GATE OXIDE/SI INTERFACES THROUGH NH3 ANNEALING OF A LAYERED POLY/A-SI STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09226730
|
Filing Dt:
|
01/07/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09228906
|
Filing Dt:
|
01/11/1999
|
|
Title:
|
CONFINEMENT DEVICE FOR USE IN DRY ETCHING OF SUBSTRATE SURFACE AND METHOD OF DRY ETCHING A WAFER SURFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2002
|
Application #:
|
09231265
|
Filing Dt:
|
01/15/1999
|
|
Title:
|
FLAME-FREE WET OXIDATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09231566
|
Filing Dt:
|
01/14/1999
|
|
Title:
|
ARTICLE COMPRISING ELECTRONIC CIRCUITS AND DEVICES WITH MAGNETICALLY PROGRAMMABLE ELECTRICAL RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09232120
|
Filing Dt:
|
01/15/1999
|
|
Title:
|
METHOD FOR REMOVING CONTAMINANTS FROM INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09232418
|
Filing Dt:
|
01/15/1999
|
|
Title:
|
ELECTRONIC APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09233529
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
METASTABILITY RISK SIMULATION ANALYSIS TOOL AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09233828
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
MASK HAVING AN ARBITRARY COMPLEX TRANSMISSION FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09233885
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
HYBRID AERIAL IMAGE SIMULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09234422
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
GEOMETRIC AERIAL IMAGE SIMULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09235011
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
FLIP CHIP ASSEMBLY OF SEMICONDUCTOR IC CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09235735
|
Filing Dt:
|
01/22/1999
|
|
Title:
|
PROCESS FOR FABRICATING DEVICE COMPRISING LEAD ZIRCONATE TITANATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09235795
|
Filing Dt:
|
01/22/1999
|
|
Title:
|
ELECTRONIC APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09236763
|
Filing Dt:
|
01/25/1999
|
|
Title:
|
TRANSISTOR UTILIZING PHOTONIC BAND-GAP MATERIAL AND INTEGRATED CIRCUIT DEVICES COMPRISING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09236933
|
Filing Dt:
|
01/25/1999
|
|
Title:
|
PROCESS FOR FABRICATING ARTICLE COMPRISING ALIGNED TRUNCATED CARBON NANOTUBES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09236966
|
Filing Dt:
|
01/25/1999
|
|
Title:
|
ARTICLE COMPRISING ENHANCED NANOTUBE EMITTER STRUCTURE AND PROCESS FOR FABRICATING ARTICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09238706
|
Filing Dt:
|
01/28/1999
|
|
Title:
|
INTEGRATED CIRCUIT BONDING METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
09240432
|
Filing Dt:
|
01/29/1999
|
|
Title:
|
APPARATUS AND METHOD FOR ANALYZING CIRCUITS USING REDUCED-ORDER MODELING OF LARGE LINEAR SUBCIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09241458
|
Filing Dt:
|
02/02/1999
|
|
Title:
|
ARTICLE FOR DE-EMBEDDING PARASITICS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09243047
|
Filing Dt:
|
02/03/1999
|
|
Title:
|
FULLY ISOLATED THIN-FILM TRENCH CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09243377
|
Filing Dt:
|
02/01/1999
|
|
Title:
|
INTEGRATED CIRCUIT COMPRISING MEANS FOR HIGH FREQUENCY SIGNAL TRANSMISSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09244327
|
Filing Dt:
|
02/03/1999
|
|
Title:
|
FUNCTIONAL OBIC ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09244857
|
Filing Dt:
|
02/05/1999
|
|
Title:
|
DEVICE AND METHOD FOR PROTECTING ELECTRONIC COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09245078
|
Filing Dt:
|
02/05/1999
|
|
Title:
|
METHOD APPARATUS, AND COMMUNICATION PROTOCOL FOR TRANSMITTING CONTROL DATA WITH AN IMPROVED ERROR CORRECTION CAPABILITY IN A DIGITAL CORDLESS TELEPHONE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09245193
|
Filing Dt:
|
02/05/1999
|
|
Title:
|
NMOS ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD FOR CMOS INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09246402
|
Filing Dt:
|
02/08/1999
|
|
Title:
|
METHOD FOR FABRICATING A MERGED INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
09250500
|
Filing Dt:
|
02/16/1999
|
|
Title:
|
CAPACITOR FOR AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09250501
|
Filing Dt:
|
02/16/1999
|
|
Title:
|
METHOD OF MAKING A CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09251702
|
Filing Dt:
|
02/17/1999
|
|
Title:
|
METHOD AND COMPOSITION FOR REDUCING GATE OXIDE DAMAGE DURING RF SPUTTER CLEAN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09255845
|
Filing Dt:
|
02/23/1999
|
|
Title:
|
METHOD FOR MAKING INP HETEROSTRUCTURE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09256443
|
Filing Dt:
|
02/23/1999
|
|
Title:
|
FLIP CHIP BUMP BONDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09259001
|
Filing Dt:
|
02/26/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE STRUCTURE INCLUDING A TANTALUM PENTOXIDE LAYER SANDWICHED BETWEEN SILICON NITRIDE LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09259028
|
Filing Dt:
|
02/26/1999
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2002
| | | | |
|
Title:
|
PROCESS FOR THE FABRICATION OF DUAL GATE STRUCTURES FOR CMOS DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09261093
|
Filing Dt:
|
03/02/1999
|
|
Title:
|
FABRICATING HIGH-Q RF COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09261270
|
Filing Dt:
|
03/01/1999
|
|
Title:
|
METAL INTERCONNECT STACK FOR INTEGRATED CIRCUIT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09261346
|
Filing Dt:
|
03/03/1999
|
|
Title:
|
PROCESS FOR FABRICATING IMPROVED IRON-COBALT MAGNETOSTRICTIVE ALLOY AND ARTICLE COMPRISING ALLOY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09263075
|
Filing Dt:
|
03/08/1999
|
|
Title:
|
INTEGRATED CIRCUIT HAVING REDUCED PROBABILITY OF WIRE-BOND FAILURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09263445
|
Filing Dt:
|
03/05/1999
|
|
Title:
|
ON-CHIP SHIELDING OF SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09265510
|
Filing Dt:
|
03/09/1999
|
|
Title:
|
PERFORMING OPTICAL PROXIMITY CORRECTION WITH THE AID OF DESIGN RULE CHECKERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09265932
|
Filing Dt:
|
03/11/1999
|
|
Title:
|
INTEGRATED CIRCUIT TESTING USING A HIGH SPEED DATA INTERFACE BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09266174
|
Filing Dt:
|
03/10/1999
|
|
Title:
|
TOP SURFACE IMAGING TECHNIQUE USING A TOPCOAT DELIVERY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
09266912
|
Filing Dt:
|
03/12/1999
|
|
Title:
|
ENERGY-SENSITIVE RESIST MATERIAL AND A PROCESS FOR DEVICE FABRICATION USING AN ENERGY-SENSITIVE RESIST MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
09268867
|
Filing Dt:
|
03/16/1999
|
|
Title:
|
FLOOR PLAN-BASED POWER BUS ANALYSIS AND DESIGN TOOL FOR INTEGRATED CIRCUTIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
09268902
|
Filing Dt:
|
03/16/1999
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
FLOOR PLAN DEVELOPMENT ELECTROMIGRATION AND VOLTAGE DROP ANALYSIS TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
09271084
|
Filing Dt:
|
03/17/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH INCREASED GATE INSULATOR LIFETIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09272732
|
Filing Dt:
|
12/14/1998
|
|
Title:
|
MEV IMPLANTATION TO FORM VERTICALLY MODULATED N+ BURIED LAYER IN AN NPN BIPOLAR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09273299
|
Filing Dt:
|
03/19/1999
|
|
Title:
|
SCHOTTKY DIODE GUARD RING STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09274254
|
Filing Dt:
|
03/22/1999
|
|
Title:
|
FORMATION OF IMPROVED LOW DIELECTRIC CONSTANT CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL BY REACTION OF CARBON-CONTAINING SILANE WITH OXIDIZING AGENT IN THE PRESENCE OF ONE OR MORE REACTION RETARDANTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09274457
|
Filing Dt:
|
03/22/1999
|
|
Title:
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LOW DIELECTRIC CONSTANT MULTIPLE CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL FOR USE IN INTEGRATED CIRCUIT STRUCTURES, AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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01/02/2001
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Application #:
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09276034
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Filing Dt:
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03/25/1999
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Title:
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METHOD FOR CLEANING VIA OPENINGS IN INTEGRATED CIRCUIT MANUFACTURING
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09276912
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Filing Dt:
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03/27/1999
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Title:
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HYBRID INORGANIC-ORGANIC COMPOSITE FOR USE AS AN INTERLAYER DIELECTRIC
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09277778
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Filing Dt:
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03/29/1999
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Title:
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METHOD OF MAKING A CAPACITOR
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09280103
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Filing Dt:
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03/29/1999
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Title:
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DEVICE COMPRISING N-CHANNEL SEMICONDUCTOR MATERIAL
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09280387
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Filing Dt:
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03/29/1999
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Title:
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CAPACITOR FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09281514
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Filing Dt:
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03/29/1999
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Title:
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PROCESS FOR TREATING DAMAGED SURFACES OF LOW DIELECTRIC CONSTANT ORGANO SILICON OXIDE INSULATION MATERIAL TO INHIBIT MOISTURE ABSORPTION
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09281602
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Filing Dt:
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03/29/1999
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Title:
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PLASMA CLEANING PROCESS FOR OPENINGS FORMED IN AT LEAST ONE LOW DIELECTRIC CONSTANT INSULATION LAYER OVER COPPER METALLIZATION IN INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09281642
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Filing Dt:
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03/31/1999
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Title:
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MANUFACTURING AND ENGINEERING DATA BASE
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09283392
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND APPARATUS FOR MODELING ELECTROMAGNETIC INTERACTIONS IN ELECTRICAL CIRCUIT METALIZATIONS TO SIMULATE THEIR ELECTRICAL CHARACTERISTICS
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09283393
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Filing Dt:
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04/01/1999
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Title:
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MEHTOD AND APPARATUS FOR QUASI FULL-WAVE MODELING OF INTERACTIONS IN CIRCUITS
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09283394
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND APPARATUS FOR MODELING ELECTROMAGNETIC INTERACTIONS IN ELECTRICAL CIRCUIT METALIZATIONS TO SIMULATE THEIR ELECTRICAL CHARACTERISTICS
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09283395
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Filing Dt:
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04/01/1999
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Title:
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METHOD AND APPARATUS FOR MODELING ELECTROMAGNETIC INTERACTIONS IN ELECTRICAL CIRCUIT METALIZATIONS TO SIMULATE THEIR ELECTRICAL CHARACTERISTICS
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09283528
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Filing Dt:
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04/01/1999
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Title:
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LITHOGRAPHIC PROCESS FOR DEVICE FABRICATION USING DARK-FIELD ILLUMINATION
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09286430
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Filing Dt:
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04/06/1999
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Title:
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MOBIUS STRIP BELT FOR LINEAR CMP TOOLS
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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09286869
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Filing Dt:
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04/06/1999
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Title:
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APPARATUS AND METHOD FOR CONTINUOUS DELIVERY AND CONDITIONING OF A POLISHING SLURRY
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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09286929
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Filing Dt:
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04/06/1999
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Title:
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METHOD FOR PROCESSING SILICON WORKPIECES USING HYBRID OPTICAL THERMOMETER SYSTEM
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09287862
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Filing Dt:
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04/07/1999
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Publication #:
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Pub Dt:
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12/13/2001
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Title:
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CHIP-ON-CHIP TESTING USING BIST
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09288746
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Filing Dt:
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04/08/1999
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Title:
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METHOD OF MANUFACTURE FOR AN INTEGRATED CIRCUIT HAVING A BIST CIRCUIT AND BOND PADS INCORPORATED THEREIN
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09289828
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Filing Dt:
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04/12/1999
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Title:
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CONSISTENT ALIGNMENT MARK PROFILES ON SEMICONDUCTOR WAFERS USING METAL ORGANIC CHEMICAL VAPOR DEPOSITION TITANIUM NITRIDE PROTECTIVE LAYER
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09290321
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Filing Dt:
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04/12/1999
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Title:
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DERIVING STATISTICAL DEVICE MODELS FROM ELECTRICAL TEST DATA
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09291157
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Filing Dt:
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04/12/1999
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Title:
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DERIVING STATISTICAL DEVICE MODELS FROM WORST-CASE FILES
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09291448
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Filing Dt:
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04/13/1999
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Title:
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BUILT-IN SELF-TEST FOR GENERATING A USAGE PROFILE TO IDENTIFY IDLE FUNCTIONAL UNIT OF AN INTEGRATED CIRCUIT DURING OPERATION FOR ON-LINE TESTING OF THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09291781
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Filing Dt:
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04/14/1999
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Title:
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EMBEDDED THIN FILM PASSIVE COMPONENTS
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09292079
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Filing Dt:
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04/14/1999
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Title:
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REDUCTION OF PLASMA DAMAGE AT CONTACT ETCH IN MOS INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09292422
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Filing Dt:
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04/15/1999
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Title:
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DAMASCENE CAPACITORS FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09292860
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Filing Dt:
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04/16/1999
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Title:
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MICROMAGNETIC DEVICE HAVING AN ANISOTROPIC FERROMAGNETIC CORE AND METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09293103
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Filing Dt:
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04/16/1999
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Title:
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LITHOGRAPHIC PROCESS HAVING SUB-WAVELENGTH RESOLUTION
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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09293510
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Filing Dt:
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04/15/1999
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Title:
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DIGITAL NOISE REDUCTION IN INTEGRATED CIRCUITS AND CIRCUIT ASSEMBLIES
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09296001
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Filing Dt:
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04/21/1999
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Publication #:
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Pub Dt:
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01/03/2002
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Title:
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DEVICE COMPRISING THERMALLY STABLE, LOW DIELECTRIC CONSTANT MATERIAL
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09298068
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Filing Dt:
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04/22/1999
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Title:
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METHOD OF FORMING A MULTI-LAYERED DUAL-POLYSILICON STRUCTURE
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09298792
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Filing Dt:
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04/23/1999
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Title:
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METHOD OF PLANARIZING A SURFACE ON AN INTEGRATED CIRCUIT
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