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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09690047
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Filing Dt:
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10/16/2000
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Title:
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METHOD AND APPARATUS FOR WASHING DRUMS
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09692012
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Filing Dt:
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10/19/2000
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Title:
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DUAL LEVEL GATE PROCESS FOR HOT CARRIER CONTROL IN DOUBLE DIFFUSED MOS TRANSISTORS
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Patent #:
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Issue Dt:
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01/15/2002
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Application #:
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09693014
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Filing Dt:
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10/20/2000
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Title:
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Off-grid metal layer utilization
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Patent #:
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Issue Dt:
|
04/23/2002
|
Application #:
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09695534
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Filing Dt:
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10/24/2000
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Title:
|
DIRECT CURRENT DECHUCKING SYSTEM
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Patent #:
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Issue Dt:
|
12/17/2002
|
Application #:
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09695540
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Filing Dt:
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10/24/2000
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Title:
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APPARATUS SUITABLE FOR MOUNTING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09698175
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Filing Dt:
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10/30/2000
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Title:
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METHOD OF MANUFACTURING AND MOUNTING ELECTRONIC DEVICES TO LIMIT THE EFFECTS OF PARASITICS
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Patent #:
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Issue Dt:
|
10/23/2001
|
Application #:
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09698375
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Filing Dt:
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10/26/2000
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Title:
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Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation
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Patent #:
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Issue Dt:
|
05/21/2002
|
Application #:
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09703616
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Filing Dt:
|
10/30/2000
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|
Title:
|
PROCESS FOR CMP REMOVAL OF EXCESS TRENCH OR VIA FILLER METAL WHICH INHIBITS FORMATION OF CONCAVE REGIONS ON OXIDE SURFACE OF INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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|
Issue Dt:
|
07/09/2002
|
Application #:
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09703745
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Filing Dt:
|
10/31/2000
|
|
Title:
|
PROCESS FOR PLANARIZATION OF METAL-FILLED TRENCHES OF INTEGRATED CIRCUIT STRUCTURES BY FORMING A LAYER OF PLANARIZABLE MATERIAL OVER THE METAL LAYER PRIOR TO PLANARIZING
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Patent #:
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Issue Dt:
|
07/23/2002
|
Application #:
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09704164
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Filing Dt:
|
10/31/2000
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Title:
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PROCESS FOR FORMING LOW K DIELECTRIC MATERIAL BETWEEN METAL LINES
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Patent #:
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Issue Dt:
|
03/25/2003
|
Application #:
|
09704200
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Filing Dt:
|
10/31/2000
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|
Title:
|
PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH LOW DIELECTRIC CONSTANT MATERIAL BETWEEN CLOSELY SPACED APART METAL LINES
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Patent #:
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|
Issue Dt:
|
07/16/2002
|
Application #:
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09704635
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Filing Dt:
|
11/01/2000
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Title:
|
PROCESS FOR INHIBITING CRACK FORMATION IN LOW DIELECTRIC CONSTANT DIELECTRIC FILMS OF INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
|
04/08/2003
|
Application #:
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09706286
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Filing Dt:
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11/03/2000
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Title:
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PROCESS MONITOR WITH STATISTICALLY SELECTED RING OSCILLATOR
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Patent #:
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|
Issue Dt:
|
03/19/2002
|
Application #:
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09706319
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Filing Dt:
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11/03/2000
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Title:
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Integrated circuits with tub-ties and shallow trench isolation
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Patent #:
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|
Issue Dt:
|
12/02/2003
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Application #:
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09710359
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Filing Dt:
|
11/09/2000
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Title:
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METHOD TO TRANSLATE UDPS USING GATE PRIMITIVES
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Patent #:
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|
Issue Dt:
|
07/08/2003
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Application #:
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09712732
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Filing Dt:
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11/14/2000
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|
Title:
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SYSTEM AND METHOD FOR REMOVAL OF MATERIAL
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Patent #:
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Issue Dt:
|
10/28/2003
|
Application #:
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09713106
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Filing Dt:
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11/15/2000
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Title:
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A SEMICONDUCTOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
05/06/2003
|
Application #:
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09713504
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Filing Dt:
|
11/15/2000
|
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Title:
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METHOD FOR AVOIDING NOTCHING IN A SEMICONDUCTOR INTERCONNECT DURING A METAL ETCHING STEP
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Patent #:
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Issue Dt:
|
08/19/2003
|
Application #:
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09714000
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Filing Dt:
|
11/15/2000
|
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Title:
|
PROCESS FOR FORMING PLANARIZED ISOLATION TRENCH IN INTEGRATED CIRCUIT STRUCTURE ON SEMICONDUCTOR SUBSTRATE
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Patent #:
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|
Issue Dt:
|
03/11/2003
|
Application #:
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09714370
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Filing Dt:
|
11/14/2000
|
|
Title:
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METHOD AND APPARATUS FOR APPLICATION OF PROXIMITY CORRECTION WITH RELATIVE SEGMENTATION
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Patent #:
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|
Issue Dt:
|
06/01/2004
|
Application #:
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09715651
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Filing Dt:
|
11/17/2000
|
|
Title:
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METHOD FOR MAKING A RADIO FREQUENCY COMPONENT AND COMPONENT PRODUCED THEREBY
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Patent #:
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|
Issue Dt:
|
12/17/2002
|
Application #:
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09715814
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Filing Dt:
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11/17/2000
|
|
Title:
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STANDARD LIBRARY GENERATOR FOR CELL TIMING MODEL
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Patent #:
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|
Issue Dt:
|
02/04/2003
|
Application #:
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09718935
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Filing Dt:
|
11/21/2000
|
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Title:
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SEMICONDUCTOR POLISHING PAD ALIGNMENT DEVICE FOR A POLISHING APPARATUS AND METHOD OF USE
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Patent #:
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Issue Dt:
|
02/25/2003
|
Application #:
|
09723434
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Filing Dt:
|
11/27/2000
|
|
Title:
|
METAL-INSULATOR-METAL CAPACITOR FORMED BY DAMASCENE PROCESSES BETWEEN METAL INTERCONNECT LAYERS AND METHOD OF FORMING SAME
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Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09723516
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Filing Dt:
|
11/28/2000
|
|
Title:
|
SILICON NITRIDE AND SILICON DIOXIDE GATE INSULATOR TRANSISTORS AND METHOD OF FORMING SAME IN A HYBRID INTEGRATED CIRCUIT
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|
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|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
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09723557
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Filing Dt:
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11/28/2000
|
|
Title:
|
BARRIER FOR COPPER METALLIZATION
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|
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|
Patent #:
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|
Issue Dt:
|
02/18/2003
|
Application #:
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09724225
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Filing Dt:
|
11/28/2000
|
|
Title:
|
METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBIRD INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBIRD CIRCUIT
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|
|
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|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09724444
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Filing Dt:
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11/28/2000
|
|
Title:
|
SILICON GERMANIUM CMOS CHANNEL
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|
|
|
Patent #:
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|
Issue Dt:
|
04/29/2003
|
Application #:
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09725631
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Filing Dt:
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11/29/2000
|
|
Title:
|
DEVICE FREQUENCY MEASUREMENT SYSTEM
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|
Patent #:
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|
Issue Dt:
|
10/14/2003
|
Application #:
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09727014
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Filing Dt:
|
11/30/2000
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2002
| | | | |
|
Title:
|
MASS SPECTROMETER PARTICLE COUNTER
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|
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|
Patent #:
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|
Issue Dt:
|
08/13/2002
|
Application #:
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09727195
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Filing Dt:
|
11/30/2000
|
|
Publication #:
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|
Pub Dt:
|
05/30/2002
| | | | |
|
Title:
|
METHOD OF MANUFACTURING AN INTERCONNECT STRUCTURE HAVING A PASSIVATION LAYER FOR PREVENTING SUBSEQUENT PROCESSING REACTIONS
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Patent #:
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Issue Dt:
|
03/25/2003
|
Application #:
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09727325
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Filing Dt:
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11/30/2000
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Publication #:
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Pub Dt:
|
05/30/2002
| | | | |
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Title:
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INTEGRATED CIRCUIT FABRICATION
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Patent #:
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Issue Dt:
|
07/01/2003
|
Application #:
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09727326
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Filing Dt:
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11/30/2000
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Publication #:
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Pub Dt:
|
05/30/2002
| | | | |
|
Title:
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METHOD FOR CLEANING TUNGSTEN FROM DEPOSITION WALL CHAMBERS
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Patent #:
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Issue Dt:
|
09/10/2002
|
Application #:
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09727426
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Filing Dt:
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11/30/2000
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Publication #:
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Pub Dt:
|
05/30/2002
| | | | |
|
Title:
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PIN PLACEMENT METHOD FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
12/31/2002
|
Application #:
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09728448
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Filing Dt:
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12/01/2000
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Publication #:
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Pub Dt:
|
06/06/2002
| | | | |
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Title:
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METHOD FOR MAKING AN INTEGRATED CIRCUIT DEVICE WITH DIELECTRICALLY ISOLATED TUBS AND RELATED CIRCUIT
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Patent #:
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Issue Dt:
|
07/02/2002
|
Application #:
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09730704
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Filing Dt:
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12/06/2000
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Publication #:
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|
Pub Dt:
|
06/14/2001
| | | | |
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Title:
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CMP SLURRY RECYCLING APPARATUS AND METHOD FOR RECYCLING CMP SLURRY
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Patent #:
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Issue Dt:
|
05/24/2005
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Application #:
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09731402
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Filing Dt:
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02/06/2001
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Publication #:
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Pub Dt:
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08/08/2002
| | | | |
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Title:
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METHOD AND APPARATUS FOR CONDITIONING A POLISHING PAD
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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09731596
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Filing Dt:
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12/06/2000
|
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Title:
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METHOD FOR PROBING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09733570
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Filing Dt:
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12/08/2000
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Publication #:
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Pub Dt:
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06/13/2002
| | | | |
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Title:
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METHODS FOR DEUTERIUM SINTERING
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09734539
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Filing Dt:
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12/11/2000
|
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Title:
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A METHOD FOR MINIMIZING CLOCK SKEW BY RELOCATING A CLOCK BUFFER UNTIL CLOCK SKEW IS WITHIN A TOLERABLE LIMIT
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Patent #:
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|
Issue Dt:
|
07/01/2003
|
Application #:
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09735084
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Filing Dt:
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12/11/2000
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Title:
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ETCH RESISTANT SHALLOW TRENCH ISOLATION IN A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09735085
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Filing Dt:
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12/11/2000
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Title:
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INTERCONNECTOR AND METHOD OF CONNECTING PROBES TO A DIE FOR FUNCTIONAL ANALYSIS
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Patent #:
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Issue Dt:
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01/22/2002
|
Application #:
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09735233
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Filing Dt:
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12/11/2000
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Title:
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Designing memory for testability to support scan capability in an asic design
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Patent #:
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Issue Dt:
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10/14/2003
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Application #:
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09735255
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Filing Dt:
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12/12/2000
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Title:
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DELAY/LOAD ESTIMATION FOR USE IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
03/18/2003
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Application #:
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09735837
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Filing Dt:
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12/13/2000
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Title:
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CELL PIN EXTENSIONS FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09736571
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Filing Dt:
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12/14/2000
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Title:
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NETLIST RESYNTHESIS PROGRAM USING STRUCTURE CO-FACTORING
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Patent #:
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Issue Dt:
|
04/29/2003
|
Application #:
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09737239
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Filing Dt:
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12/14/2000
|
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Title:
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NETLIST RESYNTHESIS PROGRAM BASED ON PHYSICAL DELAY CALCULATION
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Patent #:
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Issue Dt:
|
08/07/2001
|
Application #:
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09737504
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Filing Dt:
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12/15/2000
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Publication #:
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Pub Dt:
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05/10/2001
| | | | |
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Title:
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Apparatus for enhancing image contrast using intensity filtration
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09737717
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Filing Dt:
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12/15/2000
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Publication #:
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Pub Dt:
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06/20/2002
| | | | |
|
Title:
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METHOD OF CLEANING A SEMICONDUCTOR WAFER WITH A CLEANING BRUSH ASSEMBLY HAVING A CONTRACTIBLE AN EXPANDABLE ARBOR
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09741568
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Filing Dt:
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12/19/2000
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Publication #:
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Pub Dt:
|
06/20/2002
| | | | |
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Title:
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CARBON-DOPED HARD MASK AND METHOD OF PASSIVATING STRUCTURES DURING SEMICONDUCTOR DEVICE FABRICATION
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09741667
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Filing Dt:
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12/19/2000
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Publication #:
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Pub Dt:
|
10/18/2001
| | | | |
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Title:
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VIRTUAL-GROUND, SPLIT-GATE FLASH MEMORY CELL ARRANGEMENTS AND METHOD FOR PRODUCING SAME
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Patent #:
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Issue Dt:
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09/21/2004
|
Application #:
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09742314
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Filing Dt:
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12/21/2000
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Publication #:
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Pub Dt:
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06/27/2002
| | | | |
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Title:
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INTER-WIRING-LAYER CAPACITORS
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Patent #:
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Issue Dt:
|
09/23/2003
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Application #:
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09742855
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Filing Dt:
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12/19/2000
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Publication #:
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Pub Dt:
|
07/31/2003
| | | | |
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Title:
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OPTICAL STRUCTURES AND METHODS FOR X-RAY APPLICATIONS
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Patent #:
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Issue Dt:
|
08/12/2003
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Application #:
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09745236
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Filing Dt:
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12/19/2000
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Publication #:
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Pub Dt:
|
11/22/2001
| | | | |
|
Title:
|
X-RAY SYSTEM
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Patent #:
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Issue Dt:
|
10/08/2002
|
Application #:
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09747638
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Filing Dt:
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12/22/2000
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Title:
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INTEGRATED CIRCUIT FABRICATION DUAL PLASMA PROCESS WITH SEPARATE INTRODUCTION OF DIFFERENT GASES INTO GAS FLOW
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09750639
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Filing Dt:
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12/28/2000
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Title:
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ARRANGEMENT AND METHOD FOR POLISHING A SURFACE OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09752626
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Filing Dt:
|
12/28/2000
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Title:
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SIX-TO-ONE SIGNAL/POWER RATIO BUMP AND TRACE PATTERN FOR FLIP CHIP DESIGN
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Patent #:
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Issue Dt:
|
06/18/2002
|
Application #:
|
09753000
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Filing Dt:
|
12/30/2000
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Title:
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IRREGULAR GRID BOND PAD LAYOUT ARRANGEMENT FOR A FLIP CHIP PACKAGE
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Patent #:
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Issue Dt:
|
03/12/2002
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Application #:
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09754429
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Filing Dt:
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01/04/2001
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Publication #:
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Pub Dt:
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09/13/2001
| | | | |
|
Title:
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Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09754611
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Filing Dt:
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01/04/2001
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Publication #:
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Pub Dt:
|
07/04/2002
| | | | |
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Title:
|
MEASUREMENT TECHNIQUE FOR ULTRA-THIN OXIDES
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Patent #:
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Issue Dt:
|
04/19/2011
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Application #:
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09755826
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Filing Dt:
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01/04/2001
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Publication #:
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Pub Dt:
|
12/13/2001
| | | | |
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Title:
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METHOD OF MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
12/29/2009
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Application #:
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09755828
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Filing Dt:
|
01/04/2001
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|
Publication #:
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|
Pub Dt:
|
12/06/2001
| | | | |
|
Title:
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METHOD FOR MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
02/25/2003
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Application #:
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09756506
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Filing Dt:
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01/08/2001
|
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Title:
|
FLIP CHIP TRACE LIBRARY GENERATOR
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
09756561
|
Filing Dt:
|
01/08/2001
|
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Publication #:
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Pub Dt:
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07/11/2002
| | | | |
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Title:
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Optimal clock timing schedule for an integrated circuit
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09756568
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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09/05/2002
| | | | |
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Title:
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Process for fast cell placement in integrated circuit design
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Patent #:
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Issue Dt:
|
12/16/2003
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Application #:
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09756965
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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NON-CONTACT METHOD FOR DETERMINING QUALITY OF SEMICONDUCTOR DIELECTRICS
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09758603
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Filing Dt:
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01/12/2001
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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ROUTING TECHNIQUE TO ADJUST CLOCK SKEW
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09759120
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Filing Dt:
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01/12/2001
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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HETEROJUNCTION BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09765827
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Filing Dt:
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01/19/2001
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Publication #:
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Pub Dt:
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09/13/2001
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Title:
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FLIP-CHIP INTEGRATED CIRCUIT ROUTING TO I/O DEVICES
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Patent #:
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Issue Dt:
|
05/28/2002
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Application #:
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09766104
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Filing Dt:
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01/19/2001
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Title:
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HEAT SINK WITH CHIP DIE EMC GROUND INTERCONNECT
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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09767477
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Filing Dt:
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01/23/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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BIPOLAR DEVICE
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Patent #:
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Issue Dt:
|
04/01/2003
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Application #:
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09771272
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Filing Dt:
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01/26/2001
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Title:
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ELMORE MODEL ENHANCEMENT
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Patent #:
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Issue Dt:
|
08/27/2002
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Application #:
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09771621
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Filing Dt:
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01/30/2001
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Publication #:
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Pub Dt:
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08/01/2002
| | | | |
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Title:
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ALIGNMENT MARK FABRICATION PROCESS TO LIMIT ACCUMULATION OF ERRORS IN LEVEL TO LEVEL OVERLAY
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Patent #:
|
NONE
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Issue Dt:
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Application #:
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09777470
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Filing Dt:
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02/06/2001
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|
Publication #:
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Pub Dt:
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08/08/2002
| | | | |
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Title:
|
Conditioning wheel for conditioning a semiconductor wafer polishing pad and method of manufacture thereof
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Patent #:
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|
Issue Dt:
|
04/20/2004
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Application #:
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09777996
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Filing Dt:
|
02/06/2001
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|
Title:
|
CLUSTER TOOL REPORTING SYSTEM
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|
|
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Patent #:
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|
Issue Dt:
|
03/09/2004
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Application #:
|
09778986
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Filing Dt:
|
02/07/2001
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|
Publication #:
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Pub Dt:
|
08/08/2002
| | | | |
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Title:
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CONDITIONING WHEEL FOR CONDITIONING A SEMICONDUCTOR WAFER POLISHING PAD AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
04/27/2004
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Application #:
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09780861
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Filing Dt:
|
02/09/2001
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|
Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
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Title:
|
SEQUENTIAL TEST PATTERN GENERATION USING COMBINATIONAL TECHNIQUES
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|
|
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Patent #:
|
|
Issue Dt:
|
05/06/2003
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Application #:
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09781423
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Filing Dt:
|
02/13/2001
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|
Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
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Title:
|
LEAD STRUCTURE FOR SEALING PACKAGE
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|
|
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Patent #:
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|
Issue Dt:
|
10/08/2002
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Application #:
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09785636
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Filing Dt:
|
02/16/2001
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|
Publication #:
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Pub Dt:
|
10/10/2002
| | | | |
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Title:
|
METHOD OF MANUFACTURING A POLISHING PAD USING A BEAM
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/08/2003
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Application #:
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09785756
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Filing Dt:
|
02/16/2001
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|
Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
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Title:
|
COMPOSITE POLISHING PADS FOR CHEMICAL-MECHANICAL POLISHING
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/12/2002
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Application #:
|
09788257
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Filing Dt:
|
02/15/2001
|
|
Title:
|
BALANCED CLOCK PLACEMENT FOR INTEGRATED CIRCUITS CONTAINING MEGACELLS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
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Application #:
|
09789108
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Filing Dt:
|
02/20/2001
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|
Title:
|
PLACEMENT-BASED INTEGRATED CIRCUIT RE-SYNTHESIS TOOL USING ESTIMATED MAXIMUM INTERCONNECT CAPACITANCES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
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Application #:
|
09789254
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Filing Dt:
|
02/20/2001
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|
Publication #:
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|
Pub Dt:
|
08/23/2001
| | | | |
|
Title:
|
METHOD FOR FABRICATING A MERGED INTEGRATED CIRCUIT DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09790821
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Filing Dt:
|
02/22/2001
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|
Publication #:
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|
Pub Dt:
|
06/28/2001
| | | | |
|
Title:
|
PROCESS FOR MAKING INTEGRATED CIRCUIT STRUCTURE WITH THIN DIELECTRIC BETWEEN AT LEAST LOCAL INTERCONNECT LEVEL AND FIRST METAL INTERCONNECT LEVEL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
09792266
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Filing Dt:
|
02/23/2001
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|
Publication #:
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|
Pub Dt:
|
08/29/2002
| | | | |
|
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
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Application #:
|
09792321
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Filing Dt:
|
02/23/2001
|
|
Title:
|
METHOD OF PROTECTING ACID-CATALYZED PHOTORESIST FROM CHIP-GENERATED BASIC CONTAMINANTS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09792683
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Filing Dt:
|
02/23/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
|
Title:
|
PROCESS FOR FORMING A LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
09792685
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Filing Dt:
|
02/23/2001
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|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
|
Title:
|
PROCESS FOR FORMING A LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL CHARACTERIZED BY IMPROVED RESISTANCE TO OXIDATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
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Application #:
|
09792691
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Filing Dt:
|
02/23/2001
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|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
|
Title:
|
PROCESS FOR FORMING A LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL CHARACTERIZED BY IMPROVED RESISTANCE TO OXIDATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09800049
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Filing Dt:
|
03/05/2001
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|
Publication #:
|
|
Pub Dt:
|
07/26/2001
| | | | |
|
Title:
|
SIMPLIFIED HIGH Q INDUCTOR SUBSTRATE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09800532
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Filing Dt:
|
03/06/2001
|
|
Title:
|
METHOD FOR MINIMIZING CLOCK SKEW FOR AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09801007
|
Filing Dt:
|
03/07/2001
|
|
Title:
|
METHOD FOR MANUFACTURING A DUAL CHIP IN PACKAGE WITH A FLIP CHIP DIE MOUNTED ON A WIRE BONDED DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
09801392
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Filing Dt:
|
03/07/2001
|
|
Title:
|
CELL INTERCONNECT DELAY LIBRARY FOR INTEGRATED CIRCUIT DESIGN
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09802043
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Filing Dt:
|
03/08/2001
|
|
Title:
|
GRIDLESS ROUTER USING MAZE AND LINE PROBE TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09802198
|
Filing Dt:
|
03/08/2001
|
|
Title:
|
BUILT-IN-SELF REPAIR CIRCUITRY UTILIZING PERMANENT RECORD OF DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09802424
|
Filing Dt:
|
03/09/2001
|
|
Title:
|
SUBSTRATE PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09804783
|
Filing Dt:
|
03/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
09/19/2002
| | | | |
|
Title:
|
METAL PLANARIZATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09804939
|
Filing Dt:
|
03/13/2001
|
|
Title:
|
CHANNEL ROUTER WITH BUFFER INSERTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09805642
|
Filing Dt:
|
03/13/2001
|
|
Title:
|
METHOD OF DATAPATH CELL PLACEMENT FOR AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09808441
|
Filing Dt:
|
03/14/2001
|
|
Title:
|
POWER MESH BRIDGE
|
|
