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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09808510
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Filing Dt:
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03/14/2001
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Title:
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METHOD FOR ESTIMATING POROSITY OF HARDMACS
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09808549
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Filing Dt:
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03/14/2001
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Title:
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FULL-CHIP EXTRACTION OF INTERCONNECT PARASITIC DATA
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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09809379
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Filing Dt:
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03/15/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
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Title:
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METHOD FOR DETECTING DEFECTS IN A MATERIAL AND A SYSTEM FOR ACCOMPLISHING THE SAME
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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09814417
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Filing Dt:
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03/21/2001
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Title:
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DRIVER WAVEFORM MODELING WITH MULTIPLE EFFECTIVE CAPACITANCES
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09817642
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Filing Dt:
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03/26/2001
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Title:
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CONCENTRIC METAL DENSITY POWER ROUTING
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09818799
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Filing Dt:
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03/27/2001
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Publication #:
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Pub Dt:
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09/20/2001
| | | | |
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Title:
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Electron emitters for lithography tools
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09820059
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Filing Dt:
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03/28/2001
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Title:
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DISTRIBUTION DEPENDENT CLUSTERING IN BUFFER INSERTION OF HIGH FANOUT NETS
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09821506
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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APPARATUS FOR DETECTING WETNESS OF A SEMICONDUCTOR WAFER CLEANING BRUSH
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09823184
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Filing Dt:
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03/29/2001
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Title:
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METHOD OF DATAPATH CELL PLACEMENT FOR BITWISE AND NON-BITWISE INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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09827434
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Filing Dt:
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04/06/2001
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Title:
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WIRE DELAY DISTRIBUTED MODEL
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09828553
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Filing Dt:
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04/05/2001
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Title:
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BUFFER CELL INSERTION AND ELECTRONIC DESIGN AUTOMATION
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09833142
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Filing Dt:
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04/11/2001
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Title:
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PROCESS FOR SOLVING ASSIGNMENT PROBLEMS IN INTEGRATED CIRCUIT DESIGNS WITH UNIMODAL OBJECT PENALTY FUNCTIONS AND LINEARLY ORDERED SET OF BOXES
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09833251
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Filing Dt:
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04/11/2001
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Title:
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PLATED THROUGH HOLE INTERCONNECTIONS
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09836129
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Filing Dt:
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04/16/2001
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Title:
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STATIC TIMING ANALYSIS VALIDATION TOOL FOR ASIC CORES
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09836365
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Filing Dt:
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04/16/2001
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
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METHOD OF COIL PREPARATION FOR IONIZED METAL PLASMA PROCESS AND METHOD OF MANUFACTURING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09837492
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Filing Dt:
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04/18/2001
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Title:
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CHIP CORE SIZE ESTIMATION
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09839925
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Filing Dt:
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04/20/2001
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Title:
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CONTACT ESCAPE PATTERN
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09841824
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Filing Dt:
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04/25/2001
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Title:
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ASSIGNMENT OF CELL COORDINATES
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09841825
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Filing Dt:
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04/25/2001
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Title:
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TIMING RECOMPUTATION
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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09842214
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Filing Dt:
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04/25/2001
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Publication #:
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Pub Dt:
|
11/14/2002
| | | | |
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Title:
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METHOD OF FABRICATING SUB-MICRON HEMISPHERICAL AND HEMICYLIDRICAL STRUCTURES FROM NON-SPHERICALLY SHAPED TEMPLATES
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09842350
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Filing Dt:
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04/25/2001
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Publication #:
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Pub Dt:
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10/31/2002
| | | | |
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Title:
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PARALLELIZATION OF RESYNTHESIS
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09843443
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Filing Dt:
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04/26/2001
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Title:
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DUAL CHIP IN PACKAGE WITH A WIRE BONDED DIE MOUNTED TO A SUBSTRATE
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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09844352
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Filing Dt:
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04/27/2001
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Title:
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IN SITU LINER BARRIER
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09844361
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Filing Dt:
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04/27/2001
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Title:
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DENSITY DRIVEN ASSIGNMENT OF COORDINATES
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09844531
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Filing Dt:
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04/27/2001
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Title:
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ANALOG CAPACITOR DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09846435
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Filing Dt:
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05/01/2001
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Title:
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TEST FIXTURE FOR FLIP CHIP BALL GRID ARRAY CIRCUITS
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09847460
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Filing Dt:
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05/02/2001
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Title:
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CIRCUIT MODELING
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09847838
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Filing Dt:
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04/30/2001
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Publication #:
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Pub Dt:
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10/31/2002
| | | | |
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Title:
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RTL ANNOTATION TOOL FOR LAYOUT INDUCED NETLIST CHANGES
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09848489
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Filing Dt:
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05/03/2001
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Title:
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METHOD AND APPARATUS FOR INDENTIFYING CAUSES OF POOR SILICON-TO-SIMULATION CORRELATION
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09848758
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Filing Dt:
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05/02/2001
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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PROCESS FOR FORMING METAL-FILLED OPENINGS IN LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL WHILE INHIBITING VIA POISONING
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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09849691
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Filing Dt:
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05/04/2001
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Title:
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MINIMAL BENDS CONNECTION MODELS FOR WIRE DENSITY CALCULATION
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09849919
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Filing Dt:
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05/04/2001
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Title:
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PROCESS, APPARATUS AND PROGRAM FOR TRANSFORMING PROGRAM LANGUAGE DESCRIPTION OF AN IC TO AN RTL DESCRIPTION
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09853317
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Filing Dt:
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05/11/2001
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Publication #:
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Pub Dt:
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11/14/2002
| | | | |
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Title:
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METHOD OF CREATING HYDROGEN ISOTOPE RESERVOIRS IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09854753
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Filing Dt:
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05/15/2001
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Publication #:
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Pub Dt:
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10/18/2001
| | | | |
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Title:
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Process for fabricating a projection electron lithography mask and a removable, reusable cover for use therein
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09858166
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Filing Dt:
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05/15/2001
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Title:
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NET DELAY OPTIMIZATION WITH RAMPTIME VIOLATION REMOVAL
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09859149
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Filing Dt:
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05/15/2001
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Title:
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MODELING DELAYS FOR SMALL NETS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09859316
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Filing Dt:
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05/17/2001
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Title:
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WAFER TESTABLE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09861839
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Filing Dt:
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05/21/2001
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Publication #:
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Pub Dt:
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10/04/2001
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Title:
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METHOD FOR PRODUCING DEVICES HAVING PIEZOELECTRIC FILMS
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09862045
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Filing Dt:
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05/21/2001
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Title:
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IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09863437
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Filing Dt:
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05/24/2001
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
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Title:
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PROCESS FOR PATTERNING A MEMBRANE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09863979
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Filing Dt:
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05/23/2001
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Publication #:
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Pub Dt:
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12/13/2001
| | | | |
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Title:
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Method and apparatus for deposition of porous silica dielectrics
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09864577
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Filing Dt:
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05/24/2001
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Publication #:
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Pub Dt:
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11/01/2001
| | | | |
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Title:
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WIRE BONDING TO COPPER
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09865124
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Filing Dt:
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05/24/2001
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
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Title:
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SEMICONDUCTOR DEVICE HAVING NON-POWER ENHANCED AND POWER ENHANCED METAL OXIDE SEMICONDUCTOR DEVICES AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09865900
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
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Title:
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SELF ALIGNED GATE
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09866137
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
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Title:
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SUPPRESSION OF SIDE-LOBE PRINTING BY SHAPE ENGINEERING
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09866661
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Filing Dt:
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05/30/2001
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Title:
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RTL CODE OPTIMIZATION FOR RESOURCE SHARING STRUCTURES
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09867202
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Filing Dt:
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05/29/2001
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Publication #:
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Pub Dt:
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01/10/2002
| | | | |
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Title:
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METHOD OF FORMING AN ALIGNMENT FEATURE IN OR ON A MULTI-LAYERED SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09870851
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Filing Dt:
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05/30/2001
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Title:
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SLOPED SIDEWALL VIA FOR INTEGRATED CIRCUIT STRUCTURE TO SUPPRESS VIA POISONING AND PROCESS FOR FORMING SAME
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09871129
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Filing Dt:
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05/31/2001
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Title:
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IC TIMING ANALYSIS WITH KNOWN FALSE PATHS
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09872058
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Filing Dt:
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05/31/2001
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Title:
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PROCESS FOR FORMING A LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL ON AN INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09873043
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Filing Dt:
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05/31/2001
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Title:
|
PROCESS FOR REMOVAL OF RESIST MASK OVER LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL OF AN INTEGRATED CIRCUIT STRUCTURE, AND REMOVAL OF RESIDUES FROM VIA ETCH AND RESIST MASK REMOVAL
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09873551
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Filing Dt:
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06/04/2001
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Publication #:
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Pub Dt:
|
10/18/2001
| | | | |
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Title:
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CIRCUIT AND METHOD FOR PROVIDING INTERCONNECTIONS AMONG INDIVIDUAL INTEGRATED CIRCUIT CHIPS IN A MULTI-CHIP MODULE
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09875314
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Filing Dt:
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06/04/2001
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Title:
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METHOD OF CLOCK BUFFER PARTITIONING TO MINIMIZE CLOCK SKEW FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09876522
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Filing Dt:
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06/07/2001
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Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
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Title:
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PRINTED WIRING BOARD HAVING A DISCONTINUOUS PLATING LAYER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09876736
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Filing Dt:
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06/06/2001
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Title:
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METHOD OF GENERATING AN OPTIMAL CLOCK BUFFER SET FOR MINIMIZING CLOCK SKEW IN BALANCED CLOCK TREES
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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09878499
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Filing Dt:
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06/11/2001
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Title:
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HARD MACRO HAVING AN ANTENNA RULE VIOLATION FREE INPUT/OUTPUT PORTS
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09878657
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Filing Dt:
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06/11/2001
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Publication #:
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Pub Dt:
|
10/11/2001
| | | | |
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Title:
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SEMICONDUCTOR DEVICE STRUCTURE INCLUDING A TANTALUM PENTOXIDE LAYER SANDWICHED BETWEEN SILICON NITRIDE LAYERS
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09878690
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Filing Dt:
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06/11/2001
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Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
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Title:
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METHOD OF FORMING A REVERSE GATE STRUCTURE WITH A SPIN ON GLASS PROCESS
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09878741
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Filing Dt:
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06/11/2001
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Title:
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OPTICAL INTENSITY MODIFIER
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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09878820
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Filing Dt:
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06/11/2001
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
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Title:
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PLASMA TREATMENT SYSTEM
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09879297
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Filing Dt:
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06/12/2001
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Title:
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RTL BACK ANNOTATOR
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09879380
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Filing Dt:
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06/12/2001
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Title:
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OPTIMAL CLOCK TIMING SCHEDULE FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09879417
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Filing Dt:
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06/12/2001
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Title:
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METHOD OF ANALYZING STATIC CURRENT TEST VECTORS WITH REDUCED FILE SIZES FOR SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09879506
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Filing Dt:
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06/12/2001
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Title:
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METHOD OF ANALYZING STATIC CURRENT TEST VECTORS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09879642
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Filing Dt:
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06/12/2001
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Title:
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METHOD AND APPRATUS FOR REMOVING PHOTORESIST EDGE BEADS FROM THIN FILM SUBSTRATES
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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09879643
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Filing Dt:
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06/12/2001
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Title:
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PROCESS FOR FAST CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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09879664
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Filing Dt:
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06/12/2001
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Title:
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MASK CORRECTION FOR PHOTOLITHOGRAPHIC PROCESSES
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09879783
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Filing Dt:
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06/12/2001
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Title:
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COMPOSITION WITH EMC SHIELDING CHARACTERISTICS
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09879841
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Filing Dt:
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06/12/2001
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Title:
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METHOD AND APPARATUS FOR OPTIMIZING THE TIMING OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09879845
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Filing Dt:
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06/12/2001
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Title:
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EPSILON-DISCREPANT SELF-TEST TECHNIQUE
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09879846
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Filing Dt:
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06/12/2001
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Title:
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MASK CORRECTION OPTIMIZATION
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09880607
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Filing Dt:
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06/12/2001
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Title:
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GENERATING STANDARD DELAY FORMAT FILES WITH CONDITIONAL PATH DELAY FOR DESIGNING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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09880675
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Filing Dt:
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06/13/2001
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Title:
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SCAN METHOD FOR BUILT-IN-SELF-REPAIR (BISR)
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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09881151
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Filing Dt:
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06/14/2001
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Title:
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CONVERTER DEVICE
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09882114
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Filing Dt:
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06/15/2001
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Title:
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METHOD OF CONTROL CELL PLACEMENT TO MINIMIZE CONNECTION LENGTH AND CELL DELAY
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09882124
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Filing Dt:
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06/14/2001
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Title:
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PROCESS FOR SELECTIVE POLISHING OF METAL-FILLED TRENCHES OF INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09882623
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Filing Dt:
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06/15/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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METHOD OF CONVERTING A METAL OXIDE SEMICONDUCTOR TRANSISTOR INTO A BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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09882624
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Filing Dt:
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06/15/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SEMICONDUCTOR DEVICE HAVING AT LEAST ONE SOURCE/DRAIN REGION FORMED ON AN ISOLATION REGION AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09882899
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Filing Dt:
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06/15/2001
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Title:
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METHOD FOR REDUCING SIMULATION OVERHEAD FOR EXTERNAL MODELS
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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09882911
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Filing Dt:
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06/15/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SEMICONDUCTOR DEVICE HAVING A GHOST SOURCE/DRAIN REGION AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09882961
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Filing Dt:
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06/15/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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FORMATION OF SILICON ON INSULATOR (SOI) DEVICES AS ADD-ON MODULES FOR SYSTEM ON A CHIP PROCESSING
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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09883733
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Filing Dt:
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06/18/2001
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Title:
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PSEUDO-RANDOM ONE-TO-ONE CIRCUIT SYNTHESIS
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09884711
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Filing Dt:
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06/18/2001
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Title:
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UNIVERSAL TEST COUPON FOR PERFORMING PREQUALIFICATION TESTS ON SUBSTRATES
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09884736
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Filing Dt:
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06/19/2001
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Title:
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PLASMA TREATMENT OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL TO FORM STRUCTURES USEFUL IN FORMATION OF METAL INTERCONNECTS AND/OR FILLED VIAS FOR INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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09884805
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Filing Dt:
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06/18/2001
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Publication #:
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Pub Dt:
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11/01/2001
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Title:
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CONFINEMENT DEVICE FOR USE IN DRY ETCHING OF SUBSTRATE SURFACE AND METHOD OF DRY ETCHING A WAFER SURFACE
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09885299
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Filing Dt:
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06/20/2001
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Title:
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HIGH DENSITY SIGNAL ROUTING
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09885491
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Filing Dt:
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06/20/2001
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Title:
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SPLITTING AND ASSIGNING POWER PLANES
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09885497
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Filing Dt:
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06/19/2001
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Title:
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METHOD OF SHALLOW TRENCH ISOLATION FORMATION AND PLANARIZATION
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09885589
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Filing Dt:
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06/19/2001
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Title:
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METHOD IN INTEGRATING CLOCK TREE SYNTHESIS AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09885596
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Filing Dt:
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06/19/2001
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Title:
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METHOD OF GLOBAL PLACEMENT OF CONTROL CELLS AND HARDMAC PINS IN A DATAPATH MACRO FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09885687
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Filing Dt:
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06/19/2001
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Title:
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SEMICONDUCTOR DEVICE PACKAGE SUBSTRATE PROBE FIXTURE
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09885896
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Filing Dt:
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06/20/2001
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Title:
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MODULAR COLLECTION OF SPARE GATES FOR USE IN HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09886780
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Filing Dt:
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06/21/2001
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Publication #:
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Pub Dt:
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11/01/2001
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Title:
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INTEGRATED CIRCUIT HAVING A MICROMAGNETIC DEVICE AND METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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09887131
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Filing Dt:
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06/22/2001
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Title:
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PROCESS INDEPENDENT ALIGNMENT MARKS
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09887938
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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FERRITE FILM FORMATION METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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09888302
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Filing Dt:
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06/21/2001
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Title:
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WAFER HOLDER FOR BACKSIDE VIEWING FRONTSIDE PROBING ON AUTOMATED WAFER PROBE STATIONS
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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09888493
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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AUTOMATIC HANDOFF FOR WIRELESS PICONET MULTIMODE CELL PHONE
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09892241
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Filing Dt:
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06/26/2001
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Title:
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METHOD OF CONTROL CELL PLACEMENT FOR DATAPATH MACROS IN INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09892250
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Filing Dt:
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06/27/2001
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Title:
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH LOW DIELECTRIC CONSTANT MATERIAL BETWEEN CLOSELY SPACED APART METAL LINES
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09894116
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Filing Dt:
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06/28/2001
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Publication #:
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Pub Dt:
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11/01/2001
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Title:
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POLISHING FLUID, POLISHING METHOD, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD
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