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04/22/1997
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08332179
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Filing Dt:
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10/31/1994
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ELECTRON FIELD EMITTERS COMPRISING PARTICLES COATED WITH LOW VOLTAGE EMITTING MATERIAL
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04/09/1996
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08333168
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11/02/1994
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Title:
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11/26/1996
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08333367
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Filing Dt:
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11/02/1994
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Title:
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08/12/1997
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08344318
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Filing Dt:
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11/22/1994
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Title:
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11/19/1996
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08344785
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Filing Dt:
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11/22/1994
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Title:
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SINGLE-POLYSILICON CMOS ACTIVE PIXEL
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10/31/1995
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08346444
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Filing Dt:
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11/29/1994
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Title:
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SUBSTRATES AND METHODS FOR GAS PHASE DEPOSITION OF SEMICONDUCTORS AND OTHER MATERIALS
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Issue Dt:
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12/10/1996
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08346454
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Filing Dt:
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11/29/1994
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Title:
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METHOD FOR DETECTING A COATING MATERIAL ON A SUBSTRATE
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Issue Dt:
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07/09/1996
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08346706
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Filing Dt:
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11/30/1994
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Title:
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AREA-EFFICIENT LAYOUT FOR HIGH VOLTAGE LATERAL DEVICES
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Issue Dt:
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08/27/1996
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08346806
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Filing Dt:
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11/30/1994
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Title:
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MINIENVIRONMENT FOR HAZARDOUS PROCESS TOOLS
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Patent #:
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Issue Dt:
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08/15/1995
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08346810
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Filing Dt:
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11/30/1994
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Title:
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METHOD AND APPARATUS FOR PLANAR MAGNETRON SPUTTERING
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Patent #:
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Issue Dt:
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09/03/2002
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08347527
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Filing Dt:
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11/30/1994
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Title:
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PROCESS FOR FORMING ISOLATION REGIONS IN AN INTEGRATED CIRCUIT AND STRUCTURE FORMED THEREBY
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Issue Dt:
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06/04/1996
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08349649
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Filing Dt:
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12/05/1994
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Title:
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METHOD OF FORMING METAL LAYERS FORMED AS A COMPOSITE OF SUB-LAYERS USING TI TEXTURE CONTROL LAYER
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Issue Dt:
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08/13/1996
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08350439
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Filing Dt:
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12/06/1994
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Title:
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HIGH Q INTEGRATED INDUCTOR
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Patent #:
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Issue Dt:
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05/06/1997
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08351516
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12/07/1994
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Title:
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METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
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02/04/1997
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08351977
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12/08/1994
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Title:
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POLY-BUFFERED LOCOS
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Patent #:
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Issue Dt:
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11/19/1996
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08353015
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Filing Dt:
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12/09/1994
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Title:
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METHOD FOR MAKING A METAL TO METAL CAPACITOR
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Patent #:
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Issue Dt:
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11/12/1996
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08353032
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Filing Dt:
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12/09/1994
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Title:
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ARTICLE COMPRISING A THIN FILM TRANSISTOR WITH LOW CONDUCTIVITY ORGANIC LAYER
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Issue Dt:
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09/23/1997
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08355787
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12/14/1994
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Title:
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METHODOLOGY FOR MONITORING SOLVENT QUALITY
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07/29/1997
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08357728
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Filing Dt:
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12/13/1994
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Title:
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USE OF RETICLE STITCHING TO PROVIDE DESIGN FLEXIBILITY
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Issue Dt:
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09/24/1996
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08359309
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Filing Dt:
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12/19/1994
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Title:
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INDUCTOR FOR HIGH FREQUENCY CIRCUITS
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03/04/1997
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08359973
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12/20/1994
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Title:
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MULTI-COMPONENT ELECTRONIC DEVICES AND METHODS FOR MAKING THEM
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01/20/1998
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08361616
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12/22/1994
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Title:
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METHOD OF MAKING FIELD EMISSION DEVICES EMPLOYING ULTRA-FINE DIAMOND PARTICLE EMITTERS
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Issue Dt:
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07/23/1996
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08362616
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Filing Dt:
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12/22/1994
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Title:
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INTEGRATED CIRCUIT FABRICATION
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Patent #:
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Issue Dt:
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12/05/1995
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Application #:
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08365264
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Filing Dt:
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12/28/1994
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Title:
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METHOD AND APPARATUS FOR TESTING LARGE EMBEDDED COUNTERS
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Patent #:
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Issue Dt:
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04/30/1996
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08365394
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Filing Dt:
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12/28/1994
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Title:
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METHOD FOR BUILT-IN SELF-TESTING OF RING-ADDRESS FIFOS
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Patent #:
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Issue Dt:
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10/01/1996
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Application #:
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08365652
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Filing Dt:
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12/29/1994
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Title:
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METHOD OF MAKING MULTILAYERED A1-ALLOY STRUCTURE FOR METAL CONDUCTORS
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Issue Dt:
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09/24/1996
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Application #:
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08366192
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Filing Dt:
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12/29/1994
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Title:
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INTEGRATED CIRCUIT FABRICATION WITH INTERLEVEL DIELECTRIC
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Patent #:
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Issue Dt:
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07/02/1996
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Application #:
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08366515
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Filing Dt:
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12/30/1994
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Title:
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REVERSE SIDE ETCHING FOR PRODUCING LAYERS WITH STRAIN VARIATION
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Issue Dt:
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02/06/1996
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Application #:
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08366529
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Filing Dt:
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12/30/1994
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Title:
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MULTIPLE LAYER TUNGSTEN DEPOSITION PROCESS
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Patent #:
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Issue Dt:
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03/26/1996
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Application #:
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08366539
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Filing Dt:
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12/30/1994
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Title:
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METHOD FOR TESTING SOLDER MASK MATERIAL
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Issue Dt:
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02/04/1997
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08366867
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12/30/1994
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Title:
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NOVEL BARRIER LAYER TREATMENTS FOR TUNGSTEN PLUG
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Patent #:
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Issue Dt:
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12/31/1996
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Application #:
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08366952
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Filing Dt:
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12/30/1994
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Title:
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SELF-ALIGNED OPAQUE REGIONS FOR ATTENUATING PHASE-SHIFTING MASKS
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Issue Dt:
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09/09/1997
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08367556
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01/03/1995
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Title:
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PROGRAMMABLE MICROSYSTEMS IN SILICON
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Issue Dt:
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07/09/1996
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08370902
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01/10/1995
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Title:
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METHOD FOR MAKING MULTICHIP CIRCUITS USING ACTIVE SEMICONDUCTOR SUBSTRATES
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Issue Dt:
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05/20/1997
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08373732
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01/17/1995
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Title:
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LASER-ASSISTED PARTICLE ANALYSIS
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07/08/1997
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08374193
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01/18/1995
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PROCESS FOR SELECTIVE DEPOSITION OF POLYSILICON OVER SINGLE CRYSTAL SILICON SUBSTRATE AND RESULTING PRODUCT
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01/28/1997
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08374195
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01/18/1995
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Title:
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IMPROVED MOS STRUCTURE WITH HOT CARRIER REDUCTION ME
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07/01/1997
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08377844
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01/25/1995
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Title:
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TIMING SHELL GENERATION THROUGH NETLIST REDUCTION
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02/04/1997
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08378027
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01/24/1995
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Title:
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BARRIER METAL TECHNOLOGY FOR TUNGSTEN PLUG INTERCONNECTION
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01/02/1996
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08378435
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01/26/1995
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METHOD AND APPARATUS FOR TESTING LONG COUNTERS
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03/25/1997
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08378750
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01/26/1995
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METHOD FOR FABRICATING RELIABLE METALLIZATION WITH TA-SI-N BARRIER FOR SEMICONDUCTORS
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10/01/1996
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08379052
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01/27/1995
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Title:
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PROCESS FOR DEVICE FABRICATION USING PROJECTION LITHOGRAPHY AND AN APPARATUS THEREFOR
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01/28/1997
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08380774
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01/31/1995
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Title:
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MULTILAYER PILLAR STRUCTURE FOR IMPROVED FIELD EMISSION DEVICES
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Issue Dt:
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10/01/1996
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08381262
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01/31/1995
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Title:
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FIELD EMISSION DISPLAY HAVING CORRUGATED SUPPORT PILLARS AND METHOD FOR MANUFACTURING
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04/01/1997
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08381375
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01/31/1995
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FIELD EMISSION DEVICES EMPLOYING ACTIVATED DIAMOND PARTICLE EMITTERS AND METHODS FOR MAKING SAME
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Issue Dt:
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10/15/1996
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08387154
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02/10/1995
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Title:
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SEMICONDUCTOR BOND PAD STRUCTURE AND INCREASED BOND PAD COUNT PER DIE
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03/04/1997
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08388934
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02/15/1995
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Title:
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METHOD AND ARRANGEMENT FOR CHARACTERIZING MICRO-SIZE PATTERNS
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10/28/1997
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08390329
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02/17/1995
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Title:
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FILTERING TECHNIQUE FOR CVD CHAMBER PROCESS GASES
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Issue Dt:
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08/12/1997
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08391905
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02/21/1995
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Title:
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PROCESS FOR FABRICATING A DEVICE IN WHICH THE PROCESS IS CONTROLLED BY NEAR-FIELD IMAGING LATENT FEATURES INTRODUCED INTO ENERGY SENSITIVE RESIST MATERIALS
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08/19/1997
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08393494
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03/02/1995
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Title:
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ARTICLE COMPRISING ALPHA-HEXATHIENYL
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03/04/1997
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08393628
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02/24/1995
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Title:
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PACKAGING MULTI-CHIP MODULES WITHOUT WIRE-BOND INTERCONNECTION
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12/21/1999
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08396541
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03/01/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING HEXAGONAL CMOS "NAND" GATE DEVICE
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Issue Dt:
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08/12/1997
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08396542
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03/01/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING HEXAGONAL SEMICONDUCTOR "AND" GATE DEVICE
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Issue Dt:
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07/23/1996
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08396560
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03/01/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING HEXAGONAL SEMICONDUCTOR "OR" GATE DEVICE
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02/24/1998
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08397346
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03/02/1995
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Title:
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SEMICONDUCTOR DEVICE WITH INCREASED PARASITIC EMITTER RESISTANCE AND IMPROVED LATCH-UP IMMUNITY
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10/28/1997
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08401099
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03/06/1995
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SYSTEM AND METHOD FOR PERFORMING OPTICAL PROXIMITY CORRECTION ON MACROCELL LIBRARIES
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02/05/2002
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08409191
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03/23/1995
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Title:
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SYNTHESIS SHELL GENRATION AND USE IN ASIC DESIGN
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08/26/1997
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08409757
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03/24/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND METHOD USING HIERARCHICAL CLUSTERIZATION AND PLACEMENT IMPROVEMENT BASED ON COMPLETE RE-PLACEMENT OF CELL CLUSTERS
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06/27/2000
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08410375
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03/27/1995
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BICMOS COMPACTED LOGIC ARRAY
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03/11/1997
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08412087
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03/27/1995
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Title:
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SEMICONDUCTOR DEVICE PACKAGE FABRICATION METHOD AND APPARATUS
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Issue Dt:
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12/31/1996
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08412678
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03/29/1995
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Title:
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METHOD FOR SUPPLYING PHOSPHOROUS VAPOR
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Issue Dt:
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09/02/1997
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08413527
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03/30/1995
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Title:
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INTEGRATED CIRCUIT MULTI-LEVEL INTERCONNECTION TECHNIQUE
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07/02/1996
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08416457
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04/03/1995
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Title:
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FLOORPLANNING TECHNIQUE USING MULTI-PARTITIONING BASED ON A PARTITION COST FACTOR FOR NON-SQUARE SHAPED PARTITONS
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11/06/2001
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08424828
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04/19/1995
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Title:
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SUPPORT FOR SEMICONDUCTOR BOND WIRES
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Issue Dt:
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10/29/1996
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08428323
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04/25/1995
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PREFORMED PLANAR STRUCTURES FOR SEMICONDUCTOR DEVICE ASSEMBLIES
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09/17/1996
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08429605
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04/27/1995
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Title:
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OVERMOLDED SEMICONDUCTOR PACKAGE
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Issue Dt:
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04/06/1999
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08430084
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04/27/1995
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Title:
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TRANSISTOR FABRICATION METHOD
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Issue Dt:
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06/03/1997
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08430399
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04/28/1995
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Title:
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HIGH DENSITY BOND PAD LAYOUT ARRANGEMENTS FIR SEMICONDUCTOR DIES, AND CONNECTING TO THE BOND PADS
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05/06/1997
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08430664
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04/28/1995
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Title:
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ELECTRONIC PACKAGE WITH REDUCED BENDING STRESS
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04/08/1997
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08430665
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04/28/1995
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Title:
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EXTERNALLY BONDABLE OVERMOLDED PACKAGE ARRANGEMENTS
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Issue Dt:
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03/04/1997
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08431341
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04/28/1995
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Title:
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INTEGRATED CIRCUIT ETCHING
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Patent #:
|
|
Issue Dt:
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04/15/1997
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Application #:
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08431355
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Filing Dt:
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04/28/1995
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Title:
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REDUCED STRESS TUNGSTEN DEPOSITION
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08432535
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Filing Dt:
|
05/02/1995
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Title:
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PARTIALLY-MOLDED, PCB CHIP CARRIER PACKAGE FOR CERTAIN NON-SQUARE DIE SHAPES
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Patent #:
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Issue Dt:
|
12/23/1997
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Application #:
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08434276
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Filing Dt:
|
05/03/1995
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Title:
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PROCESS FOR MOUNTING A SEMICONDUCTOR DEVICE TO A CIRCUIT SUBBSTRATE
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|
|
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Patent #:
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|
Issue Dt:
|
04/08/1997
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Application #:
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08434660
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Filing Dt:
|
05/04/1995
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|
Title:
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SEMICONDUCTOR CELL HAVING A VARIABLE TRANSISTOR WIDTH
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|
|
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Patent #:
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|
Issue Dt:
|
08/05/1997
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Application #:
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08434673
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Filing Dt:
|
05/04/1995
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|
Title:
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PROCESS FOR MAKING GROUP IV SEMICONDUCTOR SUBSTRATE TREATED WITH ONE OR MORE GROUP IV ELEMENTS TO FORM ONE OR MORE BARRIER REGIONS CAPABLE OF INHIBITING MIGRATION OF DOPANT MATERILS IN SUBSTRATE
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Patent #:
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|
Issue Dt:
|
01/13/1998
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Application #:
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08434674
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Filing Dt:
|
05/04/1995
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|
Title:
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OXIDE FORMED IN SEMICONDUCTOR SUBSTRATE BY IMPLANTATION OF SUBSTRATE WITH A NOBLE GAS PRIOR TO OXIDATION
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|
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Patent #:
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|
Issue Dt:
|
04/22/1997
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Application #:
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08438296
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Filing Dt:
|
05/10/1995
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|
Title:
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BONDING SCHEME USING GROUP VB METALLIC LAYER
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|
|
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Patent #:
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|
Issue Dt:
|
07/23/1996
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Application #:
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08439040
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Filing Dt:
|
04/10/1995
|
|
Title:
|
SELF-ALIGNED ALIGNMENT MARKS FOR PHASE-SHIFTING MASKS
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|
|
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Patent #:
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|
Issue Dt:
|
08/21/2001
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Application #:
|
08441142
|
Filing Dt:
|
05/15/1995
|
|
Title:
|
ARTICLE COMPRISING AN ORGANIC THIN FILM TRANSISTOR ADAPTED FOR BIASING TO FORM A N-TYPE OR A P-TYPE TRANSISTOR
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|
|
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Patent #:
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Issue Dt:
|
06/16/1998
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Application #:
|
08441539
|
Filing Dt:
|
05/15/1995
|
|
Title:
|
METHOD OF CALCULATING MACROCELL POWER AND DELAY VALUES
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/05/1997
|
Application #:
|
08446122
|
Filing Dt:
|
05/19/1995
|
|
Title:
|
ACTIVE NEURAL NETWORK DETERMINATION OF ENDPOINT IN A PLASMA ETCH PROCESS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/27/1999
|
Application #:
|
08451177
|
Filing Dt:
|
05/26/1995
|
|
Title:
|
AUTOMATED GENERATION OF MEGACELLS IN AN INTEGRATED CIRCUIT DESIGN SYSTEM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08451283
|
Filing Dt:
|
05/26/1995
|
|
Title:
|
PROCESS FOR DRY LITHOGRAPHIC ETCHING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/01/1997
|
Application #:
|
08454542
|
Filing Dt:
|
05/30/1995
|
|
Title:
|
METHOD FOR PROTECTING A SEMICONDUCTOR DEVICE WITH A SUPERCONDUCTIVE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08454976
|
Filing Dt:
|
05/31/1995
|
|
Title:
|
PROCESS OF MANUFACTURING AN INTERGRATED CIRCUIT HAVING AN INTERFERO- METRICALLY PROFILED MOUNTING FILM
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
06/11/1996
|
Application #:
|
08463064
|
Filing Dt:
|
06/05/1995
|
|
Title:
|
RELIABLE METALLIZATION WITH BARRIER FOR SEMICONDUCTORS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/07/1998
|
Application #:
|
08468167
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
ACTIVE NEURAL NETWORK CONTROL OF WAFER ATTRIBUTES IN A PLASMA ETCH PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08470945
|
Filing Dt:
|
06/05/1995
|
|
Title:
|
SEMICONDUCTOR DEVICE ASSEMBLY TECHNIQUES USING PREFORMED PLANAR STRUCTURES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08472033
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
INTEGRATED CIRCUIT CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08473543
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
LAYOUT CONFIGURATION FOR AN INTEGRATED CIRCUIT GATE ARRAY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/1997
|
Application #:
|
08474794
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
METHOD OF MAKING SELF-ALIGNED REMOTE POLYSILICON CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1997
|
Application #:
|
08475028
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
METHOD OF FORMING AN MOS-TYPE INTEGRATED CIRCUIT STRUCTURE WITH A DIODE FORMED IN THE SUBSTRATE UNDER A POLYSILICON GATE ELECTRODE TO CONSERVE SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08475110
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SUBSTRATES AND METHODS FOR GAS PHASE DEPOSITION OF SEMICONDUCTORS AND OTHER MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08475586
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SILICON CONTROLLED RECTIFIER (SCR) WITH CAPACITIVE TRIGGER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08476431
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
NON-SQUARE DIE FOR INTEGRATED CIRCUITS AND SYSTEMS CONTAINING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/1997
|
Application #:
|
08477490
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
CONFIGURATION MANAGEMENT AND AUTOMATED TEST SYSTEM FOR ASIC DESIGN SOFTWARE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08477827
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
OPTICAL CORRECTIVE TECHNIQUES WITH RETICLE FORMATION AND RETICLE STITCHING TO PROVIDE DESIGN FLEXIBILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/1998
|
Application #:
|
08478133
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
METHD OF MAKING PMOSFETS HAVING INDIUM OR GALLIUM DOPED BURIED CHAN- NELS AND N+POLYSILICON GATES AND CMOS DEVICES FABRICATED THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1997
|
Application #:
|
08479018
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING PN JUNCTIONS SEPARATED BY DEPRESSIONS
|
|
