|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10306067
|
Filing Dt:
|
11/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
FIRST APPROXIMATION FOR OPC SIGNIFICANT SPEED-UP
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10306565
|
Filing Dt:
|
11/27/2002
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|
Publication #:
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|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10307018
|
Filing Dt:
|
11/27/2002
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|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
FAILURE ANALYSIS VEHICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10308557
|
Filing Dt:
|
12/03/2002
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|
Publication #:
|
|
Pub Dt:
|
12/25/2003
| | | | |
|
Title:
|
EFFECTIVE APPROXIMATED CALCULATION OF SMOOTH FUNCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10313333
|
Filing Dt:
|
12/06/2002
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|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
PROCESS TO MINIMIZE POLYSILICON GATE DEPLETION AND DOPANT PENETRATION AND TO INCREASE CONDUCTIVITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10315480
|
Filing Dt:
|
12/09/2002
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|
Title:
|
CONTAMINATION DISTRIBUTION APPARATUS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10316386
|
Filing Dt:
|
12/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
PROCESS FOR OXIDE FABRICATION USING OXIDATION STEPS BELOW AND ABOVE A THRESHOLD TEMPERATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10316594
|
Filing Dt:
|
12/11/2002
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|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
|
Title:
|
ESTIMATING FREE SPACE IN IC CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10317147
|
Filing Dt:
|
12/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2003
| | | | |
|
Title:
|
METHOD OF VERIFYING IC MASK SETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10318623
|
Filing Dt:
|
12/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
|
Title:
|
AUTOMATED SELECTION AND PLACEMENT OF MEMORY DURING DESIGN OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10318639
|
Filing Dt:
|
12/13/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
|
Title:
|
METHOD FOR CREATING DERIVATIVE INTEGRATED CIRCUIT LAYOUTS FOR RELATED PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10321250
|
Filing Dt:
|
12/16/2002
|
|
Title:
|
SENICONDUCTOR WAFER ARRANGEMENT OF A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10321938
|
Filing Dt:
|
12/16/2002
|
|
Title:
|
DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10322974
|
Filing Dt:
|
12/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
Substrate processing system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10324698
|
Filing Dt:
|
12/20/2002
|
|
Title:
|
METHOD FOR THE FORMATION OF ACTIVE AREA UTILIZING REVERSE TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10326717
|
Filing Dt:
|
12/19/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
METHOD FOR COMBINING STATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10327283
|
Filing Dt:
|
12/19/2002
|
|
Title:
|
DIAMOND METAL-FILLED PATTERNS ACHIEVING LOW PARASITIC COUPLING CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10327304
|
Filing Dt:
|
12/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR CLASSIFYING AN INTEGRATED CIRCUT FOR OPTICAL PROXIMITY CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10327314
|
Filing Dt:
|
12/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR CONSTRUCTING A HIERARCHY-DRIVEN CHIP COVERING FOR OPTICAL PROXIMITY CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10327333
|
Filing Dt:
|
12/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
MULTI-LEVEL REDISTRIBUTION LAYER TRACES FOR REDUCING CURRENT CROWDING IN FLIPCHIP SOLDER BUMPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2000
|
Application #:
|
10327451
|
Filing Dt:
|
12/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
SIDELOBE CORRECTION FOR ATTENUATED PHASE SHIFT MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10327452
|
Filing Dt:
|
12/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
ADAPTIVE SEM EDGE RECOGNITION ALGORITHM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
10328066
|
Filing Dt:
|
12/23/2002
|
|
Title:
|
IN-SITU METROLOGY SYSTEM AND METHOD FOR MONITORING METALIZATION AND OTHER THIN FILM FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10328333
|
Filing Dt:
|
12/23/2002
|
|
Title:
|
DUAL DAMASCENE INTERCONNECT STRUCTURE WITH IMPROVED ELECTRO MIGRATION LIFETIMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10328346
|
Filing Dt:
|
12/24/2002
|
|
Title:
|
CHROMELESS PHASE SHIFT MASK USING NON-LINEAR OPTICAL MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10328614
|
Filing Dt:
|
12/23/2002
|
|
Title:
|
LOW K POLYMER E-BEAM PRINTABLE MECHANICAL SUPPORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
10330929
|
Filing Dt:
|
12/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
PROCESS WINDOW COMPLIANT CORRECTIONS OF DESIGN LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10331521
|
Filing Dt:
|
12/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR VISUALIZING AND ANALYZING RESISTANCE NETWORKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10334430
|
Filing Dt:
|
12/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
OPTIMIZATION OF DIE YIELD IN A SILICON WAFER "SWEET SPOT"
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10334568
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
PLACEMENT OF CONFIGURABLE INPUT/OUTPUT BUFFER STRUCTURES DURING DESIGN OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10334570
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
LENGTH MATRIX GENERATOR FOR REGISTER TRANSFER LEVEL CODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10334731
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
NETLIST REDUNDANCY DETECTION AND GLOBAL SIMPLIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10334743
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
CONGESTION ESTIMATION FOR REGISTER TRANSFER LEVEL CODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10335177
|
Filing Dt:
|
12/31/2002
|
|
Title:
|
MODULAR GROWTH OF MULTIPLE GATE OXIDES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10335360
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
SIMPLIFIED PROCESS TO DESIGN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10335470
|
Filing Dt:
|
12/31/2002
|
|
Title:
|
INTERCONNECT ROUTING USING PARALLEL LINES AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10335540
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
BUILT-IN SELF-TEST HIERARCHY FOR AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10339821
|
Filing Dt:
|
01/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
SPLIT AND MERGE DESIGN FLOW CONCEPT FOR FAST TURNAROUND TIME OF CIRCUIT LAYOUT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10339844
|
Filing Dt:
|
01/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
DONUT POWER MESH SCHEME FOR FLIP CHIP PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10341082
|
Filing Dt:
|
01/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
BOND PAD DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10341119
|
Filing Dt:
|
01/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
METHOD FOR IMPROVING OPC MODELING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
10347759
|
Filing Dt:
|
01/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
ELECTRONIC ORGANIC SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10349564
|
Filing Dt:
|
01/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
NET SEGMENT ANALYZER FOR CHIP CAD LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10349770
|
Filing Dt:
|
01/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
SIMULATED VOLTAGE CONTRAST IMAGE GENERATOR AND COMPARATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10357142
|
Filing Dt:
|
02/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
DIELECTRIC STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10358968
|
Filing Dt:
|
02/04/2003
|
|
Title:
|
ALTERNATING APERTURE PHASE-SHIFT MASK FABRICATION METHOD
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10360276
|
Filing Dt:
|
02/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
|
Title:
|
Process for oxide fabrication using oxidation steps below and above a threshold temperature
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10360746
|
Filing Dt:
|
02/05/2003
|
|
Title:
|
METHOD FOR PREVENTING BORDERLESS CONTACT TO WELL LEAKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10360903
|
Filing Dt:
|
02/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
METHOD TO USE A LASER TO PERFORM THE EDGE CLEAN OPERATION ON A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10368520
|
Filing Dt:
|
02/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
METHODS AND STRUCTURE FOR IC TEMPERATURE SELF-MONITORING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10368760
|
Filing Dt:
|
02/18/2003
|
|
Title:
|
METHOD FOR CREATING SELF-ALIGNED ALLOY CAPPING LAYERS FOR COPPER INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10368811
|
Filing Dt:
|
02/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
|
Title:
|
SILICON GERMANIUM CMOS CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10368812
|
Filing Dt:
|
02/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ENHANCING IMAGE CONTRAST USING INTENSITY FILTRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10369269
|
Filing Dt:
|
02/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
A MODE REGISTER IN AN INTEGRATED CIRCUIT THAT STORES TEST SCRIPTS AND OPERATING PARAMETERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10370137
|
Filing Dt:
|
02/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
FLIP-COVER SENSOR FOR KEYPAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
10370812
|
Filing Dt:
|
02/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2003
| | | | |
|
Title:
|
APPARATUS FOR WASHING DRUMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10371386
|
Filing Dt:
|
02/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
SUBSTRATE IMPEDANCE MEASUREMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10382036
|
Filing Dt:
|
03/05/2003
|
|
Publication #:
|
|
Pub Dt:
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09/09/2004
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Title:
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METHOD FOR EVALUATING LOGIC FUNCTIONS BY LOGIC CIRCUITS HAVING OPTIMIZED NUMBER OF AND/OR SWITCHES
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10382142
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Filing Dt:
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03/05/2003
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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DIFFUSED MOS DEVICES WITH STRAINED SILICON PORTIONS AND METHODS FOR FORMING SAME
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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10382709
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Filing Dt:
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03/06/2003
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Publication #:
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Pub Dt:
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08/21/2003
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Title:
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CAPACITOR WITH STOICHIOMETRICALLY ADJUSTED DIELECTRIC AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10383031
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Filing Dt:
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03/06/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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INTEGRATED CIRCUIT ISOLATION SYSTEM
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10383149
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Filing Dt:
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03/06/2003
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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LOCAL INTERCONNECT FOR INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10387846
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Filing Dt:
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03/13/2003
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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MICROMAGNETIC DEVICE FOR POWER PROCESSING APPLICATIONS AND METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10387988
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Filing Dt:
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03/13/2003
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Publication #:
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Pub Dt:
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09/16/2004
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Title:
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SEQUENTIAL TESTER FOR LONGEST PREFIX SEARCH ENGINES
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10392206
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Filing Dt:
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03/19/2003
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Publication #:
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Pub Dt:
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09/23/2004
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Title:
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METHOD AND INTEGRATED CIRCUIT FOR CAPACITOR MEASUREMENT WITH DIGITAL READOUT
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10394445
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Filing Dt:
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03/20/2003
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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HIGH SPEED WAFER SORT AND FINAL TEST
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10396955
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Filing Dt:
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03/24/2003
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Publication #:
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Pub Dt:
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09/30/2004
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Title:
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LOW STRESS FLIP-CHIP PACKAGE FOR LOW-K SILICON TECHNOLOGY
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10397451
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Filing Dt:
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03/25/2003
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Title:
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HIGH-K DIELECTRIC BIRD'S BEAK OPTIMIZATIONS USING IN-SITU O2 PLASMA OXIDATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10397993
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Filing Dt:
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03/25/2003
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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A low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10400252
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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LOW VIA RESISTANCE SYSTEM
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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10400278
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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01/29/2004
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Title:
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METAL PLANARIZATION SYSTEM
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10400279
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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LOCAL INTERCONNECT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10400281
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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Ion beam dual damascene process
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10400297
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Filing Dt:
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03/26/2003
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Title:
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VIA AND METAL LINE INTERFACE CAPABLE OF REDUCING THE INCIDENCE OF ELECTRO-MIGRATION INDUCED VOIDS
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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10400310
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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REDUCED PARTICULATE ETCHING
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10402054
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Filing Dt:
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03/28/2003
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Title:
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INTEGRATED CIRCUIT HAVING ADAPTABLE CORE AND INPUT/OUTPUT REGIONS WITH MULTI-LAYER PAD TRACE CONDUCTORS
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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10404832
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Filing Dt:
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04/01/2003
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Publication #:
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Pub Dt:
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10/07/2004
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH CONSTRICTED CURRENT PASSAGE
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10405666
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Filing Dt:
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04/02/2003
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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CARBON-DOPED HARD MASK AND METHOD OF PASSIVATING STRUCTURES DURING SEMICONDUCTOR DEVICE FABRICATION
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10406847
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Filing Dt:
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04/04/2003
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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CHROMELESS PHASE SHIFT MASK
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10407065
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Filing Dt:
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04/03/2003
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS
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Patent #:
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Issue Dt:
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07/26/2005
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Application #:
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10408205
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Filing Dt:
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04/04/2003
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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SYSTEM AND METHOD FOR ACHIEVING TIMING CLOSURE IN FIXED PLACED DESIGNS AFTER IMPLEMENTING LOGIC CHANGES
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10409423
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Filing Dt:
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04/08/2003
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Publication #:
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Pub Dt:
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09/11/2003
| | | | |
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION IN DOUBLE DIFFUSED MOS TRANSISTORS
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10409499
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Filing Dt:
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04/08/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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ANALOG CAPACITOR IN DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10409859
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Filing Dt:
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04/09/2003
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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WAFER BLADE CONTACT MONITOR
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10410925
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Filing Dt:
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04/09/2003
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Title:
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MECHANICAL STRESS FREE PROCESSING METHOD
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10412867
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Filing Dt:
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04/14/2003
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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MODIFIED BINARY SEARCH FOR OPTIMIZING EFFICIENCY OF DATA COLLECTION TIME
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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10413051
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Filing Dt:
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04/14/2003
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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HIGH K GATE INSULATOR REMOVAL
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10414601
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Filing Dt:
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04/15/2003
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Title:
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DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10417007
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Filing Dt:
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04/16/2003
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Publication #:
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Pub Dt:
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11/04/2004
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Title:
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EXTENSIBLE IO TESTING IMPLEMENTATION
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10417049
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Filing Dt:
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04/16/2003
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Publication #:
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Pub Dt:
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10/21/2004
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Title:
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WAFER-MOUNTED MICRO-PROBING PLATFORM
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10417706
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Filing Dt:
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04/17/2003
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
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Title:
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METHOD FOR REDUCING RETICLE SET COST
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|
|
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Patent #:
|
|
Issue Dt:
|
06/06/2006
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Application #:
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10417708
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Filing Dt:
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04/16/2003
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Title:
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WAFER CHUCKING APPARATUS AND METHOD FOR SPIN PROCESSOR
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|
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Patent #:
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Issue Dt:
|
01/03/2006
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Application #:
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10418375
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Filing Dt:
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04/18/2003
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
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Title:
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ION RECOIL IMPLANTATION AND ENHANCED CARRIER MOBILITY IN CMOS DEVICE
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|
|
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Patent #:
|
|
Issue Dt:
|
03/01/2005
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Application #:
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10418560
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Filing Dt:
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04/16/2003
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
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Title:
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SELF-TIMED RELIABILITY AND YIELD VEHICLE ARRAY
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|
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Patent #:
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Issue Dt:
|
07/27/2004
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Application #:
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10420219
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Filing Dt:
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04/22/2003
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|
Title:
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DUAL CLOCK PACKAGE OPTION
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|
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Patent #:
|
|
Issue Dt:
|
04/18/2006
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Application #:
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10421068
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Filing Dt:
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04/23/2003
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
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Title:
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PLANARIZATION WITH REDUCED DISHING
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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10421421
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Filing Dt:
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04/23/2003
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Publication #:
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Pub Dt:
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10/28/2004
| | | | |
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Title:
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VISUAL WEAR CONFIRMATION POLISHING PAD
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|
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10422270
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Filing Dt:
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04/24/2003
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Publication #:
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Pub Dt:
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11/06/2003
| | | | |
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Title:
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PLASMA TREATMENT OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL TO FORM STRUCTURES USEFUL IN FORMATION OF METAL INTERCONNECTS AND/OR FILLED VIAS FOR INTERGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10423096
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Filing Dt:
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04/25/2003
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Title:
|
PAD CONDITIONING MONITOR
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|
|
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Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10423184
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Filing Dt:
|
04/25/2003
|
|
Title:
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METHOD FOR INCORPORATING GERMANIUM INTO A SEMICONDUCTOR WAFER
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