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07/11/2006
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10646997
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08/22/2003
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Pub Dt:
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02/24/2005
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Title:
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A SPIRAL INDUCTOR FORMED IN A SEMICONDUCTOR SUBSTRATE
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Patent #:
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12/12/2006
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10647863
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Filing Dt:
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08/25/2003
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Pub Dt:
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03/03/2005
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Title:
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ZERO CAPACITANCE BONDPAD UTILIZING ACTIVE NEGATIVE CAPACITANCE
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Issue Dt:
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04/26/2005
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10648602
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08/25/2003
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FORMING COPPER INTERCONNECTS WITH SN COATINGS
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11/23/2004
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10649140
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08/27/2003
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08/05/2004
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Title:
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METHOD OF MAKING ULTRA THIN BODY VERTICAL REPLACEMENT GATE MOSFET
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07/11/2006
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10649215
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08/26/2003
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03/03/2005
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Title:
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METHODOLOGY FOR GENERATING A MODIFIED VIEW OF A CIRCUIT LAYOUT
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05/02/2006
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10650296
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08/27/2003
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03/03/2005
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Title:
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METHOD OF CLOCK DRIVEN CELL PLACEMENT AND CLOCK TREE SYNTHESIS FOR INTEGRATED CIRCUIT DESIGN
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06/27/2006
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10650395
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08/28/2003
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03/03/2005
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Title:
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HIGH QUALITY FACTOR SPIRAL INDUCTOR THAT UTILIZES ACTIVE NEGATIVE CAPACITANCE
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03/21/2006
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10652007
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08/29/2003
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05/12/2005
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Title:
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LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL CHARACTERIZED BY IMPROVED RESISTANCE TO OXIDATION
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08/30/2005
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10652369
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08/29/2003
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03/03/2005
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Title:
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VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
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06/01/2004
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10652453
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08/29/2003
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Title:
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BONDING PAD ISOLATION
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05/30/2006
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10655050
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09/04/2003
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03/10/2005
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Title:
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PHASE-SHIFTING MASK AND SEMICONDUCTOR DEVICE
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03/08/2005
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10658017
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09/08/2003
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03/10/2005
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Title:
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METHOD OF TRANSLATING A NET DESCRIPTION OF AN INTEGRATED CIRCUIT DIE
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07/18/2006
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10658168
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09/08/2003
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03/24/2005
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Title:
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METHOD OF QUALIFYING A PROCESS TOOL WITH WAFER DEFECT MAPS
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11/21/2006
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10659134
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09/10/2003
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03/10/2005
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Title:
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APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
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04/11/2006
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10659138
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09/10/2003
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03/10/2005
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Title:
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FIRST TIME SILICON AND PROTO TEST CELL NOTIFICATION
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03/14/2006
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10661013
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09/12/2003
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03/17/2005
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WAFER EDGE INSPECTION DATA GATHERING
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06/21/2005
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10664137
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09/17/2003
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03/24/2005
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Title:
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CUSTOM CLOCK INTERCONNECTS ON A STANDARDIZED SILICON PLATFORM
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Issue Dt:
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04/20/2010
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10664636
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09/19/2003
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Title:
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USER INTERFACE SOFTWARE DEVELOPMENT TOOL AND METHOD FOR ENHANCING THE SEQUENCING OF
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06/13/2006
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10665927
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09/17/2003
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03/17/2005
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Title:
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METHOD OF NOISE ANALYSIS AND CORRECTION OF NOISE VIOLATIONS FOR AN INTEGRATED CIRCUIT DESIGN
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01/09/2007
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10667624
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09/22/2003
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03/24/2005
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Title:
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SYSTEM AND METHOD FOR OBSCURING UNWANTED AMBIENT NOISE AND HANDSET AND CENTRAL OFFICE EQUIPMENT INCORPORATING THE SAME
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07/25/2006
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10668021
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09/22/2003
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03/24/2005
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PAD CONDITIONER SETUP
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07/04/2006
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10668875
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09/23/2003
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03/24/2005
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Title:
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HIGH PERFORMANCE VOLTAGE CONTROL DIFFUSION RESISTOR
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08/31/2004
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10669398
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09/24/2003
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04/22/2004
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HIGH DOPANT CONENTRATION DIFFUSED RESISTOR AND METHOD OF MANUFACTURE THEREFOR
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03/07/2006
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10672495
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09/26/2003
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03/31/2005
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PACKAGED INTEGRATED CIRCUIT PROVIDING TRACE ACCESS TO HIGH-SPEED LEADS
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06/06/2006
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10673703
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09/29/2003
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03/31/2005
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METHODS AND APPARATUS FOR DETERMINING PAD HEIGHT FOR A WIRE-BONDING OPERATION IN AN INTEGRATED CIRCUIT
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04/04/2006
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10673721
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09/29/2003
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04/14/2005
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FUNCTIONALITY BASED PACKAGE DESIGN FOR INTEGRATED CIRCUIT BLOCKS
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07/28/2009
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10675258
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09/30/2003
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10/14/2004
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Title:
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ALUMINUM PAD POWER BUS AND SIGNAL ROUTING FOR INTEGRATED CIRCUIT DEVICES UTILIZING COPPER TECHNOLOGY INTERCONNECT STRUCTURES
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08/08/2006
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10675259
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09/30/2003
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03/31/2005
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METHOD FOR CONTROLLING TRENCH DEPTH IN SHALLOW TRENCH ISOLATION FEATURES
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11/01/2005
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10675260
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09/30/2003
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03/31/2005
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REINFORCED BOND PAD
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07/18/2006
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10675263
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09/30/2003
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03/31/2005
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SELECTIVE ISOTROPIC ETCH FOR TITANIUM-BASED MATERIALS
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11/21/2006
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10675569
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09/30/2003
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03/31/2005
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BYPASS LOOP GAS FLOW CALIBRATION
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08/28/2007
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10675572
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09/30/2003
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03/31/2005
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REAL-TIME GATE ETCH CRITICAL DIMENSION CONTROL BY OXYGEN MONITORING
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07/07/2009
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10675575
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09/30/2003
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07/01/2004
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IN-SITU REMOVAL OF SURFACE IMPURITIES PRIOR TO ARSENIC-DOPED POLYSILICON DEPOSITION IN THE FABRICATION OF A HETEROJUNCTION BIPOLAR TRANSISTOR
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06/14/2005
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10675581
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09/30/2003
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03/31/2005
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ALTERNATING PULSE DUAL-BEAM APPARATUS, METHODS AND SYSTEMS FOR VOLTAGE CONTRAST BEHAVIOR ASSESSMENT OF MICROCIRCUITS
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08/09/2005
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10675633
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09/30/2003
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03/31/2005
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METAL-OXIDE-SEMICONDUCTOR DEVICE INCLUDING A BURIED LIGHTLY-DOPED DRAIN REGION
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12/27/2005
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10676602
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10/01/2003
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04/21/2005
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SUBSTRATE-BIASED I/O AND POWER ESD PROTECTION CIRCUITS IN DEEP-SUBMICRON TWIN-WELL PROCESS
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01/04/2005
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10676934
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09/30/2003
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Title:
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PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER
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01/03/2006
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10679004
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10/02/2003
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MECHANISM FOR IMPROVING THE STRUCTURAL INTEGRITY OF LOW-K FILMS
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Issue Dt:
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09/28/2004
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10680047
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10/07/2003
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NONINTRUSIVE WAFER MARKING
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Issue Dt:
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12/06/2005
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10680503
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Filing Dt:
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10/06/2003
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Title:
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METHOD OF REDUCING PROCESS PLASMA DAMAGE USING OPTICAL SPECTROSCOPY
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03/18/2008
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10681554
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10/08/2003
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04/14/2005
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ROBUST HIGH DENSITY SUBSTRATE DESIGN FOR THERMAL CYCLING RELIABILITY
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Issue Dt:
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11/30/2004
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10683101
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10/09/2003
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SLOTTED BONDING PAD
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08/21/2007
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10683369
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10/10/2003
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04/14/2005
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INCREMENTAL DUMMY METAL INSERTIONS
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01/11/2005
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10684119
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10/10/2003
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04/29/2004
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IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
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06/06/2006
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10684713
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10/14/2003
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03/03/2005
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MULTIPLE OPERATING VOLTAGE VERTICAL REPLACEMENT-GATE (VRG) TRANSISTOR
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02/28/2006
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10688231
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10/17/2003
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04/21/2005
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METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING IMPROVED PERFORMANCE AND RELIABILITY
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09/19/2006
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10688460
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10/17/2003
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04/21/2005
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PROCESS AND APPARATUS FOR FAST ASSIGNMENT OF OBJECTS TO A RECTANGLE
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06/21/2005
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10690861
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10/22/2003
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04/28/2005
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COMPLIMENTARY METAL OXIDE SEMICONDUCTOR CAPACITOR AND METHOD FOR MAKING SAME
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06/14/2005
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10691400
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10/22/2003
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Pub Dt:
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04/28/2005
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ULTRA LOW DIELECTRIC CONSTANT THIN FILM
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03/22/2005
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10691938
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10/23/2003
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METHOD AND APPARATUS FOR MEASURING SHEET RESISTANCE
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Patent #:
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NONE
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10692110
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Filing Dt:
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10/23/2003
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12/02/2004
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Novel solution for low cost, speedy probe cards
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09/19/2006
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10693075
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10/23/2003
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Pub Dt:
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04/28/2005
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COMPARISON OF TWO HIERARCHICAL NETLIST TO GENERATE CHANGE ORDERS FOR UPDATING AN INTEGRATED CIRCUIT LAYOUT
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05/17/2005
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10693078
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10/23/2003
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04/28/2005
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DAISY CHAIN GANG TESTING
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Issue Dt:
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08/09/2005
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10693110
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10/24/2003
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Pub Dt:
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04/28/2005
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CHEMICAL MECHANICAL ELECTROPOLISHING SYSTEM
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04/25/2006
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10694208
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10/27/2003
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Pub Dt:
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04/28/2005
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Title:
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PROCESS AND APPARATUS FOR PLACEMENT OF CELLS IN AN IC DURING FLOORPLAN CREATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10694486
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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Bonding pad design
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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10694611
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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SEMICONDUCTOR DEVICE HAVING REDUCED INTRA-LEVEL AND INTER-LEVEL CAPACITANCE
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10695193
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Filing Dt:
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10/28/2003
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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FABRICATING SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10696105
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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GATE REUSE METHODOLOGY FOR DIFFUSED CELL-BASED IP BLOCKS IN PLATFORM-BASED SILICON PRODUCTS
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10696136
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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FIELD PLATED SCHOTTKY DIODE AND METHOD OF FABRICATION THEREFOR
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10696203
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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PROCESS YIELD LEARNING
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10696320
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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NEW METHODOLOGY TO MEASURE MANY MORE TRANSISTORS ON THE SAME TEST AREA
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10697357
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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METHOD OF PARTITIONING AN INTEGRATED CIRCUIT DESIGN FOR PHYSICAL DESIGN VERIFICATION
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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10697506
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Filing Dt:
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10/29/2003
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Title:
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METHOD OF VAPORIZING AND IONIZING METALS FOR USE IN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10697507
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Filing Dt:
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10/29/2003
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Title:
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VAPORIZATION AND IONIZATION OF METALS FOR USE IN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10697757
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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METHOD FOR MAKING ENHANCED SUBSTRATE CONTACT FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10698167
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Filing Dt:
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10/30/2003
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Title:
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CALCIUM DOPED POLYSILICON GATE ELECTRODES
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10698169
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Filing Dt:
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10/31/2003
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Title:
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MEMORY DEVICE HAVING AN ELECTRON TRAPPING LAYER IN A HIGH-K DIELECTRIC GATE STACK
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10699021
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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METHODS AND APPARATUS FOR THE DETECTION OF DAMAGED REGIONS ON DIELECTRIC FILM OR OTHER PORTIONS OF A DIE
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10699276
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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MIXED LVR AND HVR RETICLE SET DESIGN FOR THE PROCESSING OF GATE ARRAYS, EMBEDDED ARRAYS AND RAPID CHIP PRODUCTS
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10700790
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Filing Dt:
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11/03/2003
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Title:
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VDD OVER AND UNDERVOLTAGE MEASUREMENT TECHNIQUES USING MONITOR CELLS
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10700791
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Filing Dt:
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11/03/2003
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Title:
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METHOD FOR TESTING IDD AT MULTIPLE VOLTAGES
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10701328
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Filing Dt:
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11/03/2003
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Title:
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METHOD FOR PERFORMING STATISTICAL POST PROCESSING IN SEMICONDCTOR MANUFACTRING USING ID CELLS
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10702165
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Filing Dt:
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11/04/2003
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Title:
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THIN FILM CMOS CALIBRATION STANDARD HAVING PROTECTIVE COVER LAYER
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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10702875
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Filing Dt:
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11/05/2003
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Publication #:
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Pub Dt:
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08/03/2006
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Title:
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DEVICE PACKAGES HAVING STABLE WIREBONDS
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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10702996
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Filing Dt:
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11/05/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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SEMICONDUCTOR PACKAGE HAVING DISCRETE NON-ACTIVE ELECTRICAL COMPONENTS INCORPORATED INTO THE PACKAGE
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10704449
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Filing Dt:
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11/07/2003
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Publication #:
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Pub Dt:
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05/20/2004
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Title:
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MULTI-LAYERED SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10704922
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Filing Dt:
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11/10/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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METHOD OF GENERATING A SCHEMATIC DRIVEN LAYOUT FOR A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10706120
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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LOW VOLTAGE BREAKDOWN ELEMENT FOR ESD TRIGGER DEVICE
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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10706127
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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METHODOLOGY FOR DEBUGGING RTL SIMULATIONS OF PROCESSOR BASED SYSTEM ON CHIP
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Patent #:
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Issue Dt:
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08/07/2007
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Application #:
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10706467
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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REVERSE CONDUCTION PROTECTION METHOD AND APPARATUS FOR A DUAL POWER SUPPLY DRIVER
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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10713492
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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FLEXIBLE DESIGN FOR MEMORY USE IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/23/2007
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Application #:
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10713951
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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INTEGRATED CIRCUIT CARRIER APPARATUS METHOD AND SYSTEM
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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10716299
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Filing Dt:
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11/18/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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CONTACT FOR USE IN AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10718291
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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METHOD OF GENERATING A PHYSICAL NETLIST FOR A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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10718536
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Filing Dt:
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11/24/2003
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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HIGH K DIELECTRIC MATERIAL AND METHOD OF MAKING A HIGH K DIELECTRIC MATERIAL
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10718829
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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ANALYSIS OF INTEGRATED CIRCUITS FOR HIGH FREQUENCY PERFORMANCE
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10719195
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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METAL-OXIDE-SEMICONDUCTOR DEVICE FORMED IN SILICON-ON-INSULATOR
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10719393
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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PROCESS AND APPARATUS FOR PLACEMENT OF MEGACELLS IN ICS DESIGN
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10719787
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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METHOD AND APPARATUS FOR FINDING OPTIMAL UNIFICATION SUBSTITUTION FOR FORMULAS IN TECHNOLOGY LIBRARY
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10721126
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Filing Dt:
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11/25/2003
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Publication #:
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Pub Dt:
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06/24/2004
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Title:
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MASK LAYER AND DUAL DAMASCENE INTERCONNECT STRUCTURE IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10721971
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Filing Dt:
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11/24/2003
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Title:
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METHOD FOR CREATING BARRIER LAYERS FOR COPPER DIFFUSION
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Patent #:
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Issue Dt:
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09/30/2008
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Application #:
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10722652
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Filing Dt:
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11/26/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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METHODS AND APPARATUS FOR INTEGRATED CIRCUIT DEVICE POWER DISTRIBUTION VIA INTERNAL WIRE BONDS
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10723547
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Filing Dt:
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11/26/2003
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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VERTICAL REPLACEMENT-GATE JUNCTION FIELD-EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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10723701
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Filing Dt:
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11/26/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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CONTACT RESISTANCE DEVICE FOR IMPROVED PROCESS CONTROL
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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10724851
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Filing Dt:
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12/01/2003
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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PROCESS AND APPARATUS FOR ABSTRACTING IC DESIGN FILES
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10724996
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Filing Dt:
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12/01/2003
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Publication #:
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Pub Dt:
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06/02/2005
| | | | |
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Title:
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INTEGRATED CIRCUITS, AND DESIGN AND MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
05/01/2007
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Application #:
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10725638
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Filing Dt:
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12/02/2003
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Publication #:
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Pub Dt:
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08/18/2005
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Title:
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CUSTOMIZABLE DEVELOPMENT AND DEMONSTRATION PLATFORM FOR STRUCTURED ASICS
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10727474
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Filing Dt:
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12/04/2003
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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METHOD AND APPARATUS FOR TESTING OF INTEGRATED CIRCUIT PACKAGE
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10728036
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Filing Dt:
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12/03/2003
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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METHOD OF GENERATING AN EFFICIENT STUCK-AT FAULT AND TRANSITION DELAY FAULT TRUNCATED SCAN TEST PATTERN FOR AN INTEGRATED CIRCUIT DESIGN
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