|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/1996
|
Application #:
|
08479587
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
METHOD AND APPARATUS FOR ASSEMBLING MULTICHIP MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/1997
|
Application #:
|
08481799
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
KEYED END EFFECTOR FOR CMP PAD CONDITIONER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08484003
|
Filing Dt:
|
01/09/1996
|
|
Title:
|
INPUT-OUTPUT (I/O) STRUCTURE WITH CAPACITIVELY TRIGGERED THYRISTOR FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08484177
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
ENCAPSULATION OF ELECTRONIC COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/1998
|
Application #:
|
08484675
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SEGMENTED EMITTER LOW NOISE TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1998
|
Application #:
|
08485060
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
MULTIPLE PIN DIE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08485517
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
APPARATUS AND METHOD USING OPTICAL ENERGY FOR SPECIFYING AND QUANTITATIVELY CONTROLLING CHEMICALLY-REACTIVE COMPONENTS OF SEMICONDUCTOR PROCESSING PLASMA ETCHING GAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08486803
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SILICIDATION PROCESS WITH ETCH STOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/1997
|
Application #:
|
08486844
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
MULTIFUNCTIONAL CHIP WIRE BONDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1996
|
Application #:
|
08488075
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SELF-ALIGNED TWIN WELL PROCESS HAVING A SIO2-POLYSILICON-SIO2 BARRIER MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/1997
|
Application #:
|
08489270
|
Filing Dt:
|
06/09/1995
|
|
Title:
|
APPARATUS AND METHOD FOR ANALYZING CIRCUITS USING REDUCED-ORDER MODELING OF LARGE LINEAR SUBSCIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/1998
|
Application #:
|
08491433
|
Filing Dt:
|
06/16/1995
|
|
Title:
|
METHOD FOR LOCAL RIP-UP AND REROUTE OF SIGNAL PATHS IN AN IC DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08496861
|
Filing Dt:
|
06/30/1995
|
|
Title:
|
IMAGE SENSOR ARRAY WITH PICTURE ELEMENT SENSOR TESTABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1998
|
Application #:
|
08497470
|
Filing Dt:
|
06/30/1995
|
|
Title:
|
DOPING OF SILICON LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08498738
|
Filing Dt:
|
07/06/1995
|
|
Title:
|
CONNECTOR FOR MOUNTING AN ELECTRICAL COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/1997
|
Application #:
|
08500729
|
Filing Dt:
|
07/11/1995
|
|
Title:
|
SELF-ALIGNED ALIGNMENT MARKS FOR PHASE-SHIFTING MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08501289
|
Filing Dt:
|
07/12/1995
|
|
Title:
|
METHOD OF MAKING COMBINED METAL OXIDE SEMICONDUCTOR AND JUNCTION FIELD EFFECT TRANSISTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/1996
|
Application #:
|
08502566
|
Filing Dt:
|
07/13/1995
|
|
Title:
|
COMBINED JFET & MOS TRANSISTOR DEVICE, CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/1996
|
Application #:
|
08505047
|
Filing Dt:
|
07/21/1995
|
|
Title:
|
METHOD OF MAKING IN-CONTAINING III/V SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08506164
|
Filing Dt:
|
07/24/1995
|
|
Title:
|
METHOD OF IMPROVING MOLDING OF AN OVERMOLDED PACKAGE BODY ON A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08506382
|
Filing Dt:
|
07/24/1995
|
|
Title:
|
A METHOD OF PLANARIZING AN ARRAY OF PLASTICALLY DEFORMABLE ELECTRICAL CONTACTS ON AN INTEGRATED CIRCUIT PACKAGE TO COMPENSATE FOR BOTTOM SURFACE WARPAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/1997
|
Application #:
|
08506821
|
Filing Dt:
|
07/25/1995
|
|
Title:
|
PROCESS MONITOR FOR CMOS INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/1997
|
Application #:
|
08509267
|
Filing Dt:
|
07/31/1995
|
|
Title:
|
APPARATUS FOR DETERMINING THE THERMAL RESISTIVITY OF ELECTRICALLY INSULATING CRYSTALLINE MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/1997
|
Application #:
|
08509678
|
Filing Dt:
|
07/31/1995
|
|
Title:
|
METHOD OF DETERMINING THE THERMAL RESISTIVITY OF ELECTRICALLY INSULATING CRYSTALLINE MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1998
|
Application #:
|
08509930
|
Filing Dt:
|
08/01/1995
|
|
Title:
|
COMBINED PHOTOGATE AND PHOTODIODE ACTIVE PIXEL IMAGE SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08511845
|
Filing Dt:
|
08/07/1995
|
|
Title:
|
PROCESS FOR REDUCING TRANSIENT DIFFUSION OF DOPANT ATOMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08512678
|
Filing Dt:
|
08/08/1995
|
|
Title:
|
AUTOMATING PHOTOLITHOGRAPHY IN THE FABRICATION OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08516060
|
Filing Dt:
|
08/17/1995
|
|
Title:
|
HIGH RESOLUTION REMOTE POSITION DETECTION USING SEGMENTED GRATINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/1997
|
Application #:
|
08516368
|
Filing Dt:
|
08/17/1995
|
|
Title:
|
SUB-MICRON THROUGH-THE-LENS POSITIONING UTILIZING OUT OF PHASE SEGMENTED GRATINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
08517142
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/1998
|
Application #:
|
08517153
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL DRAM ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08517171
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
CAD FOR HEXAGONAL ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08517189
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL SENSE CELL ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08517236
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL ARCHITECTURE WITH TRIANGULAR SHAPED CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08517266
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL SRAM ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08517339
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRI-DIRECTIONAL INTERCONNECT ARCHITECTURE FOR SRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08517406
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
ARCHITECTURE HAVING DIAMOND SHAPED OR PARALLELOGRAM SHAPED CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/1998
|
Application #:
|
08517441
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
POLYDIRECTIONAL NON-ORTHOGINAL THREE LAYER INTERCONNECT ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08517451
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRIANGULAR SEMICONDUCTOR 'NAND' GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08517479
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRIANGULAR SEMICONDUCTOR "AND" GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08517508
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08517892
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRIANGULAR SEMICONDUCTOR OR GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/1997
|
Application #:
|
08520030
|
Filing Dt:
|
08/28/1995
|
|
Title:
|
LEAK DETECTION SYSTEM FOR A GAS MANIFOLD OF A CHEMICAL VAPOR DEPOSITION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/1997
|
Application #:
|
08520058
|
Filing Dt:
|
08/28/1995
|
|
Title:
|
A METHOD OF FORMING A LAYER OF MATERIAL ON A WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/1996
|
Application #:
|
08521795
|
Filing Dt:
|
08/31/1995
|
|
Title:
|
IMPLANTATION OF A SEMICONDUCTOR SUBSTRATE WITH CONTROLLED AMOUNT OF NOBLE GAS IONS TO REDUCE CHANNELING AND/OR DIFFUSION OF A BORON DOPANT SUBSEQUENTLY IMPLANTED INTO THE SUBSTRATE TO FORM P- LDD REGION OF A PMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08525839
|
Filing Dt:
|
09/08/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING MULTIWAY PARTITIONING WITH CONSTRAINTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1998
|
Application #:
|
08531115
|
Filing Dt:
|
09/20/1995
|
|
Title:
|
WAFER PROCESSING USING THERMAL NITRIDE ETCH MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08531659
|
Filing Dt:
|
09/21/1995
|
|
Title:
|
HIGH SURFACE AREA TRENCHES FOR AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1998
|
Application #:
|
08531727
|
Filing Dt:
|
09/21/1995
|
|
Title:
|
INTEGRATED CIRCUIT DEVICE FABRICATION BY PLASMA ETCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08534008
|
Filing Dt:
|
09/26/1995
|
|
Title:
|
ANTIFUSE DEVICE FOR USE ON A FIELD PROGRAMMABLE INTERCONNECT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/1997
|
Application #:
|
08534356
|
Filing Dt:
|
09/27/1995
|
|
Title:
|
SELF-POWERED DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/1997
|
Application #:
|
08536002
|
Filing Dt:
|
09/29/1995
|
|
Title:
|
HIGH DENSITY CMOS INTEGRATED CIRCUIT WITH HEAT TRANSFER STRUCTURE FOR IMPROVED COOLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08536004
|
Filing Dt:
|
09/29/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING GENERALIZED ASSIGNMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/1996
|
Application #:
|
08538317
|
Filing Dt:
|
10/03/1995
|
|
Title:
|
COMPENSATION OF THE TEMPERATURE COEFFICIENT OF THE DIELECTRIC CONSTANT OF BARIUM STRONTIUM TITANATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08538318
|
Filing Dt:
|
10/03/1995
|
|
Title:
|
PYROCHLORE BASED OXIDES WITH HIGH DIELECTRIC CONSTANT AND LOW TEMPERATURE COEFFICIENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08538629
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
METHOD OF CENTERING A HIGH PRESSURE LID SEAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/1998
|
Application #:
|
08538630
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
HIGH PRESSURE LID SEAL CLIP APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08538631
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
HIGH CONTACT DENSITY BALL GRID ARRAY PACKAGE FOR FLIP-CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/1997
|
Application #:
|
08538907
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
METHOD OF CENTERING A LID SEAL CLIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/1998
|
Application #:
|
08539188
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
CONFIGURABLE BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08539189
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
CENTERING LID SEAL CLIP APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08542995
|
Filing Dt:
|
10/13/1995
|
|
Title:
|
MICROELECTRONIC PACKAGE WITH DEVICE COOLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08545462
|
Filing Dt:
|
10/19/1995
|
|
Title:
|
DEFECT ISOLATION USING SCAN-PATH TESTING AND ELECTRON BEAM PROBING IN MULTI-LEVEL HIGH DENSITY ASICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/1997
|
Application #:
|
08545879
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
METHOD AND APPARATUS FOR TESTING OF SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08545880
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
APPARATUS AND METHOD FOR MEASURING QUIESCENT CURRENT UTILIZING TIMESET SWITCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/1997
|
Application #:
|
08546055
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
METHOD AND APPARATUS FOR BUILT-IN SELF-TEST WITH MULTIPLE CLOCK CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08546078
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
APPARATUS FOR CONTROLLING A CHARGED PARTICLE BEAM AND A LITHOGRAPHIC PROCESS IN WHICH THE APPARATUS IS USED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/1997
|
Application #:
|
08546921
|
Filing Dt:
|
10/23/1995
|
|
Title:
|
PROCESS AND STRUCTURE FOR REDUCTION OF CHANNELING DURING IMPLANTATION OF SOURCE AND DRAIN REGIONS IN FORMATION OF MOS INTEGRATED CIRCUIT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08548533
|
Filing Dt:
|
10/26/1995
|
|
Title:
|
FIELD EMISSION DEVICE AND METHOD FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1998
|
Application #:
|
08549990
|
Filing Dt:
|
10/30/1995
|
|
Title:
|
INTEGRATED CIRCUIT WITH ACTIVE DEVICES UNDER BOND PADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/1997
|
Application #:
|
08550879
|
Filing Dt:
|
10/31/1995
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Title:
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AUXILIARY MASK FEATURES FOR ENHANCING THE RESOLUTION OF PHOTOLITHOGRAPHY
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Patent #:
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Issue Dt:
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10/14/1997
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Application #:
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08552421
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Filing Dt:
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11/03/1995
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Title:
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METHOD TO DERIVE THE FUNCTIONALITY OF A DIGITAL CIRCUIT FROM ITS MASK LAYOUT
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Patent #:
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Issue Dt:
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09/23/1997
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Application #:
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08552461
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Filing Dt:
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11/09/1995
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Title:
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PROCESS FOR MAKING INTEGRATED CIRCUIT STRUCTURE COMPRISING LOCAL AREA INTERCONNECTS FORMED OVER SEMICONDUCTOR SUBSTRATE BY SELECTIVE DEPOSITION ON SEED LAYER IN PATTERNED TRENCH
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Patent #:
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Issue Dt:
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08/12/1997
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Application #:
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08552998
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Filing Dt:
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11/03/1995
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Title:
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ENERGY-SENSITIVE RESIST MATERIAL AND A PROCESS FOR DEVICE FABRICATION USING AN ENERGY-SENSITIVE RESIST MATERIAL
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08553118
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Filing Dt:
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11/07/1995
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Title:
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METHOD AND APPARATUS FOR REAL TIME MONITORING OF WAFER ATTRIBUTES IN A PLASMA ETCH PROCESS
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08554501
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Filing Dt:
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11/07/1995
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Title:
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METHOD OF GLOBAL PLANARIZATION IN FABRICATING INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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07/15/1997
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Application #:
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08555594
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Filing Dt:
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11/09/1995
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Title:
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FIELD EMISSION DEVICES EMPLOYING IMPROVED EMITTERS ON METAL FOIL AND METHODS FOR MAKING SUCH DEVICES
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Patent #:
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Issue Dt:
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02/17/1998
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Application #:
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08556599
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Filing Dt:
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11/13/1995
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Title:
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ESD PROTECTION FOR DEEP SUBMICRON CMOS DEVICES WITH MINIMUM TRADEOFF FOR LATCHUP BEHAVIOR
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Patent #:
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Issue Dt:
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04/28/1998
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Application #:
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08557721
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Filing Dt:
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11/13/1995
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Title:
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PROCESS FOR FORMING LOW DIELECTRIC CONSTANT LAYERS USING FULLERENES
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08558165
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Filing Dt:
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11/13/1995
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Title:
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METHOD FOR PRODUCING INTEGRATED CIRCUIT CHIP HAVING OPTIMIZED CELL PLACEMENT
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Patent #:
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Issue Dt:
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09/29/1998
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Application #:
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08558997
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Filing Dt:
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11/16/1995
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Title:
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PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION
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Patent #:
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Issue Dt:
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06/03/1997
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Application #:
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08559206
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Filing Dt:
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11/13/1995
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Title:
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COMPUTER IMPLEMENTED METHOD FOR PRODUCING OPTIMIZED CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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01/27/1998
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Application #:
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08560588
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Filing Dt:
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11/20/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING FUZZY CELL CLUSTERIZATION
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Patent #:
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Issue Dt:
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04/28/1998
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Application #:
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08560671
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Filing Dt:
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11/20/1995
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Title:
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ELECTROSTATIC PROTECTION DEVICES FOR PROTECTING SEMICONDUCTOR INTEGRATED CIRCUITRY
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08560834
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Filing Dt:
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11/20/1995
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Title:
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COMPUTER IMPLEMENTED METHOD FOR LEVELING INTERCONNECT WIRING DENSITY IN A CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08560848
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Filing Dt:
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11/20/1995
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING HIGHLY PARALLEL SIEVE OPTIMIZATION WITH MULTIPLE "JIGGLES"
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Patent #:
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Issue Dt:
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07/22/1997
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Application #:
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08561107
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Filing Dt:
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11/21/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR CMOS "NAND" GATE DEVICE
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Patent #:
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Issue Dt:
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09/23/1997
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Application #:
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08561473
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Filing Dt:
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11/21/1995
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Title:
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METHOD OF FORMING A DMOS-CONTROLLED LATERAL BIOPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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06/30/1998
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Application #:
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08562235
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Filing Dt:
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11/21/1995
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Title:
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BIPOLAR TRANSISTOR WITH MOS-CONTROLLED PROTECTION FOR REVERSE-BIASED EMITTER-BASED JUNCTION
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08563688
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Filing Dt:
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11/28/1995
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Title:
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PROCESS FOR CONTROLLING DOPANT DIFFUSION IN A SEMICONDUCTOR LAYER
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Patent #:
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Issue Dt:
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11/18/1997
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Application #:
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08565286
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Filing Dt:
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11/30/1995
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Title:
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INTEGRATED CIRCUIT FABRICATION
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Patent #:
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Issue Dt:
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11/18/1997
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Application #:
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08566445
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Filing Dt:
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12/01/1995
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Title:
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ENERGY SENSITIVE RESIST MATERIAL AND PROCESS FOR DEVICE FABRICATION USING THE RESIST MATERIAL
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Patent #:
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Issue Dt:
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04/15/1997
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Application #:
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08566766
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Filing Dt:
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12/04/1995
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Title:
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METHOD OF DEPOSITING THIN PASSIVATING FILM ON MICROMINIATURE SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08567894
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Filing Dt:
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12/06/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR SEMICONDUCTOR "OR" GATE DEVICE
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Patent #:
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Issue Dt:
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05/20/1997
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Application #:
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08567952
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Filing Dt:
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12/06/1995
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR SEMICONDUCTOR "AND" GATE DEVICE
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Patent #:
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Issue Dt:
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12/31/1996
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Application #:
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08568040
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Filing Dt:
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12/06/1995
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Title:
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PROCESS FOR FORMING INTEGRATED CAPACITORS
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Patent #:
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Issue Dt:
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11/11/1997
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Application #:
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08569025
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Filing Dt:
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12/07/1995
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|
Title:
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TITANIUM SILICIDE PROCESS
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|
|
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Patent #:
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|
Issue Dt:
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10/13/1998
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Application #:
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08570429
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Filing Dt:
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12/11/1995
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|
Title:
|
INTEGRATED CIRCUIT FABRICATION
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|
|
|
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Patent #:
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Issue Dt:
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04/29/1997
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Application #:
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08570906
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Filing Dt:
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12/12/1995
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Title:
|
ACOUSTIC ANALYSIS OF GAS MIXTURES
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Patent #:
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Issue Dt:
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04/29/1997
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Application #:
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08572196
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Filing Dt:
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12/14/1995
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Title:
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COMPLEMENTARY TFT DEVICES WITH DIODE-EFFECT ELIMINATION MEANS INDEPENDENT OF TFT-CHANNEL GEOMETRY
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|
