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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 32 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
7594201
Issue Dt:
09/22/2009
Application #:
11460680
Filing Dt:
07/28/2006
Publication #:
US20060282801
Pub Dt:
12/14/2006
Title:
ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CONTROL STRUCTURES IN RTL CODE
2
Patent #:
7480881
Issue Dt:
01/20/2009
Application #:
11465662
Filing Dt:
08/18/2006
Publication #:
US20080046848
Pub Dt:
02/21/2008
Title:
METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY DE-RATING AND CLOCK CONSERVATISM REDUCTION
3
Patent #:
7633152
Issue Dt:
12/15/2009
Application #:
11468901
Filing Dt:
08/31/2006
Publication #:
US20070064398
Pub Dt:
03/22/2007
Title:
HEAT DISSIPATION IN INTEGRATED CIRCUITS
4
Patent #:
8180600
Issue Dt:
05/15/2012
Application #:
11469028
Filing Dt:
08/31/2006
Publication #:
US20080059142
Pub Dt:
03/06/2008
Title:
INPUT/OUTPUT BUFFER INFORMATION SPECIFICATION (IBIS) MODEL GENERATION FOR MULTI-CHIP MODULES (MCM) AND SIMILAR DEVICES
5
Patent #:
7479438
Issue Dt:
01/20/2009
Application #:
11469032
Filing Dt:
08/31/2006
Publication #:
US20080054406
Pub Dt:
03/06/2008
Title:
METHOD TO IMPROVE PERFORMANCE OF A BIPOLAR DEVICE USING AN AMORPHIZING IMPLANT
6
Patent #:
8319343
Issue Dt:
11/27/2012
Application #:
11469960
Filing Dt:
09/05/2006
Publication #:
US20070063352
Pub Dt:
03/22/2007
Title:
ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER
7
Patent #:
7298458
Issue Dt:
11/20/2007
Application #:
11473627
Filing Dt:
06/22/2006
Publication #:
US20060238728
Pub Dt:
10/26/2006
Title:
OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
8
Patent #:
7490307
Issue Dt:
02/10/2009
Application #:
11478044
Filing Dt:
06/29/2006
Publication #:
US20080005710
Pub Dt:
01/03/2008
Title:
AUTOMATIC GENERATION OF TIMING CONSTRAINTS FOR THE VALIDATION/SIGNOFF OF TEST STRUCTURES
9
Patent #:
7465655
Issue Dt:
12/16/2008
Application #:
11494221
Filing Dt:
07/27/2006
Publication #:
US20060264024
Pub Dt:
11/23/2006
Title:
INTEGRATED CIRCUIT WITH SUBSTANTIALLY PERPENDICULAR WIRE BONDS
10
Patent #:
7680205
Issue Dt:
03/16/2010
Application #:
11494962
Filing Dt:
07/28/2006
Publication #:
US20080043873
Pub Dt:
02/21/2008
Title:
METHOD AND SYSTEM FOR TRANSMITTER BEAMFORMING FOR REDUCED COMPLEXITY MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) TRANSCEIVERS
11
Patent #:
7423341
Issue Dt:
09/09/2008
Application #:
11505152
Filing Dt:
08/16/2006
Publication #:
US20080042262
Pub Dt:
02/21/2008
Title:
PLASTIC OVERMOLDED PACKAGES WITH MECHANICALLY DECOUPLED LID ATTACH ATTACHMENT
12
Patent #:
7456076
Issue Dt:
11/25/2008
Application #:
11506659
Filing Dt:
08/18/2006
Publication #:
US20060279005
Pub Dt:
12/14/2006
Title:
TECHNIQUES FOR FORMING PASSIVE DEVICES DURING SEMICONDUCTOR BACK-END PROCESSING
13
Patent #:
7456498
Issue Dt:
11/25/2008
Application #:
11506680
Filing Dt:
08/18/2006
Publication #:
US20080042267
Pub Dt:
02/21/2008
Title:
INTEGRATED CIRCUIT PACKAGE AND SYSTEM INTERFACE
14
Patent #:
7590957
Issue Dt:
09/15/2009
Application #:
11509370
Filing Dt:
08/24/2006
Publication #:
US20080052652
Pub Dt:
02/28/2008
Title:
METHOD AND APPARATUS FOR FIXING BEST CASE HOLD TIME VIOLATIONS IN AN INTEGRATED CIRCUIT DESIGN
15
Patent #:
7319889
Issue Dt:
01/15/2008
Application #:
11516316
Filing Dt:
09/06/2006
Publication #:
US20070004470
Pub Dt:
01/04/2007
Title:
SYSTEM AND METHOD FOR CONSERVING BATTERY POWER IN A MOBILE STATION
16
Patent #:
7547560
Issue Dt:
06/16/2009
Application #:
11519614
Filing Dt:
09/12/2006
Publication #:
US20070010032
Pub Dt:
01/11/2007
Title:
DEFECT IDENTIFICATION SYSTEM AND METHOD FOR REPAIRING KILLER DEFECTS IN SEMICONDUCTOR DEVICES
17
Patent #:
7408227
Issue Dt:
08/05/2008
Application #:
11524107
Filing Dt:
09/20/2006
Publication #:
US20070013006
Pub Dt:
01/18/2007
Title:
APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
18
Patent #:
7420229
Issue Dt:
09/02/2008
Application #:
11527108
Filing Dt:
09/25/2006
Publication #:
US20070015297
Pub Dt:
01/18/2007
Title:
FAILURE ANALYSIS VEHICLE FOR YIELD ENHANCEMENT WITH SELF TEST AT SPEED BURNIN CAPABILITY FOR RELIABILITY TESTING
19
Patent #:
7271485
Issue Dt:
09/18/2007
Application #:
11530550
Filing Dt:
09/11/2006
Title:
SYSTEMS AND METHODS FOR DISTRIBUTING I/O IN A SEMICONDUCTOR DEVICE
20
Patent #:
7666750
Issue Dt:
02/23/2010
Application #:
11531477
Filing Dt:
09/13/2006
Publication #:
US20080064177
Pub Dt:
03/13/2008
Title:
BIPOLAR DEVICE HAVING IMPROVED CAPACITANCE
21
Patent #:
8049282
Issue Dt:
11/01/2011
Application #:
11533785
Filing Dt:
09/21/2006
Publication #:
US20080076228
Pub Dt:
03/27/2008
Title:
BIPOLAR DEVICE HAVING BURIED CONTACTS
22
Patent #:
7535330
Issue Dt:
05/19/2009
Application #:
11534340
Filing Dt:
09/22/2006
Publication #:
US20080074228
Pub Dt:
03/27/2008
Title:
LOW MUTUAL INDUCTANCE MATCHED INDUCTORS
23
Patent #:
7847666
Issue Dt:
12/07/2010
Application #:
11535501
Filing Dt:
09/27/2006
Publication #:
US20080074229
Pub Dt:
03/27/2008
Title:
DIFFERENTIAL INDUCTOR FOR USE IN INTEGRATED CIRCUITS
24
Patent #:
7392496
Issue Dt:
06/24/2008
Application #:
11538187
Filing Dt:
10/03/2006
Publication #:
US20080155488
Pub Dt:
06/26/2008
Title:
DEVICE FOR AVOIDING TIMING VIOLATIONS RESULTING FROM PROCESS DEFECTS IN A BACKFILLED METAL LAYER OF AN INTEGRATED CIRCUIT
25
Patent #:
7239160
Issue Dt:
07/03/2007
Application #:
11540056
Filing Dt:
09/29/2006
Publication #:
US20070024303
Pub Dt:
02/01/2007
Title:
METHOD OF ELECTRICAL TESTING OF AN INTERGRATED CIRCUIT WITH AN ELECTRICAL PROBE
26
Patent #:
7332775
Issue Dt:
02/19/2008
Application #:
11542864
Filing Dt:
10/04/2006
Publication #:
US20070023848
Pub Dt:
02/01/2007
Title:
PROTRUDING SPACERS FOR SELF-ALIGNED CONTACTS
27
Patent #:
7610568
Issue Dt:
10/27/2009
Application #:
11550448
Filing Dt:
10/18/2006
Publication #:
US20070094629
Pub Dt:
04/26/2007
Title:
METHODS AND APPARATUS FOR MAKING PLACEMENT SENSITIVE LOGIC MODIFICATIONS
28
Patent #:
7496870
Issue Dt:
02/24/2009
Application #:
11551573
Filing Dt:
10/20/2006
Publication #:
US20070050744
Pub Dt:
03/01/2007
Title:
METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING
29
Patent #:
7982307
Issue Dt:
07/19/2011
Application #:
11562537
Filing Dt:
11/22/2006
Publication #:
US20080116567
Pub Dt:
05/22/2008
Title:
INTEGRATED CIRCUIT CHIP ASSEMBLY HAVING ARRAY OF THERMALLY CONDUCTIVE FEATURES ARRANGED IN APERTURE OF CIRCUIT SUBSTRATE
30
Patent #:
7804167
Issue Dt:
09/28/2010
Application #:
11565701
Filing Dt:
12/01/2006
Publication #:
US20080128919
Pub Dt:
06/05/2008
Title:
WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O
31
Patent #:
NONE
Issue Dt:
Application #:
11567086
Filing Dt:
12/05/2006
Publication #:
US20070123283
Pub Dt:
05/31/2007
Title:
SYSTEM AND METHOD FOR OBSCURING UNWANTED AMBIENT NOISE AND A MOBILE COMMUNICATIONS DEVICE AND CENTRAL OFFICE EQUIPMENT INCORPORATING THE SAME
32
Patent #:
7584439
Issue Dt:
09/01/2009
Application #:
11567986
Filing Dt:
12/07/2006
Publication #:
US20080140377
Pub Dt:
06/12/2008
Title:
CELL MODELING FOR INTEGRATED CIRCUIT DESIGN WITH CHARACTERIZATION OF UPSTREAM DRIVER STRENGTH
33
Patent #:
7782375
Issue Dt:
08/24/2010
Application #:
11575856
Filing Dt:
07/13/2007
Publication #:
US20070279481
Pub Dt:
12/06/2007
Title:
MOBILE COMMUNICATION DEVICE HAVING PANORAMIC IMAGEMAKING CAPABILITY
34
Patent #:
7607112
Issue Dt:
10/20/2009
Application #:
11609509
Filing Dt:
12/12/2006
Publication #:
US20080135974
Pub Dt:
06/12/2008
Title:
METHOD AND APPARATUS FOR PERFORMING METALIZATION IN AN INTEGRATED CIRCUIT PROCESS
35
Patent #:
7617467
Issue Dt:
11/10/2009
Application #:
11610825
Filing Dt:
12/14/2006
Publication #:
US20080148199
Pub Dt:
06/19/2008
Title:
ELECTROSTATIC DISCHARGE DEVICE VERIFICATION IN AN INTEGRATED CIRCUIT
36
Patent #:
7546560
Issue Dt:
06/09/2009
Application #:
11634683
Filing Dt:
12/06/2006
Publication #:
US20080141184
Pub Dt:
06/12/2008
Title:
OPTIMIZATION OF FLIP FLOP INITIALIZATION STRUCTURES WITH RESPECT TO DESIGN SIZE AND DESIGN CLOSURE EFFORT FROM RTL TO NETLIST
37
Patent #:
7537984
Issue Dt:
05/26/2009
Application #:
11641507
Filing Dt:
12/19/2006
Publication #:
US20070096146
Pub Dt:
05/03/2007
Title:
III-V POWER FIELD EFFECT TRANSISTORS
38
Patent #:
7557303
Issue Dt:
07/07/2009
Application #:
11641989
Filing Dt:
12/18/2006
Publication #:
US20080142250
Pub Dt:
06/19/2008
Title:
ELECTRONIC COMPONENT CONNECTION SUPPORT STRUCTURES INCLUDING AIR AS A DIELECTRIC
39
Patent #:
7727894
Issue Dt:
06/01/2010
Application #:
11649015
Filing Dt:
01/03/2007
Publication #:
US20070228572
Pub Dt:
10/04/2007
Title:
FORMATION OF AN INTEGRATED CIRCUIT STRUCTURE WITH REDUCED DISHING IN METALLIZATION LEVELS
40
Patent #:
7670203
Issue Dt:
03/02/2010
Application #:
11649197
Filing Dt:
01/03/2007
Publication #:
US20070293115
Pub Dt:
12/20/2007
Title:
PROCESS FOR MAKING AN ON-CHIP VACUUM TUBE DEVICE
41
Patent #:
7751466
Issue Dt:
07/06/2010
Application #:
11654957
Filing Dt:
01/18/2007
Publication #:
US20070189368
Pub Dt:
08/16/2007
Title:
CHANNEL ESTIMATION FOR A HIGH-SPEED DATA PACKET ACCESS RAKE RECEIVER
42
Patent #:
7430700
Issue Dt:
09/30/2008
Application #:
11670031
Filing Dt:
02/01/2007
Publication #:
US20070179745
Pub Dt:
08/02/2007
Title:
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
43
Patent #:
7557010
Issue Dt:
07/07/2009
Application #:
11673645
Filing Dt:
02/12/2007
Publication #:
US20080191246
Pub Dt:
08/14/2008
Title:
METHOD TO IMPROVE WRITER LEAKAGE IN A SIGE BIPOLAR DEVICE
44
Patent #:
7804291
Issue Dt:
09/28/2010
Application #:
11673714
Filing Dt:
02/12/2007
Publication #:
US20070168818
Pub Dt:
07/19/2007
Title:
SEMICONDUCTOR TEST DEVICE WITH HEATING CIRCUIT
45
Patent #:
7395478
Issue Dt:
07/01/2008
Application #:
11682914
Filing Dt:
03/07/2007
Publication #:
US20070162804
Pub Dt:
07/12/2007
Title:
METHOD OF GENERATING TEST PATTERNS TO EFFICIENTLY SCREEN INLINE RESISTANCE DELAY DEFECTS IN COMPLEX ASICS
46
Patent #:
7709861
Issue Dt:
05/04/2010
Application #:
11684674
Filing Dt:
03/12/2007
Publication #:
US20080061319
Pub Dt:
03/13/2008
Title:
SYSTEMS AND METHODS FOR SUPPORTING A SUBSET OF MULTIPLE INTERFACE TYPES IN A SEMICONDUCTOR DEVICE
47
Patent #:
7930674
Issue Dt:
04/19/2011
Application #:
11693081
Filing Dt:
03/29/2007
Publication #:
US20080244473
Pub Dt:
10/02/2008
Title:
MODIFYING INTEGRATED CIRCUIT DESIGNS TO ACHIEVE MULTIPLE OPERATING FREQUENCY TARGETS
48
Patent #:
7456061
Issue Dt:
11/25/2008
Application #:
11694021
Filing Dt:
03/30/2007
Publication #:
US20080237642
Pub Dt:
10/02/2008
Title:
METHOD TO REDUCE BORON PENETRATION IN A SIGE BIPOLAR DEVICE
49
Patent #:
NONE
Issue Dt:
Application #:
11695169
Filing Dt:
04/02/2007
Publication #:
US20070163993
Pub Dt:
07/19/2007
Title:
Planarization with reduced dishing
50
Patent #:
7548844
Issue Dt:
06/16/2009
Application #:
11706943
Filing Dt:
02/13/2007
Publication #:
US20070276648
Pub Dt:
11/29/2007
Title:
SEQUENTIAL TESTER FOR LONGEST PREFIX SEARCH ENGINES
51
Patent #:
7676773
Issue Dt:
03/09/2010
Application #:
11724143
Filing Dt:
03/14/2007
Publication #:
US20080229268
Pub Dt:
09/18/2008
Title:
TRACE OPTIMIZATION IN FLATTENED NETLIST BY STORING AND RETRIEVING INTERMEDIATE RESULTS
52
Patent #:
7665058
Issue Dt:
02/16/2010
Application #:
11724663
Filing Dt:
03/15/2007
Publication #:
US20070162886
Pub Dt:
07/12/2007
Title:
CUSTOMIZABLE DEVELOPMENT AND DEMONSTRATION PLATFORM FOR STRUCTURED ASICS
53
Patent #:
7669155
Issue Dt:
02/23/2010
Application #:
11728366
Filing Dt:
03/26/2007
Publication #:
US20080244491
Pub Dt:
10/02/2008
Title:
GENERIC METHODOLOGY TO SUPPORT CHIP LEVEL INTEGRATION OF IP CORE INSTANCE CONSTRAINTS IN INTEGRATED CIRCUITS
54
Patent #:
7496867
Issue Dt:
02/24/2009
Application #:
11732092
Filing Dt:
04/02/2007
Publication #:
US20080244474
Pub Dt:
10/02/2008
Title:
CELL LIBRARY MANAGEMENT FOR POWER OPTIMIZATION
55
Patent #:
7413984
Issue Dt:
08/19/2008
Application #:
11733673
Filing Dt:
04/10/2007
Publication #:
US20070178692
Pub Dt:
08/02/2007
Title:
MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
56
Patent #:
7728433
Issue Dt:
06/01/2010
Application #:
11736402
Filing Dt:
04/17/2007
Publication #:
US20070190784
Pub Dt:
08/16/2007
Title:
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
57
Patent #:
7675179
Issue Dt:
03/09/2010
Application #:
11738050
Filing Dt:
04/20/2007
Publication #:
US20070190803
Pub Dt:
08/16/2007
Title:
DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT
58
Patent #:
7825522
Issue Dt:
11/02/2010
Application #:
11741195
Filing Dt:
04/27/2007
Publication #:
US20080018419
Pub Dt:
01/24/2008
Title:
HYBRID BUMP CAPACITOR
59
Patent #:
7407824
Issue Dt:
08/05/2008
Application #:
11748569
Filing Dt:
05/15/2007
Publication #:
US20070212873
Pub Dt:
09/13/2007
Title:
GUARD RING FOR IMPROVED MATCHING
60
Patent #:
7644382
Issue Dt:
01/05/2010
Application #:
11749904
Filing Dt:
05/17/2007
Publication #:
US20070271537
Pub Dt:
11/22/2007
Title:
COMMAND-LANGUAGE-BASED FUNCTIONAL ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION
61
Patent #:
7818703
Issue Dt:
10/19/2010
Application #:
11757200
Filing Dt:
06/01/2007
Publication #:
US20080016482
Pub Dt:
01/17/2008
Title:
DENSITY DRIVEN LAYOUT FOR RRAM CONFIGURATION MODULE
62
Patent #:
7568175
Issue Dt:
07/28/2009
Application #:
11757229
Filing Dt:
06/01/2007
Publication #:
US20070234255
Pub Dt:
10/04/2007
Title:
RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES
63
Patent #:
7822099
Issue Dt:
10/26/2010
Application #:
11758975
Filing Dt:
06/06/2007
Publication #:
US20070230621
Pub Dt:
10/04/2007
Title:
DIGITAL GAUSSIAN NOISE SIMULATOR
64
Patent #:
7849422
Issue Dt:
12/07/2010
Application #:
11765691
Filing Dt:
06/20/2007
Publication #:
US20080320420
Pub Dt:
12/25/2008
Title:
EFFICIENT CELL SWAPPING SYSTEM FOR LEAKAGE POWER REDUCTION IN A MULTI-THRESHOLD VOLTAGE PROCESS
65
Patent #:
7492049
Issue Dt:
02/17/2009
Application #:
11768725
Filing Dt:
06/26/2007
Publication #:
US20070246844
Pub Dt:
10/25/2007
Title:
MULTI-LAYER REGISTRATION AND DIMENSIONAL TEST MARK FOR SCATTEROMETRICAL MEASUREMENT
66
Patent #:
7738078
Issue Dt:
06/15/2010
Application #:
11769486
Filing Dt:
06/27/2007
Publication #:
US20070247604
Pub Dt:
10/25/2007
Title:
OPTIMIZED MIRROR DESIGN FOR OPTICAL DIRECT WRITE
67
Patent #:
7894852
Issue Dt:
02/22/2011
Application #:
11770975
Filing Dt:
06/29/2007
Publication #:
US20070249392
Pub Dt:
10/25/2007
Title:
CHANNEL RECIPROCITY MATRIX DETERMINATION IN A WIRELESS MIMO COMMUNICATION SYSTEM
68
Patent #:
7479703
Issue Dt:
01/20/2009
Application #:
11772267
Filing Dt:
07/02/2007
Publication #:
US20090008767
Pub Dt:
01/08/2009
Title:
INTEGRATED CIRCUIT PACKAGE WITH SPUTTERED HEAT SINK FOR IMPROVED THERMAL PERFORMANCE
69
Patent #:
8201032
Issue Dt:
06/12/2012
Application #:
11775956
Filing Dt:
07/11/2007
Publication #:
US20080016418
Pub Dt:
01/17/2008
Title:
GENERALIZED BIST FOR MULTIPORT MEMORIES
70
Patent #:
7541669
Issue Dt:
06/02/2009
Application #:
11788346
Filing Dt:
04/19/2007
Publication #:
US20070241433
Pub Dt:
10/18/2007
Title:
SEMICONDUCTOR DEVICE PACKAGE WITH BASE FEATURES TO REDUCE LEAKAGE
71
Patent #:
7633118
Issue Dt:
12/15/2009
Application #:
11809686
Filing Dt:
05/31/2007
Publication #:
US20070228440
Pub Dt:
10/04/2007
Title:
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
72
Patent #:
7491610
Issue Dt:
02/17/2009
Application #:
11809873
Filing Dt:
06/01/2007
Publication #:
US20070238243
Pub Dt:
10/11/2007
Title:
FABRICATION METHOD
73
Patent #:
7384801
Issue Dt:
06/10/2008
Application #:
11811519
Filing Dt:
06/11/2007
Publication #:
US20070254448
Pub Dt:
11/01/2007
Title:
INTEGRATED CIRCUIT WITH INDUCTOR HAVING HORIZONTAL MAGNETIC FLUX LINES
74
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7800226
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Assignors
1
HILCO PATENT ACQUISITION 56, LLC
Exec Dt:
01/24/2018
2
BELL SEMICONDUCTOR, LLC
Exec Dt:
01/24/2018
3
BELL NORTHERN RESEARCH, LLC
Exec Dt:
01/24/2018
Assignee
1
CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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