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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 34 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
8115321
Issue Dt:
02/14/2012
Application #:
12432763
Filing Dt:
04/30/2009
Publication #:
US20100276816
Pub Dt:
11/04/2010
Title:
SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT
2
Patent #:
8099708
Issue Dt:
01/17/2012
Application #:
12432996
Filing Dt:
04/30/2009
Publication #:
US20090210846
Pub Dt:
08/20/2009
Title:
I/O PLANNING WITH LOCK AND INSERTION FEATURES
3
Patent #:
8013428
Issue Dt:
09/06/2011
Application #:
12462069
Filing Dt:
07/28/2009
Publication #:
US20090291321
Pub Dt:
11/26/2009
Title:
WHISKER-FREE LEAD FRAMES
4
Patent #:
8161447
Issue Dt:
04/17/2012
Application #:
12463509
Filing Dt:
05/11/2009
Publication #:
US20090228855
Pub Dt:
09/10/2009
Title:
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE
5
Patent #:
7724023
Issue Dt:
05/25/2010
Application #:
12463718
Filing Dt:
05/11/2009
Title:
CIRCUIT APPARATUS INCLUDING REMOVABLE BOND PAD EXTENSION
6
Patent #:
8037771
Issue Dt:
10/18/2011
Application #:
12465309
Filing Dt:
05/13/2009
Publication #:
US20100288048
Pub Dt:
11/18/2010
Title:
ELECTRONIC PRESSURE-SENSING DEVICE
7
Patent #:
8324019
Issue Dt:
12/04/2012
Application #:
12469985
Filing Dt:
05/21/2009
Publication #:
US20090289348
Pub Dt:
11/26/2009
Title:
SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION
8
Patent #:
8101871
Issue Dt:
01/24/2012
Application #:
12471982
Filing Dt:
05/26/2009
Publication #:
US20100300741
Pub Dt:
12/02/2010
Title:
ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY
9
Patent #:
7898038
Issue Dt:
03/01/2011
Application #:
12476994
Filing Dt:
06/02/2009
Publication #:
US20090236668
Pub Dt:
09/24/2009
Title:
METHOD TO IMPROVE WRITER LEAKAGE IN SIGE BIPOLAR DEVICE
10
Patent #:
7993981
Issue Dt:
08/09/2011
Application #:
12483139
Filing Dt:
06/11/2009
Publication #:
US20100314747
Pub Dt:
12/16/2010
Title:
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
11
Patent #:
8370777
Issue Dt:
02/05/2013
Application #:
12485238
Filing Dt:
06/16/2009
Publication #:
US20100318340
Pub Dt:
12/16/2010
Title:
METHOD OF GENERATING A LEADFRAME IC PACKAGE MODEL, A LEADFRAME MODELER AND AN IC DESIGN SYSTEM
12
Patent #:
8334467
Issue Dt:
12/18/2012
Application #:
12486592
Filing Dt:
06/17/2009
Publication #:
US20100319987
Pub Dt:
12/23/2010
Title:
LEAD FRAME DESIGN TO IMPROVE RELIABILITY
13
Patent #:
8681730
Issue Dt:
03/25/2014
Application #:
12500564
Filing Dt:
07/09/2009
Publication #:
US20110007704
Pub Dt:
01/13/2011
Title:
METHOD AND SYSTEM FOR USING SIGN BASED SYNCHRONIZATION SEQUENCES IN A CORRELATION PROCESS TO REDUCE CORRELATION COMPLEXITY IN AN OFDM SYSTEM
14
Patent #:
8378485
Issue Dt:
02/19/2013
Application #:
12501686
Filing Dt:
07/13/2009
Publication #:
US20110006415
Pub Dt:
01/13/2011
Title:
SOLDER INTERCONNECT BY ADDITION OF COPPER
15
Patent #:
8097179
Issue Dt:
01/17/2012
Application #:
12502057
Filing Dt:
07/13/2009
Publication #:
US20090275204
Pub Dt:
11/05/2009
Title:
METHOD FOR ABATING EFFLUENT FROM AN ETCHING PROCESS
16
Patent #:
7957450
Issue Dt:
06/07/2011
Application #:
12506053
Filing Dt:
07/20/2009
Publication #:
US20100008411
Pub Dt:
01/14/2010
Title:
METHOD AND SYSTEM FOR FRAME FORMATS FOR MIMO CHANNEL MEASUREMENT EXCHANGE
17
Patent #:
7981305
Issue Dt:
07/19/2011
Application #:
12506090
Filing Dt:
07/20/2009
Publication #:
US20090280585
Pub Dt:
11/12/2009
Title:
HIGH-DENSITY FIELD EMISSION ELEMENTS AND A METHOD FOR FORMING SAID EMISSION ELEMENTS
18
Patent #:
7948036
Issue Dt:
05/24/2011
Application #:
12506746
Filing Dt:
07/21/2009
Publication #:
US20090294856
Pub Dt:
12/03/2009
Title:
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
19
Patent #:
8245168
Issue Dt:
08/14/2012
Application #:
12508320
Filing Dt:
07/23/2009
Publication #:
US20100023904
Pub Dt:
01/28/2010
Title:
METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
20
Patent #:
8219959
Issue Dt:
07/10/2012
Application #:
12508898
Filing Dt:
07/24/2009
Publication #:
US20110023000
Pub Dt:
01/27/2011
Title:
GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS
21
Patent #:
8122422
Issue Dt:
02/21/2012
Application #:
12510082
Filing Dt:
07/27/2009
Publication #:
US20110023004
Pub Dt:
01/27/2011
Title:
ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLTAGE SCALING, ANALYZING THE BENEFITS AND AN APPARATUS THEREFOR
22
Patent #:
8239805
Issue Dt:
08/07/2012
Application #:
12510104
Filing Dt:
07/27/2009
Publication #:
US20110022998
Pub Dt:
01/27/2011
Title:
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
23
Patent #:
8127264
Issue Dt:
02/28/2012
Application #:
12510122
Filing Dt:
07/27/2009
Publication #:
US20110022996
Pub Dt:
01/27/2011
Title:
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS
24
Patent #:
8143696
Issue Dt:
03/27/2012
Application #:
12516301
Filing Dt:
05/26/2009
Publication #:
US20100314713
Pub Dt:
12/16/2010
Title:
INTEGRATED CIRCUIT INDUCTORS WITH REDUCED MAGNETIC COUPLING
25
Patent #:
7923340
Issue Dt:
04/12/2011
Application #:
12523368
Filing Dt:
07/16/2009
Publication #:
US20100065920
Pub Dt:
03/18/2010
Title:
METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A STANDARD CMOS FLOW
26
Patent #:
8222719
Issue Dt:
07/17/2012
Application #:
12526334
Filing Dt:
08/07/2009
Publication #:
US20100148329
Pub Dt:
06/17/2010
Title:
QUAD FLAT NO LEAD (QFN) INTEGRATED CIRCUIT (IC) PACKAGE HAVING A MODIFIED PADDLE AND METHOD FOR DESIGNING THE PACKAGE
27
Patent #:
7923347
Issue Dt:
04/12/2011
Application #:
12546083
Filing Dt:
08/24/2009
Publication #:
US20090311853
Pub Dt:
12/17/2009
Title:
CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
28
Patent #:
8318606
Issue Dt:
11/27/2012
Application #:
12546855
Filing Dt:
08/25/2009
Publication #:
US20110053378
Pub Dt:
03/03/2011
Title:
DIELECTRIC ETCHING
29
Patent #:
7912024
Issue Dt:
03/22/2011
Application #:
12553281
Filing Dt:
09/03/2009
Publication #:
US20100014498
Pub Dt:
01/21/2010
Title:
METHOD AND APPARATUS FOR WIDE BANDWIDTH MIXED-MODE WIRELESS COMMUNICATIONS
30
Patent #:
7927940
Issue Dt:
04/19/2011
Application #:
12555082
Filing Dt:
09/08/2009
Publication #:
US20090325353
Pub Dt:
12/31/2009
Title:
METHOD OF MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
31
Patent #:
8021955
Issue Dt:
09/20/2011
Application #:
12574426
Filing Dt:
10/06/2009
Title:
METHOD CHARACTERIZING MATERIALS FOR A TRENCH ISOLATION STRUCTURE HAVING LOW TRENCH PARASITIC CAPACITANCE
32
Patent #:
7956401
Issue Dt:
06/07/2011
Application #:
12574479
Filing Dt:
10/06/2009
Publication #:
US20100022060
Pub Dt:
01/28/2010
Title:
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS
33
Patent #:
8484608
Issue Dt:
07/09/2013
Application #:
12576775
Filing Dt:
10/09/2009
Publication #:
US20100031222
Pub Dt:
02/04/2010
Title:
BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME
34
Patent #:
9118442
Issue Dt:
08/25/2015
Application #:
12577080
Filing Dt:
10/09/2009
Publication #:
US20110085493
Pub Dt:
04/14/2011
Title:
METHOD AND SYSTEM FOR CONTINUOUS PACKET CONNECTIVITY
35
Patent #:
8284819
Issue Dt:
10/09/2012
Application #:
12582771
Filing Dt:
10/21/2009
Publication #:
US20110090996
Pub Dt:
04/21/2011
Title:
METHOD AND SYSTEM FOR INTERFERENCE SUPPRESSION IN WCDMA SYSTEMS
36
Patent #:
8332801
Issue Dt:
12/11/2012
Application #:
12608469
Filing Dt:
10/29/2009
Publication #:
US20100050142
Pub Dt:
02/25/2010
Title:
SPECIAL ENGINEERING CHANGE ORDER CELLS
37
Patent #:
7911006
Issue Dt:
03/22/2011
Application #:
12610733
Filing Dt:
11/02/2009
Publication #:
US20100044767
Pub Dt:
02/25/2010
Title:
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
38
Patent #:
8039923
Issue Dt:
10/18/2011
Application #:
12616050
Filing Dt:
11/10/2009
Publication #:
US20100061036
Pub Dt:
03/11/2010
Title:
INTERDIGITATED CAPACITORS
39
Patent #:
8119501
Issue Dt:
02/21/2012
Application #:
12618936
Filing Dt:
11/16/2009
Publication #:
US20100221893
Pub Dt:
09/02/2010
Title:
METHOD FOR SEPARATING A SEMICONDUCTOR WAFER INTO INDIVIDUAL SEMICONDUCTOR DIES USING AN IMPLANTED IMPURITY
40
Patent #:
8129759
Issue Dt:
03/06/2012
Application #:
12625457
Filing Dt:
11/24/2009
Publication #:
US20100067207
Pub Dt:
03/18/2010
Title:
SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMODATE HIGH SPEED CIRCUITRY GROUND ISOLATION
41
Patent #:
8106480
Issue Dt:
01/31/2012
Application #:
12652560
Filing Dt:
01/05/2010
Publication #:
US20100102418
Pub Dt:
04/29/2010
Title:
BIPOLAR DEVICE HAVING IMPROVED CAPACITANCE
42
Patent #:
8183698
Issue Dt:
05/22/2012
Application #:
12678405
Filing Dt:
03/16/2010
Publication #:
US20100201000
Pub Dt:
08/12/2010
Title:
BOND PAD SUPPORT STRUCTURE FOR SEMICONDUCTOR DEVICE
43
Patent #:
NONE
Issue Dt:
Application #:
12680017
Filing Dt:
03/25/2010
Publication #:
US20100264478
Pub Dt:
10/21/2010
Title:
METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE
44
Patent #:
7990842
Issue Dt:
08/02/2011
Application #:
12684650
Filing Dt:
01/08/2010
Publication #:
US20100110876
Pub Dt:
05/06/2010
Title:
BACKWARD-COMPATIBLE LONG TRAINING SEQUENCES FOR WIRELESS COMMUNICATION NETWORKS
45
Patent #:
8030199
Issue Dt:
10/04/2011
Application #:
12689749
Filing Dt:
01/19/2010
Publication #:
US20100120216
Pub Dt:
05/13/2010
Title:
TRANSISTOR FABRICATION METHOD
46
Patent #:
8222745
Issue Dt:
07/17/2012
Application #:
12689806
Filing Dt:
01/19/2010
Publication #:
US20110176278
Pub Dt:
07/21/2011
Title:
INTEGRATED HEAT SINK
47
Patent #:
8084857
Issue Dt:
12/27/2011
Application #:
12692209
Filing Dt:
01/22/2010
Publication #:
US20100120198
Pub Dt:
05/13/2010
Title:
METHOD AND ARTICLE OF MANUFACTURE FOR WIRE BONDING WITH STAGGERED DIFFERENTIAL WIRE BOND PAIRS
48
Patent #:
8181138
Issue Dt:
05/15/2012
Application #:
12695396
Filing Dt:
01/28/2010
Publication #:
US20100131458
Pub Dt:
05/27/2010
Title:
GENERATION OF AN EXTRACTED TIMING MODEL FILE
49
Patent #:
NONE
Issue Dt:
Application #:
12706042
Filing Dt:
02/16/2010
Publication #:
US20100150260
Pub Dt:
06/17/2010
Title:
METHOD AND SYSTEM FOR MINIMIZING EFFECTS OF TRANSMITTER IMPAIRMENTS IN MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) BEAMFORMING COMMUNICATION SYSTEMS
50
Patent #:
7945285
Issue Dt:
05/17/2011
Application #:
12706047
Filing Dt:
02/16/2010
Publication #:
US20100144389
Pub Dt:
06/10/2010
Title:
INTEGRATING A DIGITAL ENCODED-AUDIO BIT STREAM PLAYER IN A RADIO-FREQUENCY TELEPHONE HANDSET
51
Patent #:
8306142
Issue Dt:
11/06/2012
Application #:
12724134
Filing Dt:
03/15/2010
Publication #:
US20100226456
Pub Dt:
09/09/2010
Title:
METHOD AND SYSTEM FOR TRANSMITTER BEAMFORMING FOR REDUCED COMPLEXITY MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) TRANSCEIVERS
52
Patent #:
7910425
Issue Dt:
03/22/2011
Application #:
12727304
Filing Dt:
03/19/2010
Publication #:
US20100173459
Pub Dt:
07/08/2010
Title:
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
53
Patent #:
8227319
Issue Dt:
07/24/2012
Application #:
12728412
Filing Dt:
03/22/2010
Publication #:
US20110230031
Pub Dt:
09/22/2011
Title:
BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR
54
Patent #:
8242603
Issue Dt:
08/14/2012
Application #:
12741839
Filing Dt:
07/08/2010
Publication #:
US20100270684
Pub Dt:
10/28/2010
Title:
CHIP IDENTIFICATION USING TOP METAL LAYER
55
Patent #:
NONE
Issue Dt:
Application #:
12748722
Filing Dt:
03/29/2010
Publication #:
US20100246717
Pub Dt:
09/30/2010
Title:
INTERLEAVING IN A WIRELESS COMMUNICATION SYSTEM
56
Patent #:
8300747
Issue Dt:
10/30/2012
Application #:
12763670
Filing Dt:
04/20/2010
Publication #:
US20100202573
Pub Dt:
08/12/2010
Title:
METHOD AND SYSTEM FOR AN ADAPTIVE VBLAST RECEIVER FOR WIRELESS MULTIPLE INPUT MULTIPLE OUTOUT (MIMO) DETECTION
57
Patent #:
8043968
Issue Dt:
10/25/2011
Application #:
12764004
Filing Dt:
04/20/2010
Publication #:
US20100200993
Pub Dt:
08/12/2010
Title:
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
58
Patent #:
8917704
Issue Dt:
12/23/2014
Application #:
12768415
Filing Dt:
04/27/2010
Publication #:
US20110243105
Pub Dt:
10/06/2011
Title:
METHOD AND SYSTEM FOR AUTOMATICALLY RESCALING AN ACCUMULATION BUFFER IN SYNCHRONIZATION SYSTEMS
59
Patent #:
8584068
Issue Dt:
11/12/2013
Application #:
12779312
Filing Dt:
05/13/2010
Publication #:
US20100229141
Pub Dt:
09/09/2010
Title:
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
60
Patent #:
8321826
Issue Dt:
11/27/2012
Application #:
12791260
Filing Dt:
06/01/2010
Publication #:
US20100289112
Pub Dt:
11/18/2010
Title:
METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER
61
Patent #:
8084313
Issue Dt:
12/27/2011
Application #:
12832110
Filing Dt:
07/08/2010
Publication #:
US20100273301
Pub Dt:
10/28/2010
Title:
THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRNASISTORS FORMED ACCORDING TO THE METHOD
62
Patent #:
8332792
Issue Dt:
12/11/2012
Application #:
12836274
Filing Dt:
07/14/2010
Publication #:
US20120017190
Pub Dt:
01/19/2012
Title:
IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
63
Patent #:
8411399
Issue Dt:
04/02/2013
Application #:
12839148
Filing Dt:
07/19/2010
Publication #:
US20110051304
Pub Dt:
03/03/2011
Title:
DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING CAPACITORS
64
Patent #:
8492911
Issue Dt:
07/23/2013
Application #:
12840016
Filing Dt:
07/20/2010
Publication #:
US20120020028
Pub Dt:
01/26/2012
Title:
STACKED INTERCONNECT HEAT SINK
65
Patent #:
8196086
Issue Dt:
06/05/2012
Application #:
12840535
Filing Dt:
07/21/2010
Publication #:
US20120023473
Pub Dt:
01/26/2012
Title:
GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION
66
Patent #:
8384226
Issue Dt:
02/26/2013
Application #:
12885722
Filing Dt:
09/20/2010
Publication #:
US20110006395
Pub Dt:
01/13/2011
Title:
HYBRID BUMP CAPACITOR
67
Patent #:
8527912
Issue Dt:
09/03/2013
Application #:
12890336
Filing Dt:
09/24/2010
Publication #:
US20110016436
Pub Dt:
01/20/2011
Title:
Digitally Obtaining Contours of Fabricated Polygons
68
Patent #:
8484008
Issue Dt:
07/09/2013
Application #:
12901588
Filing Dt:
10/11/2010
Publication #:
US20120089383
Pub Dt:
04/12/2012
Title:
METHODS AND SYSTEMS FOR PERFORMING TIMING SIGN-OFF OF AN INTEGRATED CIRCUIT DESIGN
69
Patent #:
8341573
Issue Dt:
12/25/2012
Application #:
12905301
Filing Dt:
10/15/2010
Publication #:
US20120095746
Pub Dt:
04/19/2012
Title:
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
70
Patent #:
8017512
Issue Dt:
09/13/2011
Application #:
12912791
Filing Dt:
10/27/2010
Publication #:
US20110039398
Pub Dt:
02/17/2011
Title:
EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A NANOTUBE STRUCTURE
71
Patent #:
8289051
Issue Dt:
10/16/2012
Application #:
12947948
Filing Dt:
11/17/2010
Publication #:
US20120119785
Pub Dt:
05/17/2012
Title:
INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
72
Patent #:
8624352
Issue Dt:
01/07/2014
Application #:
12953624
Filing Dt:
11/24/2010
Publication #:
US20120126364
Pub Dt:
05/24/2012
Title:
MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK
73
Patent #:
8987137
Issue Dt:
03/24/2015
Application #:
12969836
Filing Dt:
12/16/2010
Publication #:
US20120153492
Pub Dt:
06/21/2012
Title:
METHOD OF FABRICATION OF THROUGH-SUBSTRATE VIAS
74
Patent #:
8742535
Issue Dt:
06/03/2014
Application #:
12969852
Filing Dt:
12/16/2010
Publication #:
US20120153430
Pub Dt:
06/21/2012
Title:
INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
75
Patent #:
8792432
Issue Dt:
07/29/2014
Application #:
13026512
Filing Dt:
02/14/2011
Publication #:
US20120207102
Pub Dt:
08/16/2012
Title:
Prioritizing RACH Message Contents
76
Patent #:
8143120
Issue Dt:
03/27/2012
Application #:
13026528
Filing Dt:
02/14/2011
Publication #:
US20110133289
Pub Dt:
06/09/2011
Title:
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
77
Patent #:
8396072
Issue Dt:
03/12/2013
Application #:
13031355
Filing Dt:
02/21/2011
Publication #:
US20120213071
Pub Dt:
08/23/2012
Title:
Method and Apparatus for Channel Traffic Congestion Avoidance in a Mobile Communication System
78
Patent #:
8547681
Issue Dt:
10/01/2013
Application #:
13032429
Filing Dt:
02/22/2011
Publication #:
US20120212878
Pub Dt:
08/23/2012
Title:
DECOUPLING CAPACITOR
79
Patent #:
8133799
Issue Dt:
03/13/2012
Application #:
13041674
Filing Dt:
03/07/2011
Publication #:
US20110250742
Pub Dt:
10/13/2011
Title:
CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
80
Patent #:
8283713
Issue Dt:
10/09/2012
Application #:
13046973
Filing Dt:
03/14/2011
Publication #:
US20110298026
Pub Dt:
12/08/2011
Title:
LOGIC-BASED EDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS
81
Patent #:
8539424
Issue Dt:
09/17/2013
Application #:
13058176
Filing Dt:
02/08/2011
Publication #:
US20110138347
Pub Dt:
06/09/2011
Title:
SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADAPTIVE VOLTAGE SCALING OPTIMIZATION
82
Patent #:
8653375
Issue Dt:
02/18/2014
Application #:
13059502
Filing Dt:
02/17/2011
Publication #:
US20110155418
Pub Dt:
06/30/2011
Title:
MITIGATION OF WHISKERS IN SN-FILMS
83
Patent #:
8599755
Issue Dt:
12/03/2013
Application #:
13069108
Filing Dt:
03/22/2011
Publication #:
US20110211529
Pub Dt:
09/01/2011
Title:
METHOD AND APPARATUS FOR WIDE BANDWIDTH MIXED-MODE WIRELESS COMMUNICATIONS
84
Patent #:
8507317
Issue Dt:
08/13/2013
Application #:
13093032
Filing Dt:
04/25/2011
Publication #:
US20110195544
Pub Dt:
08/11/2011
Title:
SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
85
Patent #:
8200280
Issue Dt:
06/12/2012
Application #:
13096420
Filing Dt:
04/28/2011
Publication #:
US20110201384
Pub Dt:
08/18/2011
Title:
CORDLESS TELEPHONE WITH DIGITAL AUDIO PLAYER CAPABILITY
86
Patent #:
8397196
Issue Dt:
03/12/2013
Application #:
13099948
Filing Dt:
05/03/2011
Publication #:
US20120284679
Pub Dt:
11/08/2012
Title:
INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS
87
Patent #:
8437419
Issue Dt:
05/07/2013
Application #:
13100014
Filing Dt:
05/03/2011
Publication #:
US20110222620
Pub Dt:
09/15/2011
Title:
METHOD AND SYSTEM FOR FRAME FORMATS FOR MIMO CHANNEL MEASUREMENT EXCHANGE
88
Patent #:
8589853
Issue Dt:
11/19/2013
Application #:
13103461
Filing Dt:
05/09/2011
Publication #:
US20120290994
Pub Dt:
11/15/2012
Title:
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
89
Patent #:
8269280
Issue Dt:
09/18/2012
Application #:
13110581
Filing Dt:
05/18/2011
Publication #:
US20110215410
Pub Dt:
09/08/2011
Title:
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
90
Patent #:
8464202
Issue Dt:
06/11/2013
Application #:
13114834
Filing Dt:
05/12/2002
Publication #:
US20120304140
Pub Dt:
11/29/2012
Title:
FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY
91
Patent #:
8610215
Issue Dt:
12/17/2013
Application #:
13119005
Filing Dt:
03/15/2011
Publication #:
US20110163419
Pub Dt:
07/07/2011
Title:
ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS
92
Patent #:
8105912
Issue Dt:
01/31/2012
Application #:
13149122
Filing Dt:
05/31/2011
Publication #:
US20110230032
Pub Dt:
09/22/2011
Title:
HIGH VOLTAGE TOLERANT METAL-OXIDE-SEMICONDUCTOR DEVICE
93
Patent #:
8423933
Issue Dt:
04/16/2013
Application #:
13150607
Filing Dt:
06/01/2011
Publication #:
US20110239171
Pub Dt:
09/29/2011
Title:
STAGED SCENARIO GENERATION
94
Patent #:
8239813
Issue Dt:
08/07/2012
Application #:
13173855
Filing Dt:
06/30/2011
Publication #:
US20110258587
Pub Dt:
10/20/2011
Title:
METHOD AND APPARATUS FOR BALANCING SIGNAL DELAY SKEW
95
Patent #:
8384205
Issue Dt:
02/26/2013
Application #:
13174970
Filing Dt:
07/01/2011
Publication #:
US20110260324
Pub Dt:
10/27/2011
Title:
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
96
Patent #:
8477594
Issue Dt:
07/02/2013
Application #:
13196082
Filing Dt:
08/02/2011
Publication #:
US20110280117
Pub Dt:
11/17/2011
Title:
BACKWARD-COMPATIBLE LONG TRAINING SEQUENCES FOR WIRELESS COMMUNICATION NETWORKS
97
Patent #:
8307324
Issue Dt:
11/06/2012
Application #:
13212427
Filing Dt:
08/18/2011
Publication #:
US20110307852
Pub Dt:
12/15/2011
Title:
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
98
Patent #:
8502372
Issue Dt:
08/06/2013
Application #:
13217857
Filing Dt:
08/25/2011
Publication #:
US20120049353
Pub Dt:
03/01/2012
Title:
LOW-COST 3D FACE-TO-FACE OUT ASSEMBLY
99
Patent #:
8372723
Issue Dt:
02/12/2013
Application #:
13222877
Filing Dt:
08/31/2011
Publication #:
US20110312146
Pub Dt:
12/22/2011
Title:
BIPOLAR DEVICE HAVING BURIED CONTACTS
100
Patent #:
8516424
Issue Dt:
08/20/2013
Application #:
13246102
Filing Dt:
09/27/2011
Publication #:
US20130080986
Pub Dt:
03/28/2013
Title:
TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLTAGE DROP INTO ACCOUNT
Assignors
1
HILCO PATENT ACQUISITION 56, LLC
Exec Dt:
01/24/2018
2
BELL SEMICONDUCTOR, LLC
Exec Dt:
01/24/2018
3
BELL NORTHERN RESEARCH, LLC
Exec Dt:
01/24/2018
Assignee
1
CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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