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Patent #:
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01/05/1999
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08572599
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Filing Dt:
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12/14/1995
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Title:
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CASSETTE LIGHT
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Patent #:
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Issue Dt:
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06/16/1998
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08573892
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Filing Dt:
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12/18/1995
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Title:
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SYSTEMS HAVING SHAPED, SELF-ALIGNING MICRO-BUMP STRUCTURES
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Issue Dt:
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11/04/1997
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08573923
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Filing Dt:
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12/18/1995
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Title:
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METHOD OF FORMING VIAS
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Patent #:
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Issue Dt:
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06/20/2000
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08577077
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Filing Dt:
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12/22/1995
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Title:
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INTEGRATED CIRCUIT PROCESSING UTILIZING MICROWAVE RADIATION
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Patent #:
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Issue Dt:
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06/30/1998
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08577454
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Filing Dt:
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12/22/1995
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Title:
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METHOD AND APPARATUS FOR PSEUDORANDOM BOUNDARY-SCAN TESTING
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Patent #:
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Issue Dt:
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07/07/1998
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08578118
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Filing Dt:
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12/27/1995
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Title:
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METHOF OF FORMING A HIGH ELECTROMIGRATION RESISTANT METALLIZATION SYSTEM
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Patent #:
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Issue Dt:
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11/11/1997
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08578743
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Filing Dt:
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12/26/1995
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Title:
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PROCESS MONITOR FOR CMOS INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/15/1997
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Application #:
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08578746
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Filing Dt:
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12/26/1995
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Title:
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SENSING DEVICE FOR CAPTURING A LIGHT IMAGE
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08578816
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Filing Dt:
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12/26/1995
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Title:
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MULTILAYER STRUCTURES AND PROCESS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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09/29/1998
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Application #:
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08578966
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Filing Dt:
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12/27/1995
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Title:
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METHOD OF MANUFACTURING POWDERED METAL SINKS HAVING INCREASED SURFACE AREA
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Patent #:
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Issue Dt:
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09/21/1999
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08579383
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Filing Dt:
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12/27/1995
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Title:
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METHOD FOR IMPROVEMENT OF TIN CVD FILM QUALITY
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Patent #:
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Issue Dt:
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07/08/1997
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08580674
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Filing Dt:
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12/29/1995
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Title:
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METHOD FOR POLISHING A WAFER
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Patent #:
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Issue Dt:
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10/06/1998
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08580800
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Filing Dt:
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12/29/1995
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Title:
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SYSTEM HAVING INTEGRATED CIRCUIT PACKAGE WITH LEAD FRAME HAVING INTERNAL POWER AND GROUND BUSSES
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Issue Dt:
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11/23/1999
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08580908
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Filing Dt:
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12/29/1995
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Title:
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HIGH DENSITY GATE ARRAY CELL ARCHITECTURE WITH METALLIZATION ROUTING TRACKS HAVING A VARIABLE PITCH
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Patent #:
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Issue Dt:
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07/06/1999
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08581299
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12/28/1995
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Title:
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SOLDER BONDING OF DENSE ARRAYS OF MICROMINITURE CONTACT PADS
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Issue Dt:
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10/28/1997
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08581665
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Filing Dt:
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12/29/1995
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Title:
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METHOD FOR MAKING BIPOLAR TRANSISTORS HAVING INDIUM DOPED BASE
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Patent #:
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Issue Dt:
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07/28/1998
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08586174
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Filing Dt:
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01/17/1996
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Title:
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LOOP-BACK TEST SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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04/06/1999
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08586412
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Filing Dt:
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01/16/1996
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Title:
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REDUCTION IN DAMAGE TO OPTICAL ELEMENTS USED IN OPTICAL LITHOGRAPHY FOR DEVICE FABRICATION
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Issue Dt:
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10/16/2001
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08586587
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Filing Dt:
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01/11/1996
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Title:
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SIDEWALL STRUCTURE FOR METAL INTERCONNECT AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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12/24/2002
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08587061
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Filing Dt:
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01/16/1996
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Title:
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TRANSISTOR FABRICATION METHOD
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Patent #:
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Issue Dt:
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04/29/1997
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Application #:
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08587426
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Filing Dt:
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01/16/1996
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Title:
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ARTICLE COMPRISING COMPLEMENTARY CIRCUIT WITH INORGANIC N-CHANNEL AND ORGANIC P-CHANNEL
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Patent #:
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Issue Dt:
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08/12/1997
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08589229
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Filing Dt:
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01/22/1996
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Title:
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PROCESS FOR MAKING AN X-RAY MASK
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Issue Dt:
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09/14/1999
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08592870
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01/24/1996
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Title:
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LOW STRESS, HIGHLY CONFORMAL CVD METAL THIN FILM
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Patent #:
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Issue Dt:
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02/09/1999
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08595021
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Filing Dt:
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01/31/1996
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Title:
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MICROELECTRONIC DEVICE WITH THIN FILM ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE
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Issue Dt:
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06/17/1997
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Application #:
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08595022
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Filing Dt:
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01/31/1996
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Title:
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MICROELECTRONIC INTEGRATED CIRCUIT MOUNTED ON CIRCUIT BOARD WITH SOLDER COLUMN GRID ARRAY INTERCONNECTION, AND METHOD OF FABRICATING THE SOLDER COLUMN GRID ARRAY
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08595543
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Filing Dt:
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02/02/1996
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Title:
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ARTICLES COMPRISING MAGNETICALLY SOFT THIN FILMS AND METHODS FOR MAKING SUCH ARTICLES
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Patent #:
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Issue Dt:
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06/02/1998
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Application #:
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08596894
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Filing Dt:
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01/25/1996
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Title:
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VARIABLE WIDTH LOW PROFILE GATE ARRAY INPUT/OUTPUT ARCHITECTURE
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08599289
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Filing Dt:
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02/09/1996
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Title:
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METHOD FOR IDENTIFYING UNTESTABLE & REDUNDANT FAULTS IN SEQUENTIAL LOGIC CIRCUITS.
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Patent #:
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Issue Dt:
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04/28/1998
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Application #:
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08600588
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Filing Dt:
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02/13/1996
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Title:
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METHOD AND SYSTEM FOR IMPROVING A PLACEMENT OF CELLS USING ENERGETIC PLACEMENT WITH ALTERNATING CONTRACTION AND EXPANSION OPERATIONS
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08604181
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Filing Dt:
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02/21/1996
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Title:
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YIMULTANEOUS PLACEMENT AND ROUTING (SPAR) METHOD FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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11/18/1997
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Application #:
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08604867
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Filing Dt:
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02/14/1996
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Title:
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METHOD FOR FORMING COMPOSITE TRENCH-FIN CAPACITORS FOR DRAMS
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Patent #:
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Issue Dt:
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03/03/1998
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Application #:
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08607365
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Filing Dt:
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02/27/1996
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Title:
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OPTICAL PROXIMITY CORRECTION METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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01/06/1998
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Application #:
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08607398
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Filing Dt:
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02/27/1996
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Title:
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PERFORMING OPTICAL PROXIMITY CORRECTION WITH THE AID OF DESIGN RULE CHECKERS
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Patent #:
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Issue Dt:
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08/18/1998
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08608609
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Filing Dt:
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02/29/1996
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Title:
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METHOD FOR METAL DELAY TESTING IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08608679
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Filing Dt:
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02/29/1996
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Title:
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APPARATUS FOR FORMING ELECTRICAL CONNECTIONS BETWEEN A SEMICONDUCTOR DIE AND A SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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08/18/1998
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08609359
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Filing Dt:
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03/01/1996
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIP USING SIMULATED ANNEALING WITH "CHESSBOARD" AND "JIGGLE" OPTIMIZATION
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Patent #:
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Issue Dt:
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03/14/2000
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08609397
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Filing Dt:
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03/01/1996
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIP USING "CHESSBOARD" AND "JIGGLE" OPTIMIZATION
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08610026
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Filing Dt:
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03/04/1996
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Title:
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A HETEROJUNCTION BIPOLAR TRANSISTOR HAVING MONO CRYSTALLING SIGE INTRINSIC BASE AND POLYCRYSTALLINE SIGE AND SI EXTRINSIC BASE REGIONS
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Patent #:
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Issue Dt:
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04/15/1997
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Application #:
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08610646
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Filing Dt:
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03/04/1996
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Title:
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METHOD FOR MAKING A HETEROJUNCTION BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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05/11/1999
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08611325
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Filing Dt:
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03/08/1996
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Title:
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TEST SHELLS FOR PROTECTING PROPRIETARY INFORMATION IN ASIC CORES
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Patent #:
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Issue Dt:
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05/20/1997
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Application #:
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08612337
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Filing Dt:
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03/06/1996
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Title:
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METHOD OF MAKING COMBINED JFET & MOS TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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12/16/1997
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Application #:
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08613040
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Filing Dt:
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03/08/1996
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Title:
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HIGH DENSITY GATE ARRAY BASE CELL ARCHITECTURE
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Patent #:
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Issue Dt:
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08/18/1998
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Application #:
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08613161
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Filing Dt:
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03/08/1996
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Title:
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GUARD RINGS TO COMPENSATE FOR SIDE LOBE RINGING IN ATTENUATED PHASE SHIFT RETICLES
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Patent #:
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Issue Dt:
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09/01/1998
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Application #:
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08615388
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Filing Dt:
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03/14/1996
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Title:
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METHOD OF PACKAGING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/26/1997
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Application #:
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08615437
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Filing Dt:
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03/14/1996
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Title:
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PLASMA CLEAN WITH HYDROGEN GAS
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Patent #:
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Issue Dt:
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03/03/1998
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Application #:
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08615865
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Filing Dt:
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03/14/1996
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Title:
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METHOD OF FLIP CHIP ASSEMBLY
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Patent #:
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Issue Dt:
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06/10/1997
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Application #:
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08616070
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Filing Dt:
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03/14/1996
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Title:
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PROTECTING PROPRIETARY ASIC DESIGN INFORMATION USING BOUNDARY SCAN ON SELECTIVE INPUTS AND OUTPUTS
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Patent #:
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Issue Dt:
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11/11/1997
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Application #:
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08619909
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Filing Dt:
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03/20/1996
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Title:
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FLIP CHIP PACKAGE WITH REDUCED NUMBER OF PACKAGE LAYERS
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Patent #:
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Issue Dt:
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06/09/1998
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Application #:
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08620964
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Filing Dt:
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03/22/1996
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Title:
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PROCESS FOR FORMING ISOLATION REGIONS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/09/1998
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Application #:
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08622795
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Filing Dt:
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03/27/1996
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Title:
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HOLOGRAPHIC METHOD FOR GENERATING THREE DIMENSIONAL CONFORMAL PHOTO-LITHOGRAPHIC MASKS
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Patent #:
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Issue Dt:
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01/06/1998
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Application #:
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08622797
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Filing Dt:
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03/27/1996
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Title:
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HOLOGRAPHIC METHOD FOR GENERATING THREE DIMENSIONAL CONFORMAL PHOTO- LITHOGRAPHIC MASKS
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Patent #:
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Issue Dt:
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01/19/1999
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Application #:
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08623470
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Filing Dt:
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03/28/1996
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Title:
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METHOD AND APPARATUS FOR PROTECTING FUNCTIONS IMBEDDED WITHIN AN INTEGRATED CIRCUIT FROM REVERSE ENGINEERING
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08626773
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Filing Dt:
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04/02/1996
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Title:
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HARDWARE SYSTEM VERIFICATION ENVIRONMENT TOOL
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Patent #:
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Issue Dt:
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08/04/1998
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Application #:
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08626776
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Filing Dt:
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04/02/1996
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Title:
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MULTILEVEL METALLIZATION STRUCTURE FOR INTEGRATED CIRCUIT I/O LINES FOR INCREASED CURRENT CAPACITY AND ESD PROTECTION
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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08627411
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Filing Dt:
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04/01/1996
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Title:
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SYSTEM HAVING HEAT DISSIPATING LEADFRAMES
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Patent #:
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Issue Dt:
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03/17/1998
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Application #:
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08627560
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Filing Dt:
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04/04/1996
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Title:
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PROCESS FOR DEVICE FABRICATION IN WHICH A THIN LAYER OF COBALT SILICIDE IS FORMED
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08627622
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Filing Dt:
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04/04/1996
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Title:
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PROCESS MONITOR USING IMPEDANCE CONTROLLED I/O CONTROLLER
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08627823
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Filing Dt:
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05/10/1996
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Title:
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METHOD FOR CREATING AND USING DESIGN SHELLS FOR INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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08630257
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Filing Dt:
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04/10/1996
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Title:
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AUTOMATED DESIGN METHOD AND SYSTEM FOR SYNTHESIZING DIGITAL MULTIPLIERS
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Patent #:
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Issue Dt:
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03/02/1999
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Application #:
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08630267
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Filing Dt:
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04/10/1996
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Title:
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METHOD OF FORMING A PLANAR SURFACE DURING MULTI-LAYER INTERCONNECT FORMATION BY A LASER-ASSISTED DIELECTRIC DEPOSITION
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Issue Dt:
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05/18/1999
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Application #:
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08631360
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Filing Dt:
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04/12/1996
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Title:
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PROCESS FOR LOW ENERGY IMPLANTATION OF SEMICONDUCTOR SUBSTRATE USING CHANNELING TO FORM RETROGRADE WELLS
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Issue Dt:
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04/06/1999
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Application #:
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08632550
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Filing Dt:
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04/15/1996
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Title:
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UTILITY WAFER FOR CHEMICAL-MECHANICAL PLANARIZATION
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Patent #:
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Issue Dt:
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06/02/1998
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Application #:
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08632952
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Filing Dt:
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04/16/1996
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Title:
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CONDUCTIVE POLYMER BALL ATTACHMENT FOR GRID ARRAY SEMICONDUCTOR PACKAGES
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Patent #:
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Issue Dt:
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09/16/1997
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Application #:
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08633992
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Filing Dt:
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04/19/1996
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Title:
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METHOD FOR SOLDER-BONDING CONTACT PAD ARRAYS
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Patent #:
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Issue Dt:
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03/28/2000
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08635288
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Filing Dt:
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04/19/1996
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Title:
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CHIP ON TAPE DIE REFRAME PROCESS
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08636349
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Filing Dt:
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04/23/1996
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Title:
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SIMULTANEOUS PLACEMENT AND ROUTING (SPAR) METHOD FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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04/29/1997
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Application #:
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08637026
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Filing Dt:
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04/24/1996
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Title:
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INCREASING TESTABILITY BY CLOCK TRANSFORMATION
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08638003
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Filing Dt:
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04/25/1996
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Title:
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CONDUCTIVE ADHESIVE BONDING MEANS
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Patent #:
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Issue Dt:
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09/15/1998
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Application #:
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08641444
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Filing Dt:
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04/30/1996
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Title:
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MEMORY HAVING DIRECT STRAP CONNECTION TO POWER SUPPLY
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08644000
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Filing Dt:
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05/07/1996
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Title:
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INTEGRATED CIRCUIT UNDERFILL RESERVOIR
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Patent #:
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Issue Dt:
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12/22/1998
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Application #:
|
08644086
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Filing Dt:
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05/09/1996
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Title:
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METHOD FOR MAKING A CAPACITOR
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Patent #:
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Issue Dt:
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01/21/1997
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Application #:
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08644596
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Filing Dt:
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05/10/1996
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Title:
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ARTICLE COMPRISING AN ORGANIC THIN FILM TRANSISTOR
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Patent #:
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Issue Dt:
|
12/02/1997
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Application #:
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08645852
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Filing Dt:
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05/14/1996
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Title:
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METHOD OF INTEGRATED CIRCUIT FABRICATION INCLUDING A STEP OF DEPOSITING TUNGSTEN
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08646037
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Filing Dt:
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05/07/1996
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Title:
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SUPPORT MEMBER FOR MOUNTING A MICROELECTRONIC CIRCUIT PACKAGE
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Patent #:
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Issue Dt:
|
07/07/1998
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Application #:
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08647344
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Filing Dt:
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05/09/1996
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Title:
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SEMICONDUCTOR CHIP PACKAGE WITH INTERCONNECT LAYERS AND ROUTING AND TESTING METHODS
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Patent #:
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Issue Dt:
|
12/23/1997
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Application #:
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08648350
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Filing Dt:
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05/15/1996
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Title:
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METHOD OF PACKAGING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
03/25/2003
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Application #:
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08650248
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Filing Dt:
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05/22/1996
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Title:
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CLOCK SKEW INSENSITIVE SCAN CHAIN REORDERING
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Patent #:
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Issue Dt:
|
07/14/1998
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Application #:
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08650476
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Filing Dt:
|
05/20/1996
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Title:
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METHOD OF FORMING POLYSILICON LOGAL INTERCONNECTS
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Patent #:
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Issue Dt:
|
10/12/1999
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Application #:
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08651018
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Filing Dt:
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05/21/1996
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Title:
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METHOD FOR FABRICATING A LOW TRIGGER VOLTAGE SILICON CONTROLLED RECTIFIER AND THICK FIELD DEVICE
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Patent #:
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Issue Dt:
|
09/07/1999
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Application #:
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08652905
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Filing Dt:
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05/23/1996
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Title:
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CATALYTIC ACCELERATION AND ELECTRICAL BIAS CONTROL OF CMP PROCESSING
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Patent #:
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Issue Dt:
|
07/08/1997
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Application #:
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08652999
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Filing Dt:
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05/24/1996
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Title:
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STROBOSCOPIC PHOTOMETER
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|
|
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Patent #:
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Issue Dt:
|
01/20/1998
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Application #:
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08653264
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Filing Dt:
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05/24/1996
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Title:
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METHOD AND APPARATUS FOR FORMING DIELECTRIC FILMS
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|
|
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Patent #:
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Issue Dt:
|
12/30/1997
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Application #:
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08655249
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Filing Dt:
|
06/05/1996
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Title:
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MULTI-LEVEL RESOLUTION LITHOGRAPHY
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|
|
|
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Patent #:
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Issue Dt:
|
02/02/1999
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Application #:
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08655438
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Filing Dt:
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05/29/1996
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Title:
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DOMINO SCAN ARCHITECTURE AND DOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUITS
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|
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Patent #:
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Issue Dt:
|
09/30/1997
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Application #:
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08655599
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Filing Dt:
|
05/30/1996
|
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Title:
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APPARATUS TO DECOUPLE CORE CIRCUITS POWER SUPPLY FROM INPUT-OUTPUT CIRCUITS POWER SUPPLY IN A SEMICONDUCTOR DEVICE PACKAGE
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|
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Patent #:
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Issue Dt:
|
11/25/1997
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Application #:
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08656033
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Filing Dt:
|
05/31/1996
|
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Title:
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WIRE BONDABLE PACKAGE DESIGN WITH MAXIUM ELECTRICAL PERFORMANCE AND MINIMUM NUMBER OF LAYERS
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|
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Patent #:
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Issue Dt:
|
06/16/1998
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Application #:
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08656996
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Filing Dt:
|
05/24/1996
|
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Title:
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PMOSFETS HAVING INDIUM OR GALLIUM DOPED BURIED CHANNELS AND N+ POLYSILICON GATES AND CMOS DEVICES FABRICATED THEREFROM
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/29/1997
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Application #:
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08657255
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Filing Dt:
|
06/03/1996
|
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Title:
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HIGH-SPEED DOUBLE-HETEROSTRUCTURE BIPOLAR TRANSISTOR DEVICES
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|
|
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Patent #:
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Issue Dt:
|
12/02/1997
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Application #:
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08657390
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Filing Dt:
|
06/03/1996
|
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Title:
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OPTICAL PROBE MICROSCOPE HAVING A FIBER OPTIC TIP THAT RECEIVES BOTH A DITHER MOTION AND A SCANNING MOTION, FOR NONDESTRUCTIVE METROLOGY OF LARGE SAMPLE SURFACES
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|
|
|
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Patent #:
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Issue Dt:
|
04/07/1998
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Application #:
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08659860
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Filing Dt:
|
06/07/1996
|
|
Title:
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METHOD FOR FABRICATING A FIELD EFFECT TRANSISTOR USING MICROTRENCHES TO CONTROL HOT ELECTRON EFFECTS
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/07/1998
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Application #:
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08660632
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Filing Dt:
|
06/07/1996
|
|
Title:
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DOSE MODIFICATION PROXIMITY EFFECT COMPENSATION (PEC) TECHNIQUE FOR ELECTRON BEAM LITHOGRAPHY
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/25/1997
|
Application #:
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08661186
|
Filing Dt:
|
06/10/1996
|
|
Title:
|
GENERIC GATE LEVEL MODEL FOR CHARACTERIZATION OF GLITCH POWER IN LOGIC CELLS
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/10/1998
|
Application #:
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08661888
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Filing Dt:
|
06/11/1996
|
|
Title:
|
SIMULATION BASED EXTRACTOR OF EXPECTED WAVEFORMS FOR GATE-LEVEL POWER ANAYSIS TOOL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
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08661889
|
Filing Dt:
|
06/11/1996
|
|
Title:
|
PARAMETRIZED WAVEFORM PROCESSOR FOR GATE-LEVEL POWER ANALYSIS TOOL
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/30/1997
|
Application #:
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08663336
|
Filing Dt:
|
06/13/1996
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A LAYER OF GALLIUM AMALGAM ON BUMP LEADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08664020
|
Filing Dt:
|
06/12/1996
|
|
Title:
|
GENERIC INTERACTIVE DEVICE MODEL WRAPPER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/1998
|
Application #:
|
08664146
|
Filing Dt:
|
06/14/1996
|
|
Title:
|
METHOD OF ASSEMBLING BALL BUMP GRID ARRAY SEMICONDUCTOR PACKAGES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08664227
|
Filing Dt:
|
06/07/1996
|
|
Title:
|
METHOD FOR PRODUCING TAPERED LINES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/1997
|
Application #:
|
08665016
|
Filing Dt:
|
06/11/1996
|
|
Title:
|
METHOD OF MAKING AN INTEGRATED CIRCUIT CHIP HAVING AN ARRY OF LOGIC GATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08668064
|
Filing Dt:
|
06/19/1996
|
|
Title:
|
GATE NETLIST TO REGISTER TRANSFER LEVEL CONVERSION TOOL
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|
