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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 7 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
Issue Dt:
06/20/2000
Application #:
08853155
Filing Dt:
05/08/1997
Title:
COMPARING AERIAL IMAGE TO SEM OF PHOTORESIST OR SUBSTRATE PATTERN FOR MASKING PROCESS CHARACTERIZATION
2
Patent #:
Issue Dt:
06/29/1999
Application #:
08853210
Filing Dt:
05/09/1997
Title:
PROCESS FOR FORMING GATE OXIDES POSSESSING DIFFERENT THICKNESSES ON A SEMICONDUCTOR SUBSTRATE
3
Patent #:
Issue Dt:
10/12/1999
Application #:
08853578
Filing Dt:
05/09/1997
Title:
APPARATUS FOR DEFINING PROPERTIES IN FINITE-STATE MACHINES
4
Patent #:
Issue Dt:
06/16/1998
Application #:
08853582
Filing Dt:
05/09/1997
Title:
INTEGRATED CIRCUIT DEVICE WITH ISOLATED CIRCUIT ELEMENTS
5
Patent #:
Issue Dt:
09/12/2000
Application #:
08853736
Filing Dt:
05/13/1997
Title:
REDUCTION OF FLOW-INDUCED MICROPHONE NOISE
6
Patent #:
Issue Dt:
02/09/1999
Application #:
08854780
Filing Dt:
05/12/1997
Title:
POWDERED METAL HEAT SINK WITH INCREASED SURFACE AREA
7
Patent #:
Issue Dt:
11/13/2001
Application #:
08856561
Filing Dt:
05/15/1997
Title:
METHOD AND APPARATUS FOR IMAGING SEMICONDUCTOR DEVICES
8
Patent #:
Issue Dt:
08/25/1998
Application #:
08857079
Filing Dt:
05/15/1997
Title:
METHOD FOR FORMING CONDUCTORS IN INTEGRATED CIRCUITS
9
Patent #:
Issue Dt:
05/30/2000
Application #:
08859751
Filing Dt:
05/21/1997
Title:
FIXTURE FOR LID-ATTACHMENT FOR ENCAPSULATED PACKAGES
10
Patent #:
Issue Dt:
11/10/1998
Application #:
08861884
Filing Dt:
05/22/1997
Title:
PRESERVING CLEARANCE BETWEEN ENCAPSULANT AND PCB FOR CAVITY-DOWN SINGLE-TIER PACKAGE ASSEMBLY
11
Patent #:
Issue Dt:
03/24/1998
Application #:
08862226
Filing Dt:
05/23/1997
Title:
PROCESS FOR CONTROLLING DOPANT DIFFUSION IN A SEMICONDUCTOR LAYER AND SEMICONDUCTOR LAYER FORMED THEREBY
12
Patent #:
Issue Dt:
11/30/1999
Application #:
08862233
Filing Dt:
05/23/1997
Title:
METHOD FOR GENERATING FORMAT-INDEPENDENT ELECTRONIC CIRCUIT REPRESENTATIONS
13
Patent #:
Issue Dt:
05/11/1999
Application #:
08862791
Filing Dt:
05/23/1997
Title:
METHOD OF CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP COMPRISING CHAOTIC PLACEMENT AND MOVING WINDOWS
14
Patent #:
Issue Dt:
11/02/1999
Application #:
08862907
Filing Dt:
05/23/1997
Title:
CAPACITOR COMPRISING IMPROVED TAOX-BASED DIELECTRIC
15
Patent #:
Issue Dt:
11/02/1999
Application #:
08863372
Filing Dt:
05/27/1997
Title:
LIGHT SENSING DEVICE HAVING AN ARRAY OF PHOTOSENSITIVE ELEMENTS COINCIDENT WITH AN ARRAY OF LENS FORMED ON AN OPTICALLY-TRANSMISSIVE MATERIAL
16
Patent #:
Issue Dt:
10/20/1998
Application #:
08863713
Filing Dt:
05/27/1997
Title:
AN ELECTRONIC COMPONENT FOR AN INTEGRATED CIRCUIT
17
Patent #:
Issue Dt:
10/13/1998
Application #:
08863798
Filing Dt:
05/27/1997
Title:
METHOD FOR USING BUILT IN SELF TEST TO CHARACTERIZE INPUT-TO-OUTPUT DELAY TIME OF EMBEDDED CORES AND OTHER INTERGRATED CIRCUITS
18
Patent #:
Issue Dt:
06/01/1999
Application #:
08864220
Filing Dt:
05/28/1997
Title:
SEMICONDUCTOR DEVICE FABRICATION
19
Patent #:
Issue Dt:
05/25/1999
Application #:
08864994
Filing Dt:
05/29/1997
Title:
CONFORMAL DIAMOND COATING FOR THERMAL IMPROVEMENT OF ELECTRONIC PACKAGES
20
Patent #:
Issue Dt:
12/22/1998
Application #:
08865548
Filing Dt:
05/29/1997
Title:
PROCESS FOR FABRICATING A DEVICE USING NITROGEN IMPLANTATION INTO SILICIDE LAYER
21
Patent #:
Issue Dt:
11/09/1999
Application #:
08866755
Filing Dt:
05/30/1997
Title:
LOW POWER CIRCUITS THROUGH HAZARD PULSE SUPPRESSION
22
Patent #:
Issue Dt:
04/25/2000
Application #:
08866937
Filing Dt:
05/31/1997
Title:
SIMULATION MODEL USING OBJECT-ORIENTED PROGRAMMING
23
Patent #:
Issue Dt:
04/06/1999
Application #:
08867286
Filing Dt:
06/02/1997
Title:
INTEGRATED CIRCUIT WITH ON-CHIP GROUND BASE
24
Patent #:
Issue Dt:
03/20/2001
Application #:
08867351
Filing Dt:
06/02/1997
Title:
OPTIMIZED BUILT-IN SELF-TEST METHOD AND APPARATUS FOR RANDOM ACCESS MEMORIES
25
Patent #:
Issue Dt:
12/01/1998
Application #:
08868269
Filing Dt:
06/03/1997
Title:
INALGAP DEVICES
26
Patent #:
Issue Dt:
06/01/1999
Application #:
08868316
Filing Dt:
06/03/1997
Title:
HIGH PERFORMANCE HEAT SPREADER FOR FLIP CHIP PACKAGES
27
Patent #:
Issue Dt:
08/22/2000
Application #:
08869278
Filing Dt:
06/04/1997
Title:
AN AUTOMATED INSPECTION SYSTEM FOR RESIDUAL METAL AFTER CHEMICAL-MECHANICAL POLISHING
28
Patent #:
Issue Dt:
05/01/2001
Application #:
08869796
Filing Dt:
06/05/1997
Title:
GROOVED SEMICONDUCTOR DIE FOR FLIP-CHIP HEAT SINK ATTACHMENT
29
Patent #:
Issue Dt:
01/05/1999
Application #:
08869944
Filing Dt:
06/05/1997
Title:
ARTICLE COMPRISING MAGNETORESISTIVE MATERIAL
30
Patent #:
Issue Dt:
05/18/1999
Application #:
08871212
Filing Dt:
06/09/1997
Title:
SEPARABLE CELLS HAVING WIRING CHANNELS FOR ROUTING SIGNALS BETWEEN SURROUNDING CELLS
31
Patent #:
Issue Dt:
08/31/1999
Application #:
08871383
Filing Dt:
06/09/1997
Title:
INTEGRATED CIRCUIT FABRICATION
32
Patent #:
Issue Dt:
12/14/1999
Application #:
08871385
Filing Dt:
06/09/1997
Title:
BIPOLAR HAVING GRADED OR MODULATED COLLECTOR PROCESS FOR MAKING
33
Patent #:
Issue Dt:
09/12/2000
Application #:
08872250
Filing Dt:
06/10/1997
Title:
MICROMAGNETIC DEVICE FOR POWER PROCESING APPLICATIONS AND METHOD OF MANUFACTURE THEREFOR
34
Patent #:
Issue Dt:
04/20/1999
Application #:
08873809
Filing Dt:
06/12/1997
Title:
PROCESS FOR MAKING INTEGRATED CIRCUIT STRUCTURE COMPRISING LOCAL AREA INTERCONNECTS FORMED OVER SEMICONDUCTOR SUBSTRATE BY SELECTIVE DEPOSITION ON SEED LAYER IN PATTERNED TRENCH
35
Patent #:
Issue Dt:
11/16/1999
Application #:
08874055
Filing Dt:
06/12/1997
Title:
AUTOMATED ENDPOINT DETECTION SYSTEM DURING CHEMICAL-MECHANICAL POLISHING
36
Patent #:
Issue Dt:
10/26/1999
Application #:
08877117
Filing Dt:
06/17/1997
Title:
"TEST BENCH INTERFACE GENERATOR FOR TESTER COMPATIBLE SIMULATIONS"
37
Patent #:
Issue Dt:
07/18/2000
Application #:
08878242
Filing Dt:
06/18/1997
Title:
LOCOS ISOLATION PROCESS USING A LAYERED PAD NITRIDE AND DRY FIELD OXIDATION STACK AND SEMICONDUCTOR DEVICE EMPLOYING THE SAME
38
Patent #:
Issue Dt:
12/28/1999
Application #:
08878579
Filing Dt:
06/19/1997
Title:
DEPOSITION OF HIGHLY DOPED SILICON DIOXIDE FILMS
39
Patent #:
Issue Dt:
09/19/2000
Application #:
08879100
Filing Dt:
06/19/1997
Title:
POLYMERIC DIELECTRIC LAYERS HAVING LOW DIELECTRIC CONSTANTS AND IMPROVED ADHESION TO METAL LINES
40
Patent #:
Issue Dt:
06/27/2000
Application #:
08879341
Filing Dt:
06/20/1997
Title:
COMPOSITE TRENCH-FIN CAPACITORS FOR DRAMS
41
Patent #:
Issue Dt:
08/03/1999
Application #:
08879659
Filing Dt:
06/23/1997
Title:
ETCH PROCESS SELECTIVE TO COBALT SILICIDE FOR FORMATION OF INTEGRATED CIRCUIT STRUCTURES
42
Patent #:
Issue Dt:
10/31/2000
Application #:
08879926
Filing Dt:
06/20/1997
Title:
MOS IMAGE SENSOR
43
Patent #:
Issue Dt:
09/22/1998
Application #:
08881293
Filing Dt:
06/24/1997
Title:
OPTICAL PROBE MICROSCOPE HAVING A FIBER OPTIC TIP THAT RECEIVES BOTH A DITHER MOTION AND A SCANNING MOTION, FOR NONDESTRUCTIVE METROLOGY OF LARGE SAMPLE SURFACES
44
Patent #:
Issue Dt:
12/29/1998
Application #:
08883403
Filing Dt:
06/26/1997
Title:
LOW POWER PROGRAMMABLE FUSE STRUCTURES SAME
45
Patent #:
Issue Dt:
06/30/1998
Application #:
08884095
Filing Dt:
06/27/1997
Title:
MOLDED ENCAPSULATED ELECTRONIC COMPONENT
46
Patent #:
Issue Dt:
09/22/1998
Application #:
08887587
Filing Dt:
07/03/1997
Title:
LOW NOISE, HIGH POWER PSEUDOMORPHIC HEMT
47
Patent #:
Issue Dt:
01/04/2000
Application #:
08887861
Filing Dt:
07/03/1997
Title:
SYSTEM AND METHOD FOR DETERMINING NEAR- SURFACE LIFETIMES AND THE TUNNELING FIELD OF A DIELECTRIC IN A SEMICONDUCTOR
48
Patent #:
Issue Dt:
05/11/1999
Application #:
08887910
Filing Dt:
07/02/1997
Title:
PROCESS FOR FORMING PHOTORESIST MASK OVER INTEGRATED CIRCUIT STRUCTURES WITH CRITICAL DIMENSION CONTROL
49
Patent #:
Issue Dt:
04/20/1999
Application #:
08889839
Filing Dt:
07/09/1997
Title:
METHOD TO OBTAIN A LOW RESISTIVITY AND CONFORMITY CHEMICAL VAPOR DEPOSITION TITANIUM FILM
50
Patent #:
Issue Dt:
06/08/1999
Application #:
08890174
Filing Dt:
07/09/1997
Title:
SPECIFICATION AND DESIGN OF COMPLEX DIGITAL SYSTEMS
51
Patent #:
Issue Dt:
02/23/1999
Application #:
08890222
Filing Dt:
07/09/1997
Title:
PROCESS FOR FORMING MOS DEVICE IN INTEGRATED CIRCUIT STRUCTURE USING COBALT SILICIDE CONTACTS AS IMPLANTATION MEDIA
52
Patent #:
Issue Dt:
06/30/1998
Application #:
08892827
Filing Dt:
07/15/1997
Title:
METHOD OF FABRICATING A LINEARLY CONTINUOUS INTEGRATED CIRCUIT GATE ARRAY
53
Patent #:
Issue Dt:
10/06/1998
Application #:
08895659
Filing Dt:
07/17/1997
Title:
APPARATUS FOR POLISHING A SUBSTRATE AT RADIALLY VARYING POLISH RATES
54
Patent #:
Issue Dt:
12/21/1999
Application #:
08895960
Filing Dt:
07/17/1997
Title:
DUAL PURPOSE RETAINING RING AND POLISHING PAD CONDITIONER
55
Patent #:
Issue Dt:
03/02/1999
Application #:
08898261
Filing Dt:
07/22/1997
Title:
PLASMA ETCH END POINT DETECTION PROCESS
56
Patent #:
Issue Dt:
05/30/2000
Application #:
08899111
Filing Dt:
07/23/1997
Title:
SLURRY FILLING A RECESS FORMED DURING SEMICONDUCTOR FABRICATION
57
Patent #:
Issue Dt:
02/17/2004
Application #:
08899464
Filing Dt:
07/23/1997
Title:
THROUGH-PAD DRAINAGE OF SLURRY DURING CHEMICAL MECHANICAL POLISHING
58
Patent #:
Issue Dt:
11/23/1999
Application #:
08899629
Filing Dt:
07/24/1997
Title:
SYSTEM AND METHOD FOR PREVENTING SMOKE AND FIRE DAMAGE TO PEOPLE AND EQUIPMENT IN A CLEAN ROOM AREA FROM A FIRE
59
Patent #:
Issue Dt:
12/07/1999
Application #:
08900845
Filing Dt:
07/25/1997
Title:
METHODS AND APPARATUS FOR ELECTRICAL MARKING OF INTEGRATED CIRCUITS TO RECORD MANUFACTURING TEST RESULTS
60
Patent #:
Issue Dt:
08/22/2000
Application #:
08901250
Filing Dt:
07/28/1997
Title:
APPARATUS AND METHOD FOR HYBRID PIN CONTROL OF BOUNDARY SCAN APPLICATIONS
61
Patent #:
Issue Dt:
03/23/1999
Application #:
08901489
Filing Dt:
07/28/1997
Title:
BALL GRID ARRAY WITH INEXPENSIVE THREADED SECURE LOCKING MECHANISM TO ALLOW REMOVAL OF A THREADED HEAT SINK THEREFROM
62
Patent #:
Issue Dt:
06/18/2002
Application #:
08902044
Filing Dt:
07/29/1997
Publication #:
Pub Dt:
12/27/2001
Title:
PROCESS FOR DEVICE FABRICATION
63
Patent #:
Issue Dt:
05/16/2000
Application #:
08902343
Filing Dt:
07/29/1997
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT FAILURE ANALYSIS USING MAGNETIC IMAGING
64
Patent #:
Issue Dt:
12/01/1998
Application #:
08902997
Filing Dt:
07/30/1997
Title:
METHOD AND APPARATUS FOR CALIBRATING STATIC TIMING ANALYZER TO PATH DELAY MEASUREMENTS
65
Patent #:
Issue Dt:
12/28/1999
Application #:
08903241
Filing Dt:
07/24/1997
Title:
ELECTRONIC SYSTEM INCLUDING PACKAGED INTEGRATED CIRCUITS WITH HEAT SPREADING STANDOFF SUPPORT MEMBERS
66
Patent #:
Issue Dt:
05/20/2003
Application #:
08903974
Filing Dt:
07/31/1997
Title:
PROCESS FOR DEVICE FABRICATION
67
Patent #:
Issue Dt:
03/21/2000
Application #:
08904233
Filing Dt:
07/31/1997
Title:
APPARATUS AND METHOD FOR ANALYZING PASSIVE CIRCUITS USING REDUCED ORDER MODELING OF LARGE LINEAR SUBCIRCUITS
68
Patent #:
Issue Dt:
05/16/2000
Application #:
08904488
Filing Dt:
08/01/1997
Title:
METHOD AND APPARATUS FOR DESIGNING INTERCONNECTIONS AND PASSIVE COMPONENTS IN INTEGRATED CIRCUITS AND EQUIVALENT STRUCTURES BY EFFICIENT PARAMETER EXTRACTION
69
Patent #:
Issue Dt:
07/27/1999
Application #:
08904527
Filing Dt:
08/01/1997
Title:
METHOD OF ETCHING SILICON MATERIALS
70
Patent #:
Issue Dt:
06/08/1999
Application #:
08904530
Filing Dt:
08/01/1997
Title:
METHOD AND APPARATUS FOR FORMING ELECTRICAL CONNECTIONS BETWEEN A SEMICONDUCTOR DIE AND A SEMICONDUCTOR PACKAGE
71
Patent #:
Issue Dt:
02/08/2000
Application #:
08905540
Filing Dt:
08/04/1997
Title:
FAST TRANSIENT CIRCUIT SIMULATION OF ELECTRONIC CIRCUITS INCLUDING A CRYSTAL
72
Patent #:
Issue Dt:
05/30/2000
Application #:
08906945
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR CONGESTION REMOVAL
73
Patent #:
Issue Dt:
06/13/2000
Application #:
08906946
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR CONTINUOUS COLUMN DENSITY OPTIMIZATION
74
Patent #:
Issue Dt:
02/13/2001
Application #:
08906947
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR DETERMINING WIRE ROUTING
75
Patent #:
Issue Dt:
05/02/2000
Application #:
08906948
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR VERTICAL CONGESTION REMOVAL
76
Patent #:
Issue Dt:
09/26/2000
Application #:
08906949
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR HORIZONTAL CONGESTION REMOVAL
77
Patent #:
Issue Dt:
05/30/2000
Application #:
08906950
Filing Dt:
08/06/1997
Title:
METHOD AND APPARATUS FOR CONGESTION DRIVEN PLACEMENT
78
Patent #:
Issue Dt:
01/30/2001
Application #:
08907183
Filing Dt:
08/06/1997
Title:
METHOD AND DEVICE FOR FAST AND ACCURATE PARASITIC EXTRACTION
79
Patent #:
Issue Dt:
10/17/2000
Application #:
08907834
Filing Dt:
08/14/1997
Title:
SEMICONDUCTOR DEVICE HAVING AN ANTI-REFLECTIVE LAYER AND A METHOD OF MANUFACTURE THEREOF
80
Patent #:
Issue Dt:
11/23/1999
Application #:
08908404
Filing Dt:
08/07/1997
Title:
REFRAMED CHIP-ON-TAPE DIE
81
Patent #:
Issue Dt:
03/23/1999
Application #:
08909312
Filing Dt:
08/11/1997
Title:
METHOD FOR DISTRIBUTING CONNECTION PADS ON A SEMICONDUCTOR DIE
82
Patent #:
Issue Dt:
03/21/2000
Application #:
08909563
Filing Dt:
08/12/1997
Title:
A DEVICE AND METHOD OF FORMING A METAL TO METAL CAPACITOR WITHIN AN INTEGRATED CIRCUIT
83
Patent #:
Issue Dt:
07/04/2000
Application #:
08911418
Filing Dt:
08/14/1997
Title:
SYSTEM AND METHOD FOR PACKAGING AN INTEGRATED CIRCUIT USING ENCAPSULANT INJECTION
84
Patent #:
Issue Dt:
10/12/1999
Application #:
08911489
Filing Dt:
08/14/1997
Title:
NYBRID INORGANIC-ORGANIC COMPOSITE FOR USE AS AN INTERLAYER DIELECTRIC
85
Patent #:
Issue Dt:
10/03/2000
Application #:
08911515
Filing Dt:
08/14/1997
Title:
INTEGRATED CIRCUIT PACKAGING APPARATUS AND METHOD
86
Patent #:
Issue Dt:
07/25/2000
Application #:
08912597
Filing Dt:
08/18/1997
Title:
CHEMICAL- MECHANICAL POLISHING PAD CONDITIONING SYSTEMS
87
Patent #:
Issue Dt:
05/04/1999
Application #:
08912887
Filing Dt:
08/15/1997
Title:
PERFORMING OPTICAL PROXIMITY CORRECTION WITH THE AID OF DESIGN RULE CHECKERS
88
Patent #:
Issue Dt:
07/04/2000
Application #:
08914493
Filing Dt:
08/19/1997
Title:
DIGITAL INTEGRATED CIRCUIT DESIGN SYSTEM AND METHODOLOGY WITH HARDWARE
89
Patent #:
Issue Dt:
03/16/1999
Application #:
08914854
Filing Dt:
08/19/1997
Title:
CHEMICAL MECHANICAL POLISHING PAD SLURRY DISTRIBUTION GROOVES
90
Patent #:
Issue Dt:
02/02/1999
Application #:
08915000
Filing Dt:
08/20/1997
Title:
APPARATUS AND METHOD FOR POLISH REMOVING A PRECISE AMOUNT OF MATERIAL FROM A WAFER
91
Patent #:
Issue Dt:
02/16/1999
Application #:
08916025
Filing Dt:
08/21/1997
Title:
PROCESS OF FABRICATING AN INTERGRATED CIRCIUIT DIE PACKAGE HAVING A PLURALITY OF PINS
92
Patent #:
Issue Dt:
07/27/1999
Application #:
08917955
Filing Dt:
08/27/1997
Title:
STRESS MIGRATION EVALUATION METHOD
93
Patent #:
Issue Dt:
06/13/2000
Application #:
08918174
Filing Dt:
08/25/1997
Title:
THIN FILM CAPACITORS AND PROCESS FOR MAKING THEM
94
Patent #:
Issue Dt:
01/02/2001
Application #:
08918293
Filing Dt:
08/25/1997
Title:
POLISHING PAD SURFACE FOR IMPROVED PROCESS CONTROL
95
Patent #:
Issue Dt:
05/30/2000
Application #:
08918360
Filing Dt:
08/26/1997
Title:
USE OF CORROSION INHIBITING COMPOUNDS TO INHIBIT CORROSION OF METAL PLUGS IN CHEMICAL-MECHANICAL POLISHING
96
Patent #:
Issue Dt:
12/08/1998
Application #:
08918394
Filing Dt:
08/26/1997
Title:
INTEGRATED CIRCUIT FABRICATION
97
Patent #:
Issue Dt:
11/23/1999
Application #:
08918451
Filing Dt:
08/26/1997
Title:
METHOD FOR COMPENSAATING FOR BOTTOM WARPAGE OF A BGA INTEGRATED CIRCUIT
98
Patent #:
Issue Dt:
04/13/1999
Application #:
08918483
Filing Dt:
08/26/1997
Title:
USE OF ETHYLENE GLYCOL AS A CORROSION INHIBITOR DURING CLEANING AFTER METAL CHEMICAL MECHANICAL POLISHING
99
Patent #:
Issue Dt:
07/25/2000
Application #:
08918577
Filing Dt:
08/19/1997
Title:
INTEGRATED CIRCUIT WITH ISOLATION OF FIELD OXIDATION BY NOBLE GAS IMPLANTATION
100
Patent #:
Issue Dt:
09/28/1999
Application #:
08918781
Filing Dt:
08/25/1997
Title:
LITHOGRAPHIC PROCESS AND ENERGY-SENSITIVE MATERIAL FOR USE THEREIN
Assignors
1
Exec Dt:
01/24/2018
2
Exec Dt:
01/24/2018
3
Exec Dt:
01/24/2018
Assignee
1
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
WASHINGTON, DC 20006

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