|
|
|
|
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Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08918846
|
Filing Dt:
|
08/25/1997
|
|
Title:
|
METHOD AND APPARATUS FOR USING PRESSURE DIFFERENTIALS THROUGH A POLISHING PAD TO IMPROVE PERFORMANCE IN CHEMICAL MECHANICAL POLISHING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/1999
|
Application #:
|
08919192
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
MAUFACTURING METHOD INCLUDING NEAR-FIELD OPTICAL MICROSCOPIC EXAMINATION OF A SEMICONDUCTOR SUBSTRATE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08919394
|
Filing Dt:
|
08/28/1997
|
|
Title:
|
PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH IMPROVED METAL SILICIDE CONTACTS USING NOTCHED SIDEWALL SPACER ON GATE ELECTRODE, AND RESULTING STRUCTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08920430
|
Filing Dt:
|
08/29/1997
|
|
Title:
|
IMPROVED OVER MOLED PACKAGE BODY ON A SUBSTRATE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08921758
|
Filing Dt:
|
08/25/1997
|
|
Title:
|
SHAPING POLISHING PAD TO CONTROL MATERIAL REMOVAL RATE SELECTIVELY
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|
|
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|
Patent #:
|
|
Issue Dt:
|
07/28/1998
|
Application #:
|
08922141
|
Filing Dt:
|
08/29/1997
|
|
Title:
|
AN INTEGRATED CIRCUIT COMPRISING SOLDER BUMPS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08922487
|
Filing Dt:
|
09/03/1997
|
|
Title:
|
INTEGRATED CIRCUIT PROCESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
08923316
|
Filing Dt:
|
09/04/1997
|
|
Title:
|
METHOD OF MECHANICAL POLISHING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08923676
|
Filing Dt:
|
09/04/1997
|
|
Title:
|
STANDARDIZED GAS ISOLATION BOX (GIB) INSTALLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
08924277
|
Filing Dt:
|
09/05/1997
|
|
Title:
|
IMPROVED METHOD FOR ESTIMATING QUIESCENT CURRENT IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08924493
|
Filing Dt:
|
08/27/1997
|
|
Title:
|
USE OF HYDROFLUORIC ACID FOR EFFECITVE PAD CONDITIONING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
08924728
|
Filing Dt:
|
09/05/1997
|
|
Title:
|
METHOD OF INTEGRATED CIRCUIT FABRICATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08924730
|
Filing Dt:
|
09/05/1997
|
|
Title:
|
INTEGRATED CIRCUIT FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08924902
|
Filing Dt:
|
09/08/1997
|
|
Title:
|
CONSISTENT ALIGNMENT MARK PROFILES ON SEMICONDUCTOR WAFERS USING PVD SHADOWING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08924903
|
Filing Dt:
|
09/08/1997
|
|
Title:
|
CONSISTENT ALIGNMENT MARK PROFILES ON SEMICONDUCTOR WAFERS USING FINE GRAIN TUNGSTEN PROTECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08925200
|
Filing Dt:
|
09/08/1997
|
|
Title:
|
CONSISTENT ALIGNMENT MARK PROFILES ON SEMICONDUCTOR WAFERS USING METAL ORGANIC CHEMICAL VAPOR DEPOSITION TITANIUM NITRIDE PROTECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08926220
|
Filing Dt:
|
09/09/1997
|
|
Title:
|
METHOD AND APPARATUS FOR FORMING DIELECTRIC FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
08926590
|
Filing Dt:
|
09/04/1997
|
|
Title:
|
EFFECTIVE SILICIDE BLOCKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08927704
|
Filing Dt:
|
09/10/1997
|
|
Title:
|
MOLDED ARRAY INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
08928826
|
Filing Dt:
|
09/12/1997
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08931066
|
Filing Dt:
|
09/15/1997
|
|
Title:
|
LINEWIDTH METROLOGY OF INTEGRATED CIRCUIT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08932005
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
METAL TO METAL CAPACITOR APPARATUS AND METHOD FOR MAKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08932614
|
Filing Dt:
|
09/17/1997
|
|
Title:
|
METAL-FILLED VIA/CONTACT OPENING WITH THIN BARRIER LAYERS IN INTEGRATED CIRCUIT STRUCTURE FOR FAST RESPONSE, AND PROCESS FOR MAKING SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08933733
|
Filing Dt:
|
09/23/1997
|
|
Title:
|
METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING NOISE MODELING AND PREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08934529
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
TAPE BALL GRID ARRAY PACKAGE WITH PERFORATED METAL STIFFENER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08935121
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
METHOD OF FORMING A T-SHAPED GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08935424
|
Filing Dt:
|
09/23/1997
|
|
Title:
|
INTEGRATED HEAT SPREADER/STIFFENER WITH APERTURES FOR SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08935521
|
Filing Dt:
|
09/23/1997
|
|
Title:
|
THIN OXIDE MASK LEVEL DEFINED RESISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
08935583
|
Filing Dt:
|
09/23/1997
|
|
Title:
|
DIE CLIP AND METHOD OF ASSEMBLY FOR SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08935584
|
Filing Dt:
|
09/23/1997
|
|
Title:
|
CONTROLLING GROOVE DIMENSIONS FOR ENHANCED SLURRY FLOW
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08935834
|
Filing Dt:
|
09/23/1997
|
|
Title:
|
INTEGRATED HEAT SPREADER/STIFFENER ASSEMBLY AND METHOD OF ASSEMBLY FOR SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08936132
|
Filing Dt:
|
09/24/1997
|
|
Title:
|
DIELECTRIC MATERIALS OF AMORPHOUS COMPOSITIONS AND DEVICES EMPLOYING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08936829
|
Filing Dt:
|
09/25/1997
|
|
Title:
|
A METHOD OF FABRICATING A MICROELECTRONIC PACKAGE HAVING POLYMER ESD PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
08937296
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
SYSTEM AND METHOD FOR PERFORMING OPTICAL PROXIMITY CORRECTION ON THE INTERFACE BETWEEN OPTICAL PROXIMITY CORRECTED CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
08938099
|
Filing Dt:
|
09/26/1997
|
|
Title:
|
MODIFYING CONTACT AREAS OF A POLISHING PAD TO PROMOTE UNIFORM REMOVAL RATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08938100
|
Filing Dt:
|
09/26/1997
|
|
Title:
|
STIFFENER RING AND HEAT SPREADER FOR USE WITH FLIP CHIP PACKAGING ASSEMBLIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08938619
|
Filing Dt:
|
09/25/1997
|
|
Title:
|
SYSTEM AND METHOD FOR EMPIRICALLY DETERMINING SHRINKAGE STRESSES IN A MOLDED PACKAGE AND POWER MODULE EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
|
Application #:
|
08939350
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
PROCESS FOR MAKING GROUP IV SEMICONDUCTOR SUBSTRATE TREATED WITH ONE OR MORE GROUP IV ELEMENTS TO FORM BARRIER REGION CAPABLE OF INHIBITING MIGRATION OF DOPANT MATERIALS IN SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
08939422
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
INTEGRATED CIRCUIT FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1998
|
Application #:
|
08939498
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
METHOD FOR INSERTING TEST POINTS FOR FULL-AND-PARTIAL-SCAN BUILT-IN SELF-TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08939689
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
METHOD AND APPARATUS FOR CHEMICAL MECHANICAL POLISHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08940156
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
ALIGNMENT MARK CONTRAST ENHANCEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08940912
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
METHOD AND APPARATUS FOR ANALYZING DIGITAL CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08941556
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
SILICON IC CONTACTS USING COMPOSITE TIN BARRIER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
08942006
|
Filing Dt:
|
10/01/1997
|
|
Title:
|
METHOD AND APPARATUS FOR CONCURRENT PAD CONDITIONING AND WAFER BUFF IN CHEMICAL MECHANICAL POLISHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08942991
|
Filing Dt:
|
10/02/1997
|
|
Title:
|
USE OF ABRASIVE TAPE CONVEYING ASSEMBLIES FOR CONDITIONING POLISHING PADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08943371
|
Filing Dt:
|
10/03/1997
|
|
Title:
|
ON-CHIP MISALIGNMENT INDICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08943585
|
Filing Dt:
|
10/03/1997
|
|
Title:
|
PROCESS FOR DEVICE FABRICATION IN WHICH A LAYER OF OXYNITRIDE IS FORMED AT LOW TEMPERATURES
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
04/25/2000
|
Application #:
|
08944247
|
Filing Dt:
|
10/06/1997
|
|
Title:
|
METHOD AND APPARATUS FOR AGITATING AN ETCHANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08946413
|
Filing Dt:
|
10/07/1997
|
|
Title:
|
METHOD OF USING GETTER LAYER TO IMPROVE METAL TO METAL CONTACT RESISTANCE AT LOW RADIO FREQUENCY POWER
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
01/27/2004
|
Application #:
|
08946693
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
IMPROVED AIR ISOLATED CROSSOVERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08946980
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
CHIP-ON-CHIP IC PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08947136
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
METHOD FOR BUILT-IN SELF-TESTING OF RING-ADDRESS FIFOS HAVING A DATA INPUT REGISTER WITH TRANSPARENT LATCHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
08947271
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
DOMINO SCAN ARCHITECTURE AND DOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08947742
|
Filing Dt:
|
10/09/1997
|
|
Title:
|
PROCESS FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS FOR MOS STRUCTURE USING SINGLE SILICIDE-FORMING STEP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08948874
|
Filing Dt:
|
10/10/1997
|
|
Title:
|
ARTICLE COMPRISING AN OXIDE LAYER ON GAN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08951779
|
Filing Dt:
|
10/16/1997
|
|
Title:
|
THIN FILM TRANSISTOR AND ORGANIC SEMICONDUCTOR METERIAL THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08954006
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
METHOD FOR IMPROVED GATE OXIDE INTEGRITY ON BULK SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/1999
|
Application #:
|
08954791
|
Filing Dt:
|
10/21/1997
|
|
Title:
|
APPARATUS FOR RAPID THERMAL PROCESSING OF A WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08955384
|
Filing Dt:
|
10/21/1997
|
|
Title:
|
METHOD OF FORMING A LAYER AND SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08955929
|
Filing Dt:
|
10/22/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE AND FABRICATION METHOD WHICH ADVANTAGEOUSLY COMBINE WIRE BONDING AND TAB TECHNIQUES TO INCREASE INTEGRATED CIRCUIT I/O PAD DENSITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08956527
|
Filing Dt:
|
10/23/1997
|
|
Title:
|
SOLDER BONDING OF ELECTRICAL COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
08956874
|
Filing Dt:
|
10/23/1997
|
|
Title:
|
SYSTEM AND METHOD FOR REPRESENTING A SYSTEM LEVEL RTL DESIGN USING HDL INDEPENDENT OBJECTS AND TRANSLATION TO SYNTHESIZABLE RTL CODE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
04/29/2003
|
Application #:
|
08957122
|
Filing Dt:
|
10/24/1997
|
|
Title:
|
SCANNING ELECTRON MICROSCOPE SYSTEM AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
08957692
|
Filing Dt:
|
10/24/1997
|
|
Title:
|
NITROGEN IMPLANTED POLYSILICON GATE FOR MOSFET GATE OXIDE HARDENING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
08958775
|
Filing Dt:
|
10/27/1997
|
|
Title:
|
BUILT IN SELF REPAIR FOR DRAMS USING ON-CHIP TEMPERATURE SENSING AND HEATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08958776
|
Filing Dt:
|
10/27/1997
|
|
Title:
|
VACUUM ASSISTED UNDERFILL PROCESS AND APPARATUS FOR SEMICONDUCTOR PACKAGE FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
08960831
|
Filing Dt:
|
10/30/1997
|
|
Title:
|
METHOD FOR PLANARIZING AN ARRAY OF SOLDER BALLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
08960925
|
Filing Dt:
|
10/30/1997
|
|
Title:
|
SHIMMING SUBSTRATE HOLDER ASSEMBLIES TO PRODUCE MORE UNIFORMLY POLISHED SUBSTRATE SURFACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08960969
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Filing Dt:
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10/30/1997
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Title:
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CONDITIONING CMP POLISHING PAD USING A HIGH PRESSURE FLUID
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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08961163
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Filing Dt:
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10/30/1997
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Title:
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AUTOMATIC RANGING APPARATUS AND METHOD FOR PRECISE INTEGRATED CIRCUIT CURRENT MEASUREMENTS
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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08961382
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Filing Dt:
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10/30/1997
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Title:
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MODIFIED CARRIER FILMS TO PRODUCE MORE UNIFORMLY POLISHED SUBSTRATE SURFACES
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08961383
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Filing Dt:
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10/30/1997
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Title:
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EFFECTIVE PAD CONDITIONING
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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08962340
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Filing Dt:
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10/31/1997
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Title:
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MAINTENANCE REGISTERS WITH BOUNDARY SCAN INTERFACE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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08963553
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Filing Dt:
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11/03/1997
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Title:
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SEMICONDUCTOR DIE METAL LAYOUT FOR FLIP CHIP PACKAGING
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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08963687
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Filing Dt:
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11/04/1997
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Title:
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METHOD FOR USING A HARDMASK TO FORM AN OPENING IN A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08963813
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Filing Dt:
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11/04/1997
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Title:
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"SEMICONDUCTOR DEVICE AND FABRICATION METHOD EMPLOYING A PALLADIUM -PLATED HEAT SPREADER SUBSTRATE"
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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08964784
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Filing Dt:
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11/05/1997
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Title:
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PARALLEL PROCESSING OF INTEGRATED CIRCUIT PIN ARRIVAL TIMES
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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08964997
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Filing Dt:
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11/05/1997
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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MODIFYING TIMING GRAPH TO AVOID GIVEN SET OF PATHS
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08965706
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Filing Dt:
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11/07/1997
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Title:
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METHOD OF CREATING AN INTERCONNECT IN A SUBSTRATE AND SEMICONDUCTOR DEVICE EMPLOYING THE SAME
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08966637
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Filing Dt:
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11/10/1997
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Title:
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PLASMA-ENHANCED OXIDE PROCESS OPTIMIZATION AND MATERIAL AND APPARATUS THEREFOR
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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08970298
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Filing Dt:
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11/14/1997
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Title:
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METHOD OF ROUGHING A METALLIC SURFACE OF A SEMICONDUCTOR DEPOSITION TOOL
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08971422
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Filing Dt:
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11/17/1997
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Title:
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LOW TEMPERATURE COEFFICIENT DIELECTRIC MATERIAL COMPRISING BINARY CALCIUM NIOBATE AND CALCIUM TANTALATE OXIDES
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08971769
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Filing Dt:
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11/17/1997
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Title:
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METHOD AND APPARATUS FOR MAKING ELECTRICAL INTERCONNECTIONS BETWEEN LAYERS OF AN IC PACKAGE
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08972231
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Filing Dt:
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11/18/1997
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Title:
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TESTING ESD PROTECTION SCHEMES IN SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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08972904
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Filing Dt:
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11/18/1997
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Title:
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INTEGRATED CIRCUIT CONDUCTORS THAT AVOID CURRENT CROWDING
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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08974846
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Filing Dt:
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11/20/1997
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Title:
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IDDQ TEST SOLUTION FOR LARGE ASICS
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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08975025
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Filing Dt:
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11/20/1997
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Title:
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REMOVAL OF A HEAT SPREADER FROM AN INTEGRATED CIRCUIT PACKAGE TO PERMIT TESTING OF THE INTEGRATED CIRCUIT AND OTHER ELEMENTS OF THE PACKAGE
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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08975250
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Filing Dt:
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11/20/1997
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Title:
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LOW-DISPLACEMENT RANK PRECONDITIONERS FOR SIMPLIFIED NON-LINEAR ANALYSIS OF CIRCUITS AND OTHER DEVICES
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08976033
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Filing Dt:
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11/21/1997
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Title:
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METHOD AND COMPOSITION FOR REDUCING GATE OXIDE DAMAGE DURING RF SPUTTER CLEAN
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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08977318
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Filing Dt:
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11/24/1997
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Title:
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POLYCIDE GATE STRUCTURE WITH INTERMEDIATE BARRIER
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08977319
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Filing Dt:
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11/24/1997
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Title:
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LAYERED SILICON NITRIDE DEPOSITION PROCESS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08978979
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Filing Dt:
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11/26/1997
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Title:
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IMPROVED ELECTRO-STATIC DISCHARGE PROTECTION OF CMOS INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08979063
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Filing Dt:
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11/26/1997
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Title:
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OVERCAST SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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12/15/1998
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Application #:
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08979297
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Filing Dt:
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11/26/1997
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Title:
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METHOD FOR REMOVING ETCHING RESIDUES AND CONTAMINANTS
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08979733
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Filing Dt:
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11/26/1997
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Title:
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PURGING GAS CONTROL STRUCTURE FOR CVD CHAMBER
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08979734
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Filing Dt:
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11/26/1997
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Title:
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IN SITU ETCH OF CVD CHAMBER
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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08980943
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Filing Dt:
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12/01/1997
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Title:
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CHEMICAL MECHANICAL POLISHING CARRIER FIXTURE AND SYSTEM
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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08982109
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Filing Dt:
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12/01/1997
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Title:
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METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT USING CHEMICAL MECHANICAL POLISHING
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08984003
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Filing Dt:
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12/03/1997
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT CORE PROBING FOR FAILURE ANALYSIS
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