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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054528/0023   Pages: 9
Recorded: 11/26/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 107
Page 1 of 2
Pages: 1 2
1
Patent #:
6383920
Issue Dt:
05/07/2002
Application #:
09757894
Filing Dt:
01/10/2001
Title:
PROCESS OF ENCLOSING VIA FOR IMPROVED RELIABILITY IN DUAL DAMASCENE INTERCONNECTS
2
Patent #:
7192997
Issue Dt:
03/20/2007
Application #:
09778996
Filing Dt:
02/07/2001
Publication #:
US20020105093
Pub Dt:
08/08/2002
Title:
ENCAPSULANT COMPOSITION AND ELECTRONIC PACKAGE UTILIZING SAME
3
Patent #:
6534371
Issue Dt:
03/18/2003
Application #:
09878605
Filing Dt:
06/11/2001
Publication #:
US20020185708
Pub Dt:
12/12/2002
Title:
C IMPLANTS FOR IMPROVED SIGE BIPOLAR YIELD
4
Patent #:
6492238
Issue Dt:
12/10/2002
Application #:
09887310
Filing Dt:
06/22/2001
Publication #:
US20020197783
Pub Dt:
12/26/2002
Title:
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC BASE FABRICATED IN AN INTEGRATED BICMOS CIRCUIT
5
Patent #:
6798017
Issue Dt:
09/28/2004
Application #:
09944665
Filing Dt:
08/31/2001
Publication #:
US20030052364
Pub Dt:
03/20/2003
Title:
VERTICAL DUAL GATE FIELD EFFECT TRANSISTOR
6
Patent #:
6885080
Issue Dt:
04/26/2005
Application #:
10082648
Filing Dt:
02/22/2002
Publication #:
US20030162400
Pub Dt:
08/28/2003
Title:
DEEP TRENCH ISOLATION OF EMBEDDED DRAM FOR IMPROVED LATCH-UP IMMUNITY
7
Patent #:
6777761
Issue Dt:
08/17/2004
Application #:
10214084
Filing Dt:
08/06/2002
Publication #:
US20040026734
Pub Dt:
02/12/2004
Title:
SEMICONDUCTOR CHIP USING BOTH POLYSILICON AND METAL GATE DEVICES
8
Patent #:
6818952
Issue Dt:
11/16/2004
Application #:
10262190
Filing Dt:
10/01/2002
Publication #:
US20040061172
Pub Dt:
04/01/2004
Title:
DAMASCENE GATE MULTI-MESA MOSFET
9
Patent #:
6667521
Issue Dt:
12/23/2003
Application #:
10283739
Filing Dt:
10/29/2002
Publication #:
US20030064555
Pub Dt:
04/03/2003
Title:
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC BASE FABRICATED IN AN INTEGRATED BICMOS CIRCUIT
10
Patent #:
6720590
Issue Dt:
04/13/2004
Application #:
10338476
Filing Dt:
01/08/2003
Publication #:
US20030136975
Pub Dt:
07/24/2003
Title:
C IMPLANTS FOR IMPROVED SIGE BIPOLAR YIELD
11
Patent #:
7625792
Issue Dt:
12/01/2009
Application #:
10599938
Filing Dt:
10/13/2006
Publication #:
US20070207567
Pub Dt:
09/06/2007
Title:
METHOD OF BASE FORMATION IN A BICMOS PROCESS
12
Patent #:
7038298
Issue Dt:
05/02/2006
Application #:
10604045
Filing Dt:
06/24/2003
Publication #:
US20040262713
Pub Dt:
12/30/2004
Title:
HIGH FT AND FMAX BIPOLAR TRANSISTOR AND METHOD OF MAKING SAME
13
Patent #:
6911681
Issue Dt:
06/28/2005
Application #:
10709113
Filing Dt:
04/14/2004
Title:
A METHOD OF BASE FORMATION IN A BICMOS PROCESS
14
Patent #:
7002190
Issue Dt:
02/21/2006
Application #:
10711479
Filing Dt:
09/21/2004
Title:
METHOD OF COLLECTOR FORMATION IN BICMOS TECHNOLOGY
15
Patent #:
6977398
Issue Dt:
12/20/2005
Application #:
10819732
Filing Dt:
04/07/2004
Publication #:
US20040188711
Pub Dt:
09/30/2004
Title:
C IMPLANTS FOR IMPROVED SIGE BIPOLAR YIELD
16
Patent #:
7361973
Issue Dt:
04/22/2008
Application #:
10851828
Filing Dt:
05/21/2004
Publication #:
US20050258515
Pub Dt:
11/24/2005
Title:
EMBEDDED STRESSED NITRIDE LINERS FOR CMOS PERFORMANCE IMPROVEMENT
17
Patent #:
7176089
Issue Dt:
02/13/2007
Application #:
10853177
Filing Dt:
05/26/2004
Publication #:
US20040219725
Pub Dt:
11/04/2004
Title:
VERTICAL DUAL GATE FIELD EFFECT TRANSISTOR
18
Patent #:
7173312
Issue Dt:
02/06/2007
Application #:
10905101
Filing Dt:
12/15/2004
Publication #:
US20060124974
Pub Dt:
06/15/2006
Title:
STRUCTURE AND METHOD TO GENERATE LOCAL MECHANICAL GATE STRESS FOR MOSFET CHANNEL MOBILITY MODIFICATION
19
Patent #:
7138319
Issue Dt:
11/21/2006
Application #:
10905538
Filing Dt:
01/10/2005
Publication #:
US20050106836
Pub Dt:
05/19/2005
Title:
DEEP TRENCH ISOLATION OF EMBEDDED DRAM FOR IMPROVED LATCH-UP IMMUNITY
20
Patent #:
7081387
Issue Dt:
07/25/2006
Application #:
10918949
Filing Dt:
08/16/2004
Publication #:
US20050012145
Pub Dt:
01/20/2005
Title:
DAMASCENE GATE MULTI-MESA MOSFET
21
Patent #:
7314794
Issue Dt:
01/01/2008
Application #:
11161534
Filing Dt:
08/08/2005
Publication #:
US20070029620
Pub Dt:
02/08/2007
Title:
LOW-COST HIGH-PERFORMANCE PLANAR BACK-GATE CMOS
22
Patent #:
7224021
Issue Dt:
05/29/2007
Application #:
11162424
Filing Dt:
09/09/2005
Publication #:
US20070057334
Pub Dt:
03/15/2007
Title:
MOSFET WITH HIGH ANGLE SIDEWALL GATE AND CONTACTS FOR REDUCED MILLER CAPACITANCE
23
Patent #:
7348638
Issue Dt:
03/25/2008
Application #:
11164179
Filing Dt:
11/14/2005
Publication #:
US20070108531
Pub Dt:
05/17/2007
Title:
ROTATIONAL SHEAR STRESS FOR CHARGE CARRIER MOBILITY MODIFICATION
24
Patent #:
7491985
Issue Dt:
02/17/2009
Application #:
11288843
Filing Dt:
11/29/2005
Publication #:
US20060124964
Pub Dt:
06/15/2006
Title:
METHOD OF COLLECTOR FORMATION IN BICMOS TECHNOLOGY
25
Patent #:
7339230
Issue Dt:
03/04/2008
Application #:
11306707
Filing Dt:
01/09/2006
Publication #:
US20070170472
Pub Dt:
07/26/2007
Title:
STRUCTURE AND METHOD FOR MAKING HIGH DENSITY MOSFET CIRCUITS WITH DIFFERENT HEIGHT CONTACT LINES
26
Patent #:
7635620
Issue Dt:
12/22/2009
Application #:
11306745
Filing Dt:
01/10/2006
Publication #:
US20080217665
Pub Dt:
09/11/2008
Title:
SEMICONDUCTOR DEVICE STRUCTURE HAVING ENHANCED PERFORMANCE FET DEVICE
27
Patent #:
7521327
Issue Dt:
04/21/2009
Application #:
11378927
Filing Dt:
03/17/2006
Publication #:
US20060177986
Pub Dt:
08/10/2006
Title:
HIGH FT AND FMAX BIPOLAR TRANSISTOR AND METHOD OF MAKING SAME
28
Patent #:
7361539
Issue Dt:
04/22/2008
Application #:
11383560
Filing Dt:
05/16/2006
Publication #:
US20070269942
Pub Dt:
11/22/2007
Title:
DUAL STRESS LINER
29
Patent #:
7618866
Issue Dt:
11/17/2009
Application #:
11423227
Filing Dt:
06/09/2006
Publication #:
US20080006818
Pub Dt:
01/10/2008
Title:
STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS
30
Patent #:
7553760
Issue Dt:
06/30/2009
Application #:
11550966
Filing Dt:
10/19/2006
Publication #:
US20080093743
Pub Dt:
04/24/2008
Title:
SUB-LITHOGRAPHIC NANO INTERCONNECT STRUCTURES, AND METHOD FOR FORMING SAME
31
Patent #:
7384852
Issue Dt:
06/10/2008
Application #:
11552641
Filing Dt:
10/25/2006
Publication #:
US20080099845
Pub Dt:
05/01/2008
Title:
SUB-LITHOGRAPHIC GATE LENGTH TRANSISTOR USING SELF-ASSEMBLING POLYMERS
32
Patent #:
7576003
Issue Dt:
08/18/2009
Application #:
11564314
Filing Dt:
11/29/2006
Publication #:
US20080122045
Pub Dt:
05/29/2008
Title:
DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE AND METHOD
33
Patent #:
7314789
Issue Dt:
01/01/2008
Application #:
11618751
Filing Dt:
12/30/2006
Publication #:
US20070111421
Pub Dt:
05/17/2007
Title:
STRUCTURE AND METHOD TO GENERATE LOCAL MECHANICAL GATE STRESS FOR MOSFET CHANNEL MOBILITY MODIFICATION
34
Patent #:
7888197
Issue Dt:
02/15/2011
Application #:
11622056
Filing Dt:
01/11/2007
Publication #:
US20080169508
Pub Dt:
07/17/2008
Title:
METHOD OF FORMING STRESSED SOI FET HAVING DOPED GLASS BOX LAYER USING SACRIFICAL STRESSED LAYER
35
Patent #:
7767099
Issue Dt:
08/03/2010
Application #:
11627488
Filing Dt:
01/26/2007
Publication #:
US20080182402
Pub Dt:
07/31/2008
Title:
SUB-LITHOGRAPHIC INTERCONNECT PATTERNING USING SELF-ASSEMBLING POLYMERS
36
Patent #:
7632724
Issue Dt:
12/15/2009
Application #:
11673716
Filing Dt:
02/12/2007
Publication #:
US20080191281
Pub Dt:
08/14/2008
Title:
STRESSED SOI FET HAVING TENSILE AND COMPRESSIVE DEVICE REGIONS
37
Patent #:
7626244
Issue Dt:
12/01/2009
Application #:
11679880
Filing Dt:
02/28/2007
Publication #:
US20080203448
Pub Dt:
08/28/2008
Title:
STRESSED DIELECTRIC DEVICES AND METHODS OF FABRICATING SAME
38
Patent #:
7321005
Issue Dt:
01/22/2008
Application #:
11687997
Filing Dt:
03/19/2007
Publication #:
US20070185227
Pub Dt:
08/09/2007
Title:
ENCAPSULANT COMPOSITION AND ELECTRONIC PACKAGE UTILIZING SAME
39
Patent #:
7384682
Issue Dt:
06/10/2008
Application #:
11861806
Filing Dt:
09/26/2007
Publication #:
US20080012156
Pub Dt:
01/17/2008
Title:
ELECTRONIC PACKAGE WITH EPOXY OR CYANATE ESTER RESIN ENCAPSULANT
40
Patent #:
7964910
Issue Dt:
06/21/2011
Application #:
11873731
Filing Dt:
10/17/2007
Publication #:
US20090101942
Pub Dt:
04/23/2009
Title:
A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE HAVING AN ANGLED CRYSTALLOGRAPHIC ETCH-DEFINED SOURCE/DRAIN RECESS AND A METHOD OF FORMING THE TRANSISTOR STRUCTURE
41
Patent #:
7750415
Issue Dt:
07/06/2010
Application #:
11874963
Filing Dt:
10/19/2007
Publication #:
US20080029836
Pub Dt:
02/07/2008
Title:
STRUCTURE AND METHOD FOR MAKING HIGH DENSITY MOSFET CIRCUITS WITH DIFFERENT HEIGHT CONTACT LINES
42
Patent #:
7615454
Issue Dt:
11/10/2009
Application #:
11876415
Filing Dt:
10/22/2007
Publication #:
US20080044974
Pub Dt:
02/21/2008
Title:
EMBEDDED STRESSED NITRIDE LINERS FOR CMOS PERFORMANCE IMPROVEMENT
43
Patent #:
7750405
Issue Dt:
07/06/2010
Application #:
11877865
Filing Dt:
10/24/2007
Publication #:
US20080042205
Pub Dt:
02/21/2008
Title:
LOW-COST HIGH-PERFORMANCE PLANAR BACK-GATE CMOS
44
Patent #:
7504697
Issue Dt:
03/17/2009
Application #:
11965993
Filing Dt:
12/28/2007
Publication #:
US20080105953
Pub Dt:
05/08/2008
Title:
ROTATIONAL SHEAR STRESS FOR CHARGE CARRIER MOBILITY MODIFICATION
45
Patent #:
8013397
Issue Dt:
09/06/2011
Application #:
12049450
Filing Dt:
03/17/2008
Publication #:
US20080164532
Pub Dt:
07/10/2008
Title:
EMBEDDED STRESSED NITRIDE LINERS FOR CMOS PERFORMANCE IMPROVEMENT
46
Patent #:
7943454
Issue Dt:
05/17/2011
Application #:
12080016
Filing Dt:
03/31/2008
Publication #:
US20080185657
Pub Dt:
08/07/2008
Title:
METHOD FOR DUAL STRESS LINER
47
Patent #:
7786527
Issue Dt:
08/31/2010
Application #:
12099435
Filing Dt:
04/08/2008
Publication #:
US20080179667
Pub Dt:
07/31/2008
Title:
SUB-LITHOGRAPHIC GATE LENGTH TRANSISTOR USING SELF-ASSEMBLING POLYMERS
48
Patent #:
7560501
Issue Dt:
07/14/2009
Application #:
12128731
Filing Dt:
05/29/2008
Publication #:
US20080227902
Pub Dt:
09/18/2008
Title:
ENCAPSULANT OF EPOXY OR CYANATE ESTER RESIN, REACTIVE FLEXIBILIZER AND THERMOPLASTIC
49
Patent #:
7772119
Issue Dt:
08/10/2010
Application #:
12186923
Filing Dt:
08/06/2008
Publication #:
US20080293257
Pub Dt:
11/27/2008
Title:
DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE
50
Patent #:
7709960
Issue Dt:
05/04/2010
Application #:
12186932
Filing Dt:
08/06/2008
Publication #:
US20080290519
Pub Dt:
11/27/2008
Title:
DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE
51
Patent #:
7888252
Issue Dt:
02/15/2011
Application #:
12372174
Filing Dt:
02/17/2009
Publication #:
US20100210098
Pub Dt:
08/19/2010
Title:
SELF-ALIGNED CONTACT
52
Patent #:
7821109
Issue Dt:
10/26/2010
Application #:
12570045
Filing Dt:
09/30/2009
Publication #:
US20100013019
Pub Dt:
01/21/2010
Title:
STRESSED DIELECTRIC DEVICES AND METHODS OF FABRICATING SAME
53
Patent #:
7960798
Issue Dt:
06/14/2011
Application #:
12618152
Filing Dt:
11/13/2009
Publication #:
US20100059764
Pub Dt:
03/11/2010
Title:
STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS
54
Patent #:
7935993
Issue Dt:
05/03/2011
Application #:
12643482
Filing Dt:
12/21/2009
Publication #:
US20100096673
Pub Dt:
04/22/2010
Title:
SEMICONDUCTOR DEVICE STRUCTURE HAVING ENHANCED PERFORMANCE FET DEVICE
55
Patent #:
8377785
Issue Dt:
02/19/2013
Application #:
13080903
Filing Dt:
04/06/2011
Publication #:
US20110183481
Pub Dt:
07/28/2011
Title:
A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE HAVING AN ANGLED CRYSTALLOGRAPHIC ETCH-DEFINED SOURCE/DRAIN RECESS AND A METHOD OF FORMING THE TRANSISTOR STRUCTURE
56
Patent #:
8853862
Issue Dt:
10/07/2014
Application #:
13330817
Filing Dt:
12/20/2011
Publication #:
US20130154026
Pub Dt:
06/20/2013
Title:
CONTACT STRUCTURES FOR SEMICONDUCTOR TRANSISTORS
57
Patent #:
8901659
Issue Dt:
12/02/2014
Application #:
13369375
Filing Dt:
02/09/2012
Publication #:
US20130207079
Pub Dt:
08/15/2013
Title:
TAPERED NANOWIRE STRUCTURE WITH REDUCED OFF CURRENT
58
Patent #:
8889562
Issue Dt:
11/18/2014
Application #:
13555306
Filing Dt:
07/23/2012
Publication #:
US20140024215
Pub Dt:
01/23/2014
Title:
DOUBLE PATTERNING METHOD
59
Patent #:
8697528
Issue Dt:
04/15/2014
Application #:
13615955
Filing Dt:
09/14/2012
Publication #:
US20130001660
Pub Dt:
01/03/2013
Title:
METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSES FOR EPITAXIALLY DEPOSITED SOURCE/DRAIN REGIONS
60
Patent #:
9093376
Issue Dt:
07/28/2015
Application #:
13659202
Filing Dt:
10/24/2012
Publication #:
US20140110784
Pub Dt:
04/24/2014
Title:
REPLACEMENT METAL GATE FINFET
61
Patent #:
9153447
Issue Dt:
10/06/2015
Application #:
13672899
Filing Dt:
11/09/2012
Publication #:
US20140110785
Pub Dt:
04/24/2014
Title:
REPLACEMENT METAL GATE FINFET
62
Patent #:
8993389
Issue Dt:
03/31/2015
Application #:
13734012
Filing Dt:
01/04/2013
Publication #:
US20140191295
Pub Dt:
07/10/2014
Title:
DUMMY GATE INTERCONNECT FOR SEMICONDUCTOR DEVICE
63
Patent #:
9129825
Issue Dt:
09/08/2015
Application #:
14070038
Filing Dt:
11/01/2013
Publication #:
US20150123205
Pub Dt:
05/07/2015
Title:
FIELD EFFECT TRANSISTOR INCLUDING A REGROWN CONTOURED CHANNEL
64
Patent #:
9034755
Issue Dt:
05/19/2015
Application #:
14096243
Filing Dt:
12/04/2013
Publication #:
US20140094014
Pub Dt:
04/03/2014
Title:
METHOD OF EPITAXIALLY FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR TRANSISTORS
65
Patent #:
9397118
Issue Dt:
07/19/2016
Application #:
14318846
Filing Dt:
06/30/2014
Publication #:
US20150380440
Pub Dt:
12/31/2015
Title:
THIN-FILM AMBIPOLAR LOGIC
66
Patent #:
9514937
Issue Dt:
12/06/2016
Application #:
14477355
Filing Dt:
09/04/2014
Publication #:
US20140370667
Pub Dt:
12/18/2014
Title:
TAPERED NANOWIRE STRUCTURE WITH REDUCED OFF CURRENT
67
Patent #:
9431266
Issue Dt:
08/30/2016
Application #:
14501893
Filing Dt:
09/30/2014
Publication #:
US20150056809
Pub Dt:
02/26/2015
Title:
DOUBLE PATTERNING METHOD
68
Patent #:
9472407
Issue Dt:
10/18/2016
Application #:
14609690
Filing Dt:
01/30/2015
Publication #:
US20150137243
Pub Dt:
05/21/2015
Title:
REPLACEMENT METAL GATE FINFET
69
Patent #:
9530651
Issue Dt:
12/27/2016
Application #:
14609790
Filing Dt:
01/30/2015
Publication #:
US20150137244
Pub Dt:
05/21/2015
Title:
REPLACEMENT METAL GATE FINFET
70
Patent #:
9437436
Issue Dt:
09/06/2016
Application #:
14609803
Filing Dt:
01/30/2015
Publication #:
US20150137245
Pub Dt:
05/21/2015
Title:
REPLACEMENT METAL GATE FINFET
71
Patent #:
9560737
Issue Dt:
01/31/2017
Application #:
14637501
Filing Dt:
03/04/2015
Publication #:
US20160262253
Pub Dt:
09/08/2016
Title:
ELECTRONIC PACKAGE WITH HEAT TRANSFER ELEMENT(S)
72
Patent #:
9391094
Issue Dt:
07/12/2016
Application #:
14825271
Filing Dt:
08/13/2015
Publication #:
US20150380523
Pub Dt:
12/31/2015
Title:
THIN-FILM AMBIPOLAR LOGIC
73
Patent #:
10237964
Issue Dt:
03/19/2019
Application #:
14846897
Filing Dt:
09/07/2015
Publication #:
US20160262270
Pub Dt:
09/08/2016
Title:
MANUFACTURING ELECTRONIC PACKAGE WITH HEAT TRANSFER ELEMENT(S)
74
Patent #:
9496371
Issue Dt:
11/15/2016
Application #:
14877051
Filing Dt:
10/07/2015
Title:
CHANNEL PROTECTION DURING FIN FABRICATION
75
Patent #:
10014373
Issue Dt:
07/03/2018
Application #:
14878861
Filing Dt:
10/08/2015
Publication #:
US20170104058
Pub Dt:
04/13/2017
Title:
FABRICATION OF SEMICONDUCTOR JUNCTIONS
76
Patent #:
9449921
Issue Dt:
09/20/2016
Application #:
14969822
Filing Dt:
12/15/2015
Title:
VOIDLESS CONTACT METAL STRUCTURES
77
Patent #:
9472556
Issue Dt:
10/18/2016
Application #:
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Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
09/29/2020
Assignee
1
ELPIS TECHNOLOGIES INC.
1891 ROBERTSON ROAD
SUITE 100
OTTAWA, CANADA K2H 5B7
Correspondence name and address
ELPIS TECHNOLOGIES INC.
1891 ROBERTSON ROAD
SUITE 100
OTTAWA, K2H 5B7 CANADA

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