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Reel/Frame:017566/0028   Pages: 7
Recorded: 05/03/2006
Attorney Dkt #:MEGICA RECORD-PENDINGPAS
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 48
1
Patent #:
7247932
Issue Dt:
07/24/2007
Application #:
09573955
Filing Dt:
05/19/2000
Title:
CHIP PACKAGE WITH CAPACITOR
2
Patent #:
7498196
Issue Dt:
03/03/2009
Application #:
09821546
Filing Dt:
03/30/2001
Publication #:
US20020140069
Pub Dt:
10/03/2002
Title:
STRUCTURE AND MANUFACTRUING METHOD OF CHIP SCALE PACKAGE
3
Patent #:
7405149
Issue Dt:
07/29/2008
Application #:
10154662
Filing Dt:
05/24/2002
Title:
POST PASSIVATION METHOD FOR SEMICONDUCTOR CHIP OR WAFER
4
Patent #:
7045901
Issue Dt:
05/16/2006
Application #:
10371505
Filing Dt:
02/21/2003
Publication #:
US20030127749
Pub Dt:
07/10/2003
Title:
MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS
5
Patent #:
7205646
Issue Dt:
04/17/2007
Application #:
10420595
Filing Dt:
04/22/2003
Publication #:
US20030205826
Pub Dt:
11/06/2003
Title:
ELECTRONIC DEVICE AND CHIP PACKAGE
6
Patent #:
7378735
Issue Dt:
05/27/2008
Application #:
10420596
Filing Dt:
04/22/2003
Publication #:
US20030199119
Pub Dt:
10/23/2003
Title:
HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY
7
Patent #:
8021976
Issue Dt:
09/20/2011
Application #:
10434142
Filing Dt:
05/08/2003
Publication #:
US20040070042
Pub Dt:
04/15/2004
Title:
METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
8
Patent #:
7468551
Issue Dt:
12/23/2008
Application #:
10437333
Filing Dt:
05/13/2003
Publication #:
US20030201545
Pub Dt:
10/30/2003
Title:
MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS
9
Patent #:
8178435
Issue Dt:
05/15/2012
Application #:
10445558
Filing Dt:
05/27/2003
Publication #:
US20030222295
Pub Dt:
12/04/2003
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP INDUCTOR USING POST PASSIVATION PROCESS
10
Patent #:
7531417
Issue Dt:
05/12/2009
Application #:
10445559
Filing Dt:
05/27/2003
Publication #:
US20040029404
Pub Dt:
02/12/2004
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP PASSIVE DEVICE USING POST PASSIVATION PROCESS
11
Patent #:
7282804
Issue Dt:
10/16/2007
Application #:
10614928
Filing Dt:
07/08/2003
Publication #:
US20040023436
Pub Dt:
02/05/2004
Title:
STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD
12
Patent #:
7443033
Issue Dt:
10/28/2008
Application #:
10653628
Filing Dt:
09/02/2003
Publication #:
US20060038231
Pub Dt:
02/23/2006
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
13
Patent #:
7230340
Issue Dt:
06/12/2007
Application #:
10685872
Filing Dt:
10/15/2003
Publication #:
US20040089951
Pub Dt:
05/13/2004
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
14
Patent #:
NONE
Issue Dt:
Application #:
10690350
Filing Dt:
10/21/2003
Publication #:
US20040063249
Pub Dt:
04/01/2004
Title:
Thin film semiconductor package and method of fabrication
15
Patent #:
7420276
Issue Dt:
09/02/2008
Application #:
10783195
Filing Dt:
02/20/2004
Publication #:
US20040166659
Pub Dt:
08/26/2004
Title:
POST PASSIVATION STRUCTURE FOR SEMICONDUCTOR CHIP OR WAFER
16
Patent #:
NONE
Issue Dt:
Application #:
10786807
Filing Dt:
02/25/2004
Publication #:
US20050186690
Pub Dt:
08/25/2005
Title:
Method for improving semiconductor wafer test accuracy
17
Patent #:
7470997
Issue Dt:
12/30/2008
Application #:
10796427
Filing Dt:
03/09/2004
Publication #:
US20050017361
Pub Dt:
01/27/2005
Title:
WIREBOND PAD FOR SEMICONDUCTOR CHIP OR WAFER
18
Patent #:
8368150
Issue Dt:
02/05/2013
Application #:
10802566
Filing Dt:
03/17/2004
Publication #:
US20040183209
Pub Dt:
09/23/2004
Title:
HIGH PERFORMANCE IC CHIP HAVING DISCRETE DECOUPLING CAPACITORS ATTACHED TO ITS IC SURFACE
19
Patent #:
8674507
Issue Dt:
03/18/2014
Application #:
10855086
Filing Dt:
05/27/2004
Publication #:
US20050017355
Pub Dt:
01/27/2005
Title:
WAFER LEVEL PROCESSING METHOD AND STRUCTURE TO MANUFACTURE TWO KINDS OF INTERCONNECTS, GOLD AND SOLDER, ON ONE WAFER
20
Patent #:
7319377
Issue Dt:
01/15/2008
Application #:
10856377
Filing Dt:
05/28/2004
Publication #:
US20040217840
Pub Dt:
11/04/2004
Title:
METHOD FOR MAKING HIGH-PERFORMANCE RF INTEGRATED CIRCUITS
21
Patent #:
7265045
Issue Dt:
09/04/2007
Application #:
10925302
Filing Dt:
08/24/2004
Publication #:
US20050020052
Pub Dt:
01/27/2005
Title:
METHOD FOR FABRICATING THERMAL COMPLIANT SEMICONDUCTOR CHIP WIRING STRUCTURE FOR CHIP SCALE PACKAGING
22
Patent #:
8368213
Issue Dt:
02/05/2013
Application #:
10935451
Filing Dt:
09/07/2004
Publication #:
US20050032349
Pub Dt:
02/10/2005
Title:
LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP
23
Patent #:
7423346
Issue Dt:
09/09/2008
Application #:
10937543
Filing Dt:
09/09/2004
Publication #:
US20060049524
Pub Dt:
03/09/2006
Title:
POST PASSIVATION INTERCONNECTION PROCESS AND STRUCTURES
24
Patent #:
7416971
Issue Dt:
08/26/2008
Application #:
10948020
Filing Dt:
09/23/2004
Publication #:
US20060063371
Pub Dt:
03/23/2006
Title:
TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
25
Patent #:
NONE
Issue Dt:
Application #:
10954781
Filing Dt:
09/30/2004
Publication #:
US20050040033
Pub Dt:
02/24/2005
Title:
METHOD OF METAL SPUTTERING FOR INTEGRATED CIRCUIT METAL ROUTING
26
Patent #:
7271489
Issue Dt:
09/18/2007
Application #:
10962963
Filing Dt:
10/12/2004
Publication #:
US20060076687
Pub Dt:
04/13/2006
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
27
Patent #:
7465653
Issue Dt:
12/16/2008
Application #:
10962964
Filing Dt:
10/12/2004
Publication #:
US20050070085
Pub Dt:
03/31/2005
Title:
RELIABLE METAL BUMPS ON TOP OF I/O PADS AFTER REMOVAL OF TEST PROBE MARKS
28
Patent #:
7355282
Issue Dt:
04/08/2008
Application #:
10970871
Filing Dt:
10/22/2004
Publication #:
US20060049483
Pub Dt:
03/09/2006
Title:
POST PASSIVATION INTERCONNECTION PROCESS AND STRUCTURES
29
Patent #:
7397117
Issue Dt:
07/08/2008
Application #:
10996535
Filing Dt:
11/24/2004
Publication #:
US20050093113
Pub Dt:
05/05/2005
Title:
CHIP PACKAGE WITH DIE AND SUBSTRATE
30
Patent #:
7977763
Issue Dt:
07/12/2011
Application #:
10996537
Filing Dt:
11/24/2004
Publication #:
US20050090099
Pub Dt:
04/28/2005
Title:
CHIP PACKAGE WITH DIE AND SUBSTRATE
31
Patent #:
7372161
Issue Dt:
05/13/2008
Application #:
11017145
Filing Dt:
12/20/2004
Publication #:
US20050104177
Pub Dt:
05/19/2005
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
32
Patent #:
7381642
Issue Dt:
06/03/2008
Application #:
11017168
Filing Dt:
12/20/2004
Publication #:
US20060063378
Pub Dt:
03/23/2006
Title:
TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
33
Patent #:
8008775
Issue Dt:
08/30/2011
Application #:
11017169
Filing Dt:
12/20/2004
Publication #:
US20060049525
Pub Dt:
03/09/2006
Title:
POST PASSIVATION INTERCONNECTION STRUCTURES
34
Patent #:
8089155
Issue Dt:
01/03/2012
Application #:
11062276
Filing Dt:
02/18/2005
Publication #:
US20050230783
Pub Dt:
10/20/2005
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP DISCRETE COMPONENTS USING POST PASSIVATION PROCESS
35
Patent #:
8129265
Issue Dt:
03/06/2012
Application #:
11062277
Filing Dt:
02/18/2005
Publication #:
US20050170634
Pub Dt:
08/04/2005
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP DISCRETE COMPONENTS USING POST PASSIVATION PROCESS
36
Patent #:
8552559
Issue Dt:
10/08/2013
Application #:
11087955
Filing Dt:
03/23/2005
Publication #:
US20060022343
Pub Dt:
02/02/2006
Title:
VERY THICK METAL INTERCONNECTION SCHEME IN IC CHIPS
37
Patent #:
7459761
Issue Dt:
12/02/2008
Application #:
11092379
Filing Dt:
03/29/2005
Publication #:
US20050184358
Pub Dt:
08/25/2005
Title:
HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS
38
Patent #:
7355288
Issue Dt:
04/08/2008
Application #:
11120234
Filing Dt:
05/02/2005
Publication #:
US20050189650
Pub Dt:
09/01/2005
Title:
LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE
39
Patent #:
7338890
Issue Dt:
03/04/2008
Application #:
11136650
Filing Dt:
05/24/2005
Publication #:
US20050215043
Pub Dt:
09/29/2005
Title:
LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE
40
Patent #:
7465654
Issue Dt:
12/16/2008
Application #:
11178541
Filing Dt:
07/11/2005
Publication #:
US20060019490
Pub Dt:
01/26/2006
Title:
STRUCTURE OF GOLD BUMPS AND GOLD CONDUCTORS ON ONE IC DIE AND METHODS OF MANUFACTURING THE STRUCTURES
41
Patent #:
7372162
Issue Dt:
05/13/2008
Application #:
11181175
Filing Dt:
07/14/2005
Publication #:
US20050251586
Pub Dt:
11/10/2005
Title:
MULTIPLE SELECTABLE FUNCTION INTEGRATED CIRCUIT MODULE
42
Patent #:
RE40887
Issue Dt:
09/01/2009
Application #:
11183300
Filing Dt:
07/15/2005
Title:
SEMICONDUCTOR CHIP WITH REDISTRIBUTION METAL LAYER
43
Patent #:
7405150
Issue Dt:
07/29/2008
Application #:
11273071
Filing Dt:
11/14/2005
Publication #:
US20060068574
Pub Dt:
03/30/2006
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
44
Patent #:
7276422
Issue Dt:
10/02/2007
Application #:
11273085
Filing Dt:
11/14/2005
Publication #:
US20060060973
Pub Dt:
03/23/2006
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
45
Patent #:
7265047
Issue Dt:
09/04/2007
Application #:
11273105
Filing Dt:
11/14/2005
Publication #:
US20060076684
Pub Dt:
04/13/2006
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
46
Patent #:
7351650
Issue Dt:
04/01/2008
Application #:
11273447
Filing Dt:
11/14/2005
Publication #:
US20060063374
Pub Dt:
03/23/2006
Title:
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
47
Patent #:
8723322
Issue Dt:
05/13/2014
Application #:
11364375
Filing Dt:
02/28/2006
Publication #:
US20060148247
Pub Dt:
07/06/2006
Title:
METHOD OF METAL SPUTTERING FOR INTEGRATED CIRCUIT METAL ROUTING
48
Patent #:
NONE
Issue Dt:
Application #:
11389717
Filing Dt:
03/27/2006
Publication #:
US20060163729
Pub Dt:
07/27/2006
Title:
Structure and manufacturing method of a chip scale package
Assignor
1
MEGIC CORPORATION
Exec Dt:
04/28/2006
Assignee
1
MEGICA CORPORATION
NO. 47, PARK 2ND RD. SCIENCE-BASED INDUSTRIAL PARK
ROOM 301/302
HSINCHU, TAIWAN
Correspondence name and address
SAILE ACKERMAN, LLC
28 DAVIS AVENUE
POUGKEEPSIE, NY 12601

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