Total properties:
35
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08917149
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Filing Dt:
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08/25/1997
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Title:
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REDUCTION OF CHARGE LOSS IN NONVOLATILE MEMORY CELLS BY PHOSPHORUS IMPLANTATION INTO PECVD NITRIDE/OXYNITRIDE FILMS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08986160
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Filing Dt:
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12/05/1997
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Title:
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SIDEWALL SPACER FOR PROTECTING TUNNEL OXIDE DURING ISOLATION TRENCH FORMATION IN SELF-ALIGNED FLASH MEMORY CORE
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08989820
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Filing Dt:
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12/12/1997
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Title:
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SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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08991448
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Filing Dt:
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12/16/1997
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Title:
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FLASH MEMORY GATE COUPLING USING HSG POLYSILICON
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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08992077
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Filing Dt:
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12/17/1997
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Title:
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METHOD TO IMPROVE TESTING SPEED OF MEMORY
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08992536
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Filing Dt:
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12/17/1997
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Title:
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METHOD FOR FULLY PLANARIZED CONDUCTIVE LINE FOR A STACK GATE
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08992950
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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08992960
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR IMPROVED FORMATION OF CONTROL AND FLOATING GATES IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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08993409
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Filing Dt:
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12/18/1997
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Title:
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METHODS FOR FORMING A CONTROL GATE APPARATUS IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09019409
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Filing Dt:
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02/05/1998
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Title:
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METHOD FOR FORMING ISOLATION IN FLASH MEMORY WAFER
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Patent #:
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|
Issue Dt:
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09/04/2001
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Application #:
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09052057
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09052058
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09052060
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Filing Dt:
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03/30/1998
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Title:
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FULLY RECESSED SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH SINGLE WRAP AROUND BURIED DRAIN REGION
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Patent #:
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|
Issue Dt:
|
11/14/2000
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Application #:
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09052061
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Filing Dt:
|
03/30/1998
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Title:
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FULLY RECESSED SEMICONDUCTOR DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
03/07/2000
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Application #:
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09092352
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Filing Dt:
|
06/05/1998
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Title:
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A SEMICONDUCTOR DEVICE HAVING A REDUCED HEIGHT FLOATING GATE
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|
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Patent #:
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|
Issue Dt:
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01/16/2001
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Application #:
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09119777
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Filing Dt:
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07/21/1998
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Title:
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LOW TEMPERATURE PHOTORESIST REMOVAL FOR REWORK DURING METAL
MASK FORMATION
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|
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Patent #:
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|
Issue Dt:
|
08/08/2000
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Application #:
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09134525
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Filing Dt:
|
08/14/1998
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Title:
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MULTIPURPOSE GRADED SILICON OXYNITRIDE CAP LAYER
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|
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Patent #:
|
|
Issue Dt:
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08/22/2000
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Application #:
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09134526
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Filing Dt:
|
08/14/1998
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Title:
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METHOD FOR FABRICATING A DOPED POLYSILICON FEATURE IN A SEMICONDUCTOR DEVICE
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|
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Patent #:
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|
Issue Dt:
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10/26/1999
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Application #:
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09143090
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Filing Dt:
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08/28/1998
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Title:
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METHODS AND ARRANGEMENTS FOR INTRODUCING NITROGEN INTO A TUNNEL OXIDE IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
12/14/1999
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Application #:
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09154074
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Filing Dt:
|
09/16/1998
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Title:
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METHODS FOR FORMING NITROGEN-RICH REGIONS IN A FLOATING GATE AND INTERPOLY DIELECTRIC LAYER IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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|
Issue Dt:
|
06/05/2001
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Application #:
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09163310
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Filing Dt:
|
09/30/1998
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Title:
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SELF-ALIGNING POLY 1 ONO DIELECTRIC FOR NON-VOLATILE MEMORY
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|
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Patent #:
|
|
Issue Dt:
|
06/26/2001
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Application #:
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09163315
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Filing Dt:
|
09/30/1998
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Title:
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VIABLE MEMORY CELL FORMED USING RAPID THERMAL ANNEALING
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|
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Patent #:
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|
Issue Dt:
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12/19/2000
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Application #:
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09170061
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Filing Dt:
|
10/13/1998
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Title:
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METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
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|
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Patent #:
|
|
Issue Dt:
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04/03/2001
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Application #:
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09177294
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Filing Dt:
|
10/22/1998
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Title:
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PROCESS FOR FABRICATING A COMMON SOURCE REGION IN MEMORY DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
06/26/2001
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Application #:
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09377183
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Filing Dt:
|
08/19/1999
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Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING ASSYMETRICALLY NITROGEN DOPED GATE OXIDE
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|
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Patent #:
|
|
Issue Dt:
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10/30/2001
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Application #:
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09440934
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Filing Dt:
|
11/16/1999
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Title:
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SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
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Application #:
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09470568
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Filing Dt:
|
12/22/1999
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Title:
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FULLY RECESSED SEMICONDUCTOR METHOD FOR LOW POWER APPLICATIONS WITH SINGLE WRAP AROUND BURIED DRAIN REGION
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|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
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Application #:
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09476121
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Filing Dt:
|
01/03/2000
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
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Application #:
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09567534
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Filing Dt:
|
05/10/2000
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Title:
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Multipurpose graded silicon oxynitride cap layer
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|
|
Patent #:
|
|
Issue Dt:
|
02/05/2002
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Application #:
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09620339
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Filing Dt:
|
07/20/2000
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Title:
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Fully recessed semiconductor method for low power applications
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|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
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Application #:
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09629780
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Filing Dt:
|
07/31/2000
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR METHOD WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
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Application #:
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09632536
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Filing Dt:
|
08/04/2000
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Title:
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A TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH CORNER DOPING AND SIDEWALL DOPING
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|
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Patent #:
|
|
Issue Dt:
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06/17/2003
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Application #:
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09634991
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Filing Dt:
|
08/08/2000
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Title:
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SOURCE BUS FORMATION FOR A FLASH MEMORY USING SILICIDE
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|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
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Application #:
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09725843
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Filing Dt:
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11/30/2000
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Publication #:
|
|
Pub Dt:
|
08/23/2001
| | | | |
Title:
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METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
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|
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Patent #:
|
|
Issue Dt:
|
01/24/2006
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Application #:
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10718707
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Filing Dt:
|
11/24/2003
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Title:
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METHODS FOR FORMING NITROGEN-RICH REGIONS IN NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
|
|