Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 012671/0031 | |
| Pages: | 2 |
| | Recorded: | 03/04/2002 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
10091620
|
Filing Dt:
|
03/04/2002
|
Publication #:
|
|
Pub Dt:
|
07/25/2002
| | | | |
Title:
|
METHOD FOR DOUBLE-LAYER IMPLEMENTATION OF METAL OPTIONS IN AN INTEGRATED CHIP FOR EFFICIENT SILICON DEBUG
|
|
Assignee
|
|
|
901 SAN ANTONIO ROAD |
PALO ALTO, CALIFORNIA 94303 |
|
Correspondence name and address
|
|
THELEN REID & PREIEST LLP
|
|
DAVID B. RITCHIE
|
|
P.O. BOX 640640
|
|
SAN JOSE, CA 95164-0640
|
Search Results as of:
05/28/2024 09:56 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|