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Total properties:
21
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Patent #:
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Issue Dt:
|
08/29/2006
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Application #:
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10643799
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Filing Dt:
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08/18/2003
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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METHOD AND PLATFORM FOR INTEGRATED PHYSICAL VERIFICATIONS AND MANUFACTURING ENHANCEMENTS
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Patent #:
|
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Issue Dt:
|
12/12/2006
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Application #:
|
10787070
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Filing Dt:
|
02/25/2004
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Publication #:
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Pub Dt:
|
11/25/2004
| | | | |
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Title:
|
METHOD FOR CORRECTING A MASK DESIGN LAYOUT
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
|
10820260
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Filing Dt:
|
04/07/2004
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
|
Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
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Patent #:
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Issue Dt:
|
07/22/2008
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Application #:
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11074882
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Filing Dt:
|
03/07/2005
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Publication #:
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Pub Dt:
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10/13/2005
| | | | |
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Title:
|
INTERMEDIATE LAYOUT FOR RESOLUTION ENHANCEMENT IN SEMICONDUCTOR FABRICATION
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|
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Patent #:
|
|
Issue Dt:
|
02/26/2008
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Application #:
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11089723
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Filing Dt:
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03/24/2005
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Publication #:
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Pub Dt:
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10/19/2006
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Title:
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FLEXIBLE SHAPE IDENTIFICATION FOR OPTICAL PROXIMITY CORRECTION IN SEMICONDUCTOR FABRICATION
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|
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Patent #:
|
|
Issue Dt:
|
10/21/2008
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Application #:
|
11145025
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Filing Dt:
|
06/03/2005
|
|
Title:
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GATE-LENGTH BIASING FOR DIGITAL CIRCUIT OPTIMIZATION
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11199900
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Filing Dt:
|
08/08/2005
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Publication #:
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Pub Dt:
|
02/08/2007
| | | | |
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Title:
|
Method and system for reshaping metal wires in VLSI design
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|
|
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Patent #:
|
|
Issue Dt:
|
06/22/2010
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Application #:
|
11254643
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Filing Dt:
|
10/19/2005
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|
Publication #:
|
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Pub Dt:
|
07/06/2006
| | | | |
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Title:
|
METHOD AND SYSTEM FOR FINDING AN EQUIVALENT CIRCUIT REPRESENTATION FOR ONE OR MORE ELEMENTS IN AN INTEGRATED CIRCUIT
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/12/2010
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Application #:
|
11267686
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Filing Dt:
|
11/04/2005
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|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
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Title:
|
METHOD AND SYSTEM FOR TOPOGRAPHY-AWARE RETICLE ENHANCEMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
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Application #:
|
11331605
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Filing Dt:
|
01/14/2006
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|
Publication #:
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|
Pub Dt:
|
07/19/2007
| | | | |
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Title:
|
METHOD AND SYSTEM FOR PLACING LAYOUT OBJECTS IN A STANDARD-CELL LAYOUT
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/01/2009
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Application #:
|
11386268
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Filing Dt:
|
03/21/2006
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|
Title:
|
SYSTEM AND METHOD FOR VARYING THE STARTING CONDITIONS FOR A RESOLUTION ENHANCEMENT PROGRAM TO IMPROVE THE PROBABILITY THAT DESIGN GOALS WILL BE MET
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11391771
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Filing Dt:
|
03/28/2006
|
|
Title:
|
METHOD AND SYSTEM FOR RESHAPING A TRANSISTOR GATE IN AN INTEGRATED CIRCUIT TO ACHIEVE A TARGET OBJECTIVE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
11486511
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Filing Dt:
|
07/14/2006
|
|
Title:
|
ARRANGEMENT OF FILL UNIT ELEMENTS IN AN INTEGRATED CIRCUIT INTERCONNECT LAYER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
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Application #:
|
11486936
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Filing Dt:
|
07/13/2006
|
|
Title:
|
LAYOUT DESCRIPTION HAVING ENHANCED FILL ANNOTATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
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Application #:
|
11499070
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Filing Dt:
|
08/04/2006
|
|
Title:
|
METHOD AND SYSTEM FOR WAFER TOPOGRAPHY-AWARE INTEGRATED CIRCUIT DESIGN ANALYSIS AND OPTIMIZATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
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Application #:
|
11590581
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Filing Dt:
|
10/31/2006
|
|
Title:
|
METHOD OF DESIGNING A DIGITAL CIRCUIT BY CORRELATING DIFFERENT STATIC TIMING ANALYZERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11602043
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Filing Dt:
|
11/20/2006
|
|
Title:
|
METHOD AND SYSTEM FOR INTEGRATED CIRCUIT OPTIMIZATION BY USING AN OPTIMIZED STANDARD-CELL LIBRARY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
12075645
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Filing Dt:
|
03/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
|
Title:
|
PIEZOELECTRIC-BASED TOE-HEATERS FOR FROSTBITE PROTECTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12099663
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Filing Dt:
|
04/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
|
Title:
|
INTERMEDIATE LAYOUT FOR RESOLUTION ENHANCEMENT IN SEMICONDUCTOR FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12212353
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Filing Dt:
|
09/17/2008
|
|
Title:
|
GATE-LENGTH BIASING FOR DIGITAL CIRCUIT OPTIMIZATION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12288793
|
Filing Dt:
|
10/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2010
| | | | |
|
Title:
|
Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process
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|
