Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021867/0037 | |
| Pages: | 6 |
| | Recorded: | 11/20/2008 | | |
| Attorney Dkt #: | 211.025-US BRON |
| Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE RECEIVING PARTY PREVIOUSLY RECORDED ON REEL 019866 FRAME 0636. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. |
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Total properties:
1
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Patent #:
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Issue Dt:
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06/02/2009
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Application #:
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11821848
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Filing Dt:
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06/26/2007
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY HAVING A SEGMENTED BIT LINE ARCHITECTURE AND METHOD OF CONTROLLING AND/OR OPERATING SAME
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Assignee
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| PSE-BATIMENT B |
| LAUSANNE, SWITZERLAND CH-1015 |
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Correspondence name and address
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NEIL STEINBERG
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2300 M STREET, N.W.
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SUITE 800
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WASHINGTON, DC 20037
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