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Reel/Frame:037684/0039   Pages: 448
Recorded: 02/02/2016
Attorney Dkt #:040981-0072
Conveyance: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031)
Total properties: 11127
Page 76 of 112
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1
Patent #:
7669110
Issue Dt:
02/23/2010
Application #:
11241760
Filing Dt:
09/30/2005
Publication #:
US20070079225
Pub Dt:
04/05/2007
Title:
TRACE-AHEAD METHOD AND APPARATUS FOR DETERMINING SURVIVOR PATHS IN A VITERBI DETECTOR
2
Patent #:
8032818
Issue Dt:
10/04/2011
Application #:
11241761
Filing Dt:
09/30/2005
Publication #:
US20070076825
Pub Dt:
04/05/2007
Title:
METHOD AND APPARATUS FOR STORING SURVIVOR PATHS IN A VITERBI DETECTOR USING INPUT-DEPENDENT POINTER EXCHANGE
3
Patent #:
7218125
Issue Dt:
05/15/2007
Application #:
11241823
Filing Dt:
09/30/2005
Publication #:
US20070075712
Pub Dt:
04/05/2007
Title:
APPARATUS AND METHOD FOR PERFORMING A FOUR-POINT VOLTAGE MEASUREMENT FOR AN INTEGRATED CIRCUIT
4
Patent #:
7425867
Issue Dt:
09/16/2008
Application #:
11241874
Filing Dt:
09/30/2005
Publication #:
US20070075688
Pub Dt:
04/05/2007
Title:
DIFFERENTIAL INPUT/DIFFERENTIAL OUTPUT CONVERTER CIRCUIT
5
Patent #:
7180819
Issue Dt:
02/20/2007
Application #:
11243622
Filing Dt:
10/04/2005
Title:
CONVERTING DUAL PORT MEMORY INTO 2 SINGLE PORT MEMORIES
6
Patent #:
7406671
Issue Dt:
07/29/2008
Application #:
11243839
Filing Dt:
10/05/2005
Publication #:
US20070079269
Pub Dt:
04/05/2007
Title:
METHOD FOR PERFORMING DESIGN RULE CHECK OF INTEGRATED CIRCUIT
7
Patent #:
7370309
Issue Dt:
05/06/2008
Application #:
11244486
Filing Dt:
10/05/2005
Publication #:
US20070079274
Pub Dt:
04/05/2007
Title:
METHOD AND COMPUTER PROGRAM FOR DETAILED ROUTING OF AN INTEGRATED CIRCUIT DESIGN WITH MULTIPLE ROUTING RULES AND NET CONSTRAINTS
8
Patent #:
7415687
Issue Dt:
08/19/2008
Application #:
11244530
Filing Dt:
10/05/2005
Publication #:
US20070079273
Pub Dt:
04/05/2007
Title:
METHOD AND COMPUTER PROGRAM FOR INCREMENTAL PLACEMENT AND ROUTING WITH NESTED SHELLS
9
Patent #:
7573331
Issue Dt:
08/11/2009
Application #:
11244821
Filing Dt:
10/06/2005
Publication #:
US20060077584
Pub Dt:
04/13/2006
Title:
LOW POWER LOW NOISE AMPLIFIER FOR A MAGNETORESISTIVE SENSOR
10
Patent #:
7472302
Issue Dt:
12/30/2008
Application #:
11245513
Filing Dt:
10/07/2005
Publication #:
US20060041769
Pub Dt:
02/23/2006
Title:
METHOD AND APPARATUS FOR REDUCING LEAKAGE POWER IN A CACHE MEMORY USING ADAPTIVE TIME-BASED DECAY
11
Patent #:
7885681
Issue Dt:
02/08/2011
Application #:
11246654
Filing Dt:
10/07/2005
Publication #:
US20070082700
Pub Dt:
04/12/2007
Title:
METHOD OF USING MOBILE COMMUNICATIONS DEVICES FOR MONITORING PURPOSES AND A SYSTEM FOR IMPLEMENTATION THEREOF
12
Patent #:
7467363
Issue Dt:
12/16/2008
Application #:
11246880
Filing Dt:
10/07/2005
Publication #:
US20070083834
Pub Dt:
04/12/2007
Title:
METHOD FOR SRAM BITMAP VERIFICATION
13
Patent #:
7284213
Issue Dt:
10/16/2007
Application #:
11247517
Filing Dt:
10/11/2005
Publication #:
US20060226847
Pub Dt:
10/12/2006
Title:
DEFECT ANALYSIS USING A YIELD VEHICLE
14
Patent #:
7441210
Issue Dt:
10/21/2008
Application #:
11247630
Filing Dt:
10/11/2005
Publication #:
US20070083839
Pub Dt:
04/12/2007
Title:
ON-THE-FLY RTL INSTRUCTOR FOR ADVANCED DFT AND DESIGN CLOSURE
15
Patent #:
7406143
Issue Dt:
07/29/2008
Application #:
11247827
Filing Dt:
10/11/2005
Publication #:
US20060029174
Pub Dt:
02/09/2006
Title:
TRANSCEIVER HAVING A JITTER CONTROL PROCESSOR WITH A RECEIVER STAGE AND A METHOD OF OPERATION THEREOF
16
Patent #:
7290088
Issue Dt:
10/30/2007
Application #:
11247879
Filing Dt:
10/11/2005
Publication #:
US20070083706
Pub Dt:
04/12/2007
Title:
SYSTEM AND METHOD FOR COERCION OF DISK DRIVE SIZE FOR USE IN A RAID VOLUME
17
Patent #:
7363451
Issue Dt:
04/22/2008
Application #:
11248378
Filing Dt:
10/11/2005
Publication #:
US20070083703
Pub Dt:
04/12/2007
Title:
LOAD BALANCING OF DISK DRIVES
18
Patent #:
7397105
Issue Dt:
07/08/2008
Application #:
11248509
Filing Dt:
10/12/2005
Publication #:
US20060128113
Pub Dt:
06/15/2006
Title:
APPARATUS TO PASSIVATE INDUCTIVELY OR CAPACITIVELY COUPLED SURFACE CURRENTS UNDER CAPACITOR STRUCTURES
19
Patent #:
7493532
Issue Dt:
02/17/2009
Application #:
11251393
Filing Dt:
10/14/2005
Publication #:
US20070087615
Pub Dt:
04/19/2007
Title:
METHODS AND STRUCTURE FOR OPTIMIZING SAS DOMAIN LINK QUALITY AND PERFORMANCE
20
Patent #:
7644259
Issue Dt:
01/05/2010
Application #:
11252846
Filing Dt:
10/18/2005
Publication #:
US20070088941
Pub Dt:
04/19/2007
Title:
CUSTOMIZATION OF OPTION ROM IMAGES
21
Patent #:
7499146
Issue Dt:
03/03/2009
Application #:
11252877
Filing Dt:
10/19/2005
Publication #:
US20060203220
Pub Dt:
09/14/2006
Title:
LITHOGRAPHIC APPARATUS AND DEVICE MANUFACTURING METHOD, AN INTEGRATED CIRCUIT, A FLAT PANEL DISPLAY, AND A METHOD OF COMPENSATING FOR CUPPING
22
Patent #:
7656977
Issue Dt:
02/02/2010
Application #:
11256529
Filing Dt:
10/21/2005
Publication #:
US20070091994
Pub Dt:
04/26/2007
Title:
METHOD AND SYSTEM OF FREQUENCY DOMAIN EQUALIZATION
23
Patent #:
7271676
Issue Dt:
09/18/2007
Application #:
11256696
Filing Dt:
10/24/2005
Publication #:
US20070090888
Pub Dt:
04/26/2007
Title:
METHOD AND/OR APPARATUS FOR IMPLEMENTING A VOLTAGE CONTROLLED RING OSCILLATOR HAVING A MULTI-PEAK DETECTED AMPLITUDE CONTROL LOOP
24
Patent #:
7356743
Issue Dt:
04/08/2008
Application #:
11256829
Filing Dt:
10/24/2005
Publication #:
US20070091702
Pub Dt:
04/26/2007
Title:
RRAM CONTROLLER BUILT IN SELF TEST MEMORY
25
Patent #:
7739471
Issue Dt:
06/15/2010
Application #:
11256830
Filing Dt:
10/24/2005
Publication #:
US20070091105
Pub Dt:
04/26/2007
Title:
HIGH PERFORMANCE TILING FOR RRAM MEMORY
26
Patent #:
7380223
Issue Dt:
05/27/2008
Application #:
11257206
Filing Dt:
10/24/2005
Publication #:
US20070094621
Pub Dt:
04/26/2007
Title:
METHOD AND SYSTEM FOR CONVERTING NETLIST OF INTEGRATED CIRCUIT BETWEEN LIBRARIES
27
Patent #:
7404166
Issue Dt:
07/22/2008
Application #:
11257289
Filing Dt:
10/24/2005
Publication #:
US20070094633
Pub Dt:
04/26/2007
Title:
METHOD AND SYSTEM FOR MAPPING NETLIST OF INTEGRATED CIRCUIT TO DESIGN
28
Patent #:
7493519
Issue Dt:
02/17/2009
Application #:
11257470
Filing Dt:
10/24/2005
Publication #:
US20070094534
Pub Dt:
04/26/2007
Title:
RRAM MEMORY ERROR EMULATION
29
Patent #:
7580331
Issue Dt:
08/25/2009
Application #:
11257606
Filing Dt:
10/25/2005
Publication #:
US20070091741
Pub Dt:
04/26/2007
Title:
CENTER ERROR MECHANICAL CENTER ADJUSTMENT
30
Patent #:
7582938
Issue Dt:
09/01/2009
Application #:
11258253
Filing Dt:
10/25/2005
Publication #:
US20060033163
Pub Dt:
02/16/2006
Title:
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
31
Patent #:
7401313
Issue Dt:
07/15/2008
Application #:
11258738
Filing Dt:
10/26/2005
Publication #:
US20070094631
Pub Dt:
04/26/2007
Title:
METHOD AND APPARATUS FOR CONTROLLING CONGESTION DURING INTEGRATED CIRCUIT DESIGN RESYNTHESIS
32
Patent #:
7193905
Issue Dt:
03/20/2007
Application #:
11259228
Filing Dt:
10/25/2005
Title:
RRAM FLIPFLOP RCELL MEMORY GENERATOR
33
Patent #:
7580330
Issue Dt:
08/25/2009
Application #:
11259300
Filing Dt:
10/26/2005
Publication #:
US20070091742
Pub Dt:
04/26/2007
Title:
CE TO RRO CANCELLATION FOR SLED CONTROL
34
Patent #:
7595743
Issue Dt:
09/29/2009
Application #:
11259596
Filing Dt:
10/26/2005
Title:
SYSTEM AND METHOD FOR REDUCING STORAGE REQUIREMENTS FOR CONTENT ADAPTIVE BINARY ARITHMETIC CODING
35
Patent #:
7196420
Issue Dt:
03/27/2007
Application #:
11259965
Filing Dt:
10/26/2005
Title:
METHOD AND STRUCTURE FOR CREATING ULTRA LOW RESISTANCE DAMASCENE COPPER WIRING
36
Patent #:
7405476
Issue Dt:
07/29/2008
Application #:
11260334
Filing Dt:
10/27/2005
Publication #:
US20070096303
Pub Dt:
05/03/2007
Title:
ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
37
Patent #:
7589594
Issue Dt:
09/15/2009
Application #:
11260442
Filing Dt:
10/27/2005
Publication #:
US20070099581
Pub Dt:
05/03/2007
Title:
VARIABLE LOOP BANDWIDTH PHASE LOCKED LOOP
38
Patent #:
7472358
Issue Dt:
12/30/2008
Application #:
11260517
Filing Dt:
10/27/2005
Publication #:
US20070169009
Pub Dt:
07/19/2007
Title:
METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART
39
Patent #:
7362151
Issue Dt:
04/22/2008
Application #:
11260805
Filing Dt:
10/27/2005
Publication #:
US20070096783
Pub Dt:
05/03/2007
Title:
TIMING CIRCUITS WITH IMPROVED POWER SUPPLY JITTER ISOLATION TECHNICAL BACKGROUND
40
Patent #:
7619294
Issue Dt:
11/17/2009
Application #:
11262173
Filing Dt:
10/28/2005
Title:
SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
41
Patent #:
7783038
Issue Dt:
08/24/2010
Application #:
11262444
Filing Dt:
10/28/2005
Publication #:
US20070098157
Pub Dt:
05/03/2007
Title:
USING CODE AS KEYS FOR COPY PROTECTION
42
Patent #:
7401171
Issue Dt:
07/15/2008
Application #:
11262679
Filing Dt:
10/31/2005
Publication #:
US20070100847
Pub Dt:
05/03/2007
Title:
METHODS AND STRUCTURE FOR SAS EXPANDER INITIATING COMMUNICATION TO A SAS INITIATOR TO IDENTIFY CHANGES IN THE SAS DOMAIN
43
Patent #:
7389196
Issue Dt:
06/17/2008
Application #:
11262864
Filing Dt:
10/31/2005
Publication #:
US20070100574
Pub Dt:
05/03/2007
Title:
METHOD AND SYSTEM FOR VALIDATING PCI/PCI-X ADAPTERS
44
Patent #:
7477850
Issue Dt:
01/13/2009
Application #:
11263285
Filing Dt:
10/31/2005
Publication #:
US20070098412
Pub Dt:
05/03/2007
Title:
OPTICAL SIGNAL JITTER REDUCTION VIA ELECTRICAL EQUALIZATION IN OPTICAL TRANSMISSION SYSTEMS
45
Patent #:
8031706
Issue Dt:
10/04/2011
Application #:
11263300
Filing Dt:
10/31/2005
Publication #:
US20070115984
Pub Dt:
05/24/2007
Title:
CIRCUITRY FOR DETERMINING NETWORK OPERATIONS IN A NETWORK DEVICE BY ADDRESSING LOOKUP TABLES WITH CONTENTS OF PROTOCOL HEADER FIELDS
46
Patent #:
7376780
Issue Dt:
05/20/2008
Application #:
11263514
Filing Dt:
10/31/2005
Publication #:
US20070101043
Pub Dt:
05/03/2007
Title:
PROTOCOL CONVERTER TO ACCESS AHB SLAVE DEVICES USING THE MDIO PROTOCOL
47
Patent #:
7571397
Issue Dt:
08/04/2009
Application #:
11265040
Filing Dt:
11/02/2005
Publication #:
US20070099313
Pub Dt:
05/03/2007
Title:
METHOD OF DESIGN BASED PROCESS CONTROL OPTIMIZATION
48
Patent #:
7635888
Issue Dt:
12/22/2009
Application #:
11265062
Filing Dt:
11/02/2005
Publication #:
US20060054994
Pub Dt:
03/16/2006
Title:
INTERDIGITADED CAPACITORS
49
Patent #:
7716543
Issue Dt:
05/11/2010
Application #:
11266056
Filing Dt:
11/02/2005
Publication #:
US20070101200
Pub Dt:
05/03/2007
Title:
METHODS AND SYSTEMS FOR ELIMINATING TEST SYSTEM REBOOTS BETWEEN FUNCTIONAL TESTS OF HOST ADAPTER BOARDS
50
Patent #:
7640396
Issue Dt:
12/29/2009
Application #:
11266132
Filing Dt:
11/02/2005
Publication #:
US20070101062
Pub Dt:
05/03/2007
Title:
ALL PURPOSE PROCESSOR IMPLEMENTATION TO SUPPORT DIFFERENT TYPES OF CACHE MEMORY ARCHITECTURES
51
Patent #:
7327011
Issue Dt:
02/05/2008
Application #:
11266133
Filing Dt:
11/02/2005
Publication #:
US20070096252
Pub Dt:
05/03/2007
Title:
MULTI-SURFACED PLATE-TO-PLATE CAPACITOR AND METHOD OF FORMING SAME
52
Patent #:
7467359
Issue Dt:
12/16/2008
Application #:
11266687
Filing Dt:
11/03/2005
Publication #:
US20060067436
Pub Dt:
03/30/2006
Title:
DECODER USING A MEMORY FOR STORING STATE METRICS INPLEMENTING A DECODER TRELLIS
53
Patent #:
7529968
Issue Dt:
05/05/2009
Application #:
11267999
Filing Dt:
11/07/2005
Publication #:
US20070168701
Pub Dt:
07/19/2007
Title:
STORING RAID CONFIGURATION DATA WITHIN A BIOS IMAGE
54
Patent #:
8076779
Issue Dt:
12/13/2011
Application #:
11269275
Filing Dt:
11/08/2005
Publication #:
US20070102812
Pub Dt:
05/10/2007
Title:
REDUCTION OF MACRO LEVEL STRESSES IN COPPER/LOW-K WAFERS
55
Patent #:
7328382
Issue Dt:
02/05/2008
Application #:
11270077
Filing Dt:
11/09/2005
Publication #:
US20060161804
Pub Dt:
07/20/2006
Title:
MEMORY BISR CONTROLLER ARCHITECTURE
56
Patent #:
7325216
Issue Dt:
01/29/2008
Application #:
11271991
Filing Dt:
11/09/2005
Publication #:
US20070104029
Pub Dt:
05/10/2007
Title:
METHOD AND COMPUTER PROGRAM FOR SPREADING TRACE SEGMENTS IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
57
Patent #:
8401070
Issue Dt:
03/19/2013
Application #:
11272300
Filing Dt:
11/10/2005
Publication #:
US20070104273
Pub Dt:
05/10/2007
Title:
METHOD FOR ROBUST INVERSE TELECINE
58
Patent #:
7551232
Issue Dt:
06/23/2009
Application #:
11273304
Filing Dt:
11/14/2005
Publication #:
US20070109448
Pub Dt:
05/17/2007
Title:
NOISE ADAPTIVE 3D COMPOSITE NOISE REDUCTION
59
Patent #:
7583571
Issue Dt:
09/01/2009
Application #:
11273518
Filing Dt:
11/14/2005
Publication #:
US20070109937
Pub Dt:
05/17/2007
Title:
WRITE BASED POWER ADAPTIVE CONTROL SYSTEM
60
Patent #:
7461214
Issue Dt:
12/02/2008
Application #:
11273750
Filing Dt:
11/15/2005
Publication #:
US20070113023
Pub Dt:
05/17/2007
Title:
METHOD AND SYSTEM FOR ACCESSING A SINGLE PORT MEMORY
61
Patent #:
7332924
Issue Dt:
02/19/2008
Application #:
11273857
Filing Dt:
11/15/2005
Publication #:
US20070109005
Pub Dt:
05/17/2007
Title:
EMBEDDED TEST CIRCUITRY AND A METHOD FOR TESTING A SEMICONDUCTOR DEVICE FOR BREAKDOWN, WEAROUT OR FAILURE
62
Patent #:
7545900
Issue Dt:
06/09/2009
Application #:
11273940
Filing Dt:
11/15/2005
Publication #:
US20070110206
Pub Dt:
05/17/2007
Title:
LOW JITTER AND/OR FAST LOCK-IN CLOCK RECOVERY CIRCUIT
63
Patent #:
7180011
Issue Dt:
02/20/2007
Application #:
11276938
Filing Dt:
03/17/2006
Title:
DEVICE FOR MINIMIZING DIFFERENTIAL PAIR LENGTH MISMATCH AND IMPEDANCE DISCONTINUITIES IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
64
Patent #:
8049340
Issue Dt:
11/01/2011
Application #:
11277188
Filing Dt:
03/22/2006
Publication #:
US20070222084
Pub Dt:
09/27/2007
Title:
DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
65
Patent #:
7358902
Issue Dt:
04/15/2008
Application #:
11279520
Filing Dt:
04/12/2006
Publication #:
US20060181464
Pub Dt:
08/17/2006
Title:
DUAL-BAND ANTENNA FOR A WIRELESS LOCAL AREA NETWORK DEVICE
66
Patent #:
7424687
Issue Dt:
09/09/2008
Application #:
11280110
Filing Dt:
11/16/2005
Publication #:
US20070113212
Pub Dt:
05/17/2007
Title:
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT
67
Patent #:
7764614
Issue Dt:
07/27/2010
Application #:
11280590
Filing Dt:
11/15/2005
Publication #:
US20070110086
Pub Dt:
05/17/2007
Title:
MULTI-MODE MANAGEMENT OF A SERIAL COMMUNICATION LINK
68
Patent #:
7496474
Issue Dt:
02/24/2009
Application #:
11280639
Filing Dt:
11/16/2005
Publication #:
US20070112544
Pub Dt:
05/17/2007
Title:
DYNAMIC ON-CHIP LOGIC ANALYSIS
69
Patent #:
7389484
Issue Dt:
06/17/2008
Application #:
11280879
Filing Dt:
11/16/2005
Publication #:
US20070108961
Pub Dt:
05/17/2007
Title:
METHOD AND APPARATUS FOR TILING MEMORIES IN INTEGRATED CIRCUIT LAYOUT
70
Patent #:
7783253
Issue Dt:
08/24/2010
Application #:
11281130
Filing Dt:
11/17/2005
Publication #:
US20070109092
Pub Dt:
05/17/2007
Title:
SECURITY SYSTEM AND METHOD FOR PROTECTING ELECTRONIC DEVICES
71
Patent #:
7539091
Issue Dt:
05/26/2009
Application #:
11282881
Filing Dt:
11/18/2005
Publication #:
US20070115792
Pub Dt:
05/24/2007
Title:
DIFFERENTIAL PUSH-PULL GAIN CONTROLLING METHOD AND APPARATUS TO REDUCE THE EFFECTS OF ROTATIONAL ECCENTRICITY
72
Patent #:
7205673
Issue Dt:
04/17/2007
Application #:
11283044
Filing Dt:
11/18/2005
Title:
REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES BY DOPING ALUMINUM USED IN BOND PADS DURING CU/LOW-K BEOL PROCESSING
73
Patent #:
8552560
Issue Dt:
10/08/2013
Application #:
11283219
Filing Dt:
11/18/2005
Publication #:
US20070114667
Pub Dt:
05/24/2007
Title:
ALTERNATE PAD STRUCTURES/PASSIVATION INEGRATION SCHEMES TO REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES DURING CU/LOW-K BEOL PROCESSING
74
Patent #:
7298036
Issue Dt:
11/20/2007
Application #:
11283340
Filing Dt:
11/18/2005
Publication #:
US20070114644
Pub Dt:
05/24/2007
Title:
SCALING OF FUNCTIONAL ASSIGNMENTS IN PACKAGES
75
Patent #:
NONE
Issue Dt:
Application #:
11284864
Filing Dt:
11/22/2005
Publication #:
US20070150627
Pub Dt:
06/28/2007
Title:
Endian mapping engine, method of endian mapping and a processing system employing the engine and the method
76
Patent #:
7793010
Issue Dt:
09/07/2010
Application #:
11285243
Filing Dt:
11/22/2005
Publication #:
US20070130407
Pub Dt:
06/07/2007
Title:
BUS SYSTEM WITH MULTIPLE MODES OF OPERATION
77
Patent #:
7248079
Issue Dt:
07/24/2007
Application #:
11285800
Filing Dt:
11/23/2005
Publication #:
US20070115030
Pub Dt:
05/24/2007
Title:
DIFFERENTIAL BUFFER CIRCUIT WITH REDUCED OUTPUT COMMON MODE VARIATION
78
Patent #:
7494842
Issue Dt:
02/24/2009
Application #:
11286546
Filing Dt:
11/23/2005
Publication #:
US20070114613
Pub Dt:
05/24/2007
Title:
PROGRAMMABLE NANOTUBE INTERCONNECT
79
Patent #:
7655548
Issue Dt:
02/02/2010
Application #:
11286557
Filing Dt:
11/23/2005
Publication #:
US20070114517
Pub Dt:
05/24/2007
Title:
PROGRAMMABLE POWER MANAGEMENT USING A NANOTUBE STRUCTURE
80
Patent #:
7847285
Issue Dt:
12/07/2010
Application #:
11286558
Filing Dt:
11/23/2005
Publication #:
US20070125999
Pub Dt:
06/07/2007
Title:
CONFIGURABLE POWER SEGMENTATION USING A NANOTUBE STRUCTURE
81
Patent #:
7379281
Issue Dt:
05/27/2008
Application #:
11287615
Filing Dt:
11/28/2005
Publication #:
US20070121262
Pub Dt:
05/31/2007
Title:
BIAS FOR ELECTROSTATIC DISCHARGE PROTECTION
82
Patent #:
7254761
Issue Dt:
08/07/2007
Application #:
11287927
Filing Dt:
11/28/2005
Publication #:
US20070122922
Pub Dt:
05/31/2007
Title:
PLATFORM ASIC RELIABILITY
83
Patent #:
8311132
Issue Dt:
11/13/2012
Application #:
11289943
Filing Dt:
11/30/2005
Publication #:
US20070121739
Pub Dt:
05/31/2007
Title:
PILOT-ASSISTED DOPPLER FREQUENCY ESTIMATION
84
Patent #:
7531442
Issue Dt:
05/12/2009
Application #:
11290087
Filing Dt:
11/30/2005
Publication #:
US20070123024
Pub Dt:
05/31/2007
Title:
ELIMINATE IMC CRACKING IN POST WIREBONDED DIES: MACRO LEVEL STRESS REDUCTION BY MODIFYING DIELECTRIC/METAL FILM STACK IN BE LAYERS DURING CU/LOW-K PROCESSING
85
Patent #:
7698477
Issue Dt:
04/13/2010
Application #:
11290096
Filing Dt:
11/30/2005
Publication #:
US20070121495
Pub Dt:
05/31/2007
Title:
METHOD AND APPARATUS FOR MANAGING FLOW CONTROL IN PCI EXPRESS TRANSACTION LAYER
86
Patent #:
NONE
Issue Dt:
Application #:
11290178
Filing Dt:
11/30/2005
Publication #:
US20070124628
Pub Dt:
05/31/2007
Title:
Methods of memory bitmap verification for finished product
87
Patent #:
7496861
Issue Dt:
02/24/2009
Application #:
11290186
Filing Dt:
11/30/2005
Publication #:
US20070124716
Pub Dt:
05/31/2007
Title:
METHOD FOR GENERALIZING DESIGN ATTRIBUTES IN A DESIGN CAPTURE ENVIRONMENT
88
Patent #:
7701508
Issue Dt:
04/20/2010
Application #:
11290194
Filing Dt:
11/30/2005
Publication #:
US20070121001
Pub Dt:
05/31/2007
Title:
ACCURATE MOTION DETECTION FOR THE COMBINATION OF MOTION ADAPTIVE AND MOTION COMPENSATION DE-INTERLACING APPLICATIONS
89
Patent #:
7570978
Issue Dt:
08/04/2009
Application #:
11291937
Filing Dt:
12/01/2005
Publication #:
US20070129121
Pub Dt:
06/07/2007
Title:
APPARATUS AND METHOD FOR PREVENTING AN UNINTENTIONAL ACTIVATION OF A MOBILE COMMUNICATION DEVICE
90
Patent #:
8243804
Issue Dt:
08/14/2012
Application #:
11292198
Filing Dt:
12/01/2005
Publication #:
US20070127573
Pub Dt:
06/07/2007
Title:
HIERARCHICAL MOTION ESTIMATION FOR IMAGES WITH VARYING HORIZONTAL AND/OR VERTICAL DIMENSIONS
91
Patent #:
7813429
Issue Dt:
10/12/2010
Application #:
11293404
Filing Dt:
12/02/2005
Publication #:
US20060083311
Pub Dt:
04/20/2006
Title:
SYSTEM AND METHOD FOR SEGMENTATION OF MACROBLOCKS
92
Patent #:
7721143
Issue Dt:
05/18/2010
Application #:
11295344
Filing Dt:
12/06/2005
Publication #:
US20070168706
Pub Dt:
07/19/2007
Title:
METHOD FOR REDUCING REBUILD TIME ON A RAID DEVICE
93
Patent #:
7406669
Issue Dt:
07/29/2008
Application #:
11295351
Filing Dt:
12/06/2005
Publication #:
US20070130486
Pub Dt:
06/07/2007
Title:
TIMING CONSTRAINTS METHODOLOGY FOR ENABLING CLOCK RECONVERGENCE PESSIMISM REMOVAL IN EXTRACTED TIMING MODELS
94
Patent #:
7358802
Issue Dt:
04/15/2008
Application #:
11295877
Filing Dt:
12/07/2005
Publication #:
US20070126499
Pub Dt:
06/07/2007
Title:
MULTI-PHASE TECHNIQUES FOR TUNING AND/OR MEASURING OPERATIONS OF AN AMPLIFIER
95
Patent #:
7657754
Issue Dt:
02/02/2010
Application #:
11297484
Filing Dt:
12/08/2005
Publication #:
US20070136576
Pub Dt:
06/14/2007
Title:
METHODS AND APPARATUS FOR THE SECURE HANDLING OF DATA IN A MICROCONTROLLER
96
Patent #:
7504728
Issue Dt:
03/17/2009
Application #:
11298030
Filing Dt:
12/09/2005
Publication #:
US20070134903
Pub Dt:
06/14/2007
Title:
INTEGRATED CIRCUIT HAVING BOND PAD WITH IMPROVED THERMAL AND MECHANICAL PROPERTIES
97
Patent #:
7584442
Issue Dt:
09/01/2009
Application #:
11298894
Filing Dt:
12/09/2005
Publication #:
US20070136704
Pub Dt:
06/14/2007
Title:
METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
98
Patent #:
7624330
Issue Dt:
11/24/2009
Application #:
11299506
Filing Dt:
12/12/2005
Publication #:
US20070136641
Pub Dt:
06/14/2007
Title:
UNIFIED MEMORY ARCHITECTURE FOR RECORDING APPLICATIONS
99
Patent #:
7912069
Issue Dt:
03/22/2011
Application #:
11299645
Filing Dt:
12/12/2005
Publication #:
US20060088040
Pub Dt:
04/27/2006
Title:
VIRTUAL SEGMENTATION SYSTEM AND METHOD OF OPERATION THEREOF
100
Patent #:
7539798
Issue Dt:
05/26/2009
Application #:
11300012
Filing Dt:
12/14/2005
Publication #:
US20070136521
Pub Dt:
06/14/2007
Title:
MITIGATING PERFORMANCE DEGRADATION CAUSED BY A SATA DRIVE ATTACHED TO A SAS DOMAIN
Assignor
1
DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Exec Dt:
02/01/2016
Assignees
1
LSI CORPORATION
1320 RIDDER PARK DRIVE
SAN JOSE, CALIFORNIA 95131
2
AGERE SYSTEMS LLC
1110 AMERICAN PARKWAY NE
ALLENTOWN, PENNSYLVANIA 18109
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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