Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 035842/0043 | |
| Pages: | 4 |
| | Recorded: | 06/16/2015 | | |
| Attorney Dkt #: | 1012-1052 / 2015P50216 US |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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11/14/2017
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Application #:
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14710989
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Filing Dt:
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05/13/2015
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Publication #:
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Pub Dt:
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11/17/2016
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Title:
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METHOD AND CIRCUIT FOR REDUCING COLLECTOR-EMITTER VOLTAGE OVERSHOOT IN AN INSULATED GATE BIPOLAR TRANSISTOR
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Assignee
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| SIEMENSSTRASSE 2 |
| VILLACH, AUSTRIA 9500 |
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Correspondence name and address
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MURPHY, BILAK & HOMILLER/INFINEON TECHNO
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1255 CRESCENT GREEN
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SUITE 200
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CARY, NC 27518
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