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Reel/Frame:035220/0048   Pages: 83
Recorded: 03/17/2015
Attorney Dkt #:40767.149
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 100
Page 1 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
11/12/1996
Application #:
08396994
Filing Dt:
03/01/1995
Title:
CONTINUOUS TIME PROGRAMMABLE ANALOG BLOCK ARCHITECTURE
2
Patent #:
Issue Dt:
04/01/1997
Application #:
08403352
Filing Dt:
03/14/1995
Title:
ACTIVE RESISTOR FOR STABILITY COMPENSATION
3
Patent #:
Issue Dt:
02/20/1996
Application #:
08403354
Filing Dt:
03/14/1995
Title:
LOW DISTORTION DIFFERENTIAL TRANSCONDUCTOR OUTPUT CURRENT MIRROR
4
Patent #:
Issue Dt:
04/23/1996
Application #:
08403359
Filing Dt:
03/14/1995
Title:
CMOS PROGRAMMABLE RESISTOR-BASED TRANSCONDUCTOR
5
Patent #:
Issue Dt:
09/23/1997
Application #:
08403595
Filing Dt:
03/14/1995
Title:
VBB REFERENCE FOR PUMPED SUBSTRATES
6
Patent #:
Issue Dt:
02/06/1996
Application #:
08423303
Filing Dt:
04/18/1995
Title:
CONSTANT DELAY INTERCONNECT FOR COUPLING CONFIGURABLE LOGIC BLOCKS
7
Patent #:
Issue Dt:
01/21/1997
Application #:
08427117
Filing Dt:
04/21/1995
Title:
CMOS MEMORY CELL WITH GATE OXIDE OF BOTH NMOS AND PMOS TRANSISTORS AS TUNNELING WINDOW FOR PROGRAM AND ERASE
8
Patent #:
Issue Dt:
02/13/1996
Application #:
08444306
Filing Dt:
05/18/1995
Title:
CASCODE ARRAY CELL PARTITIONING FOR A SENSE AMPLIFIER OF A PROGRAMMABLE LOGIC DEVICE
9
Patent #:
Issue Dt:
01/14/1997
Application #:
08447991
Filing Dt:
05/23/1995
Title:
COMPLETELY COMPLEMENTARY MOS MEMORY CELL WITH TUNNELING THROUGH THE NMOS AND PMOS TRANSISTORS DURING PROGRAM AND ERASE
10
Patent #:
Issue Dt:
05/26/1998
Application #:
08449384
Filing Dt:
05/23/1995
Title:
METHOD OF MAKING A SPACER BASED ANTIFUSE STRUCTURE FOR LOW CAPACITANCE AND HIGH RELIABILITY
11
Patent #:
Issue Dt:
10/29/1996
Application #:
08453184
Filing Dt:
05/30/1995
Title:
LEAD FRAME WITH NOISY AND QUIET V AND V LEADS SS DD
12
Patent #:
Issue Dt:
12/10/1996
Application #:
08453479
Filing Dt:
05/30/1995
Title:
GROUND BOUNCE ISOLATED OUTPUT BUFFER POLARITY CONTROL CIRCUIT WHICH MAY BE USED W3ITH A GROUND BOUNCE LIMITING BUFFER
13
Patent #:
Issue Dt:
04/15/1997
Application #:
08456946
Filing Dt:
06/01/1995
Title:
PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES
14
Patent #:
Issue Dt:
12/31/1996
Application #:
08458865
Filing Dt:
06/02/1995
Title:
MACROCELL AND CLOCK SIGNAL ALLOCATION CIRCUIT FOR A PROGRAMMABLE LOGIC DEVICE (PLD) ENABLING PLD RESOURCES TO PROVIDE MULTIPLE FUNCTIONS
15
Patent #:
Issue Dt:
10/06/1998
Application #:
08459230
Filing Dt:
06/02/1995
Title:
MULTI-TIERED HIERARCHICAL HIGH SPEED SWITCH MATRIX STRUCTURE FOR VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES
16
Patent #:
Issue Dt:
07/14/1998
Application #:
08459234
Filing Dt:
06/02/1995
Title:
PROGRAMMABLE UNIFORM SYMMETRICAL DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD
17
Patent #:
Issue Dt:
03/11/2003
Application #:
08459570
Filing Dt:
06/02/1995
Title:
PROGRAMMABLE OPTIMIZED-DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD
18
Patent #:
Issue Dt:
06/10/1997
Application #:
08459786
Filing Dt:
06/02/1995
Title:
P-TYPE FLIP-FLOP
19
Patent #:
Issue Dt:
05/28/1996
Application #:
08459960
Filing Dt:
06/02/1995
Title:
VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES WITH A MULTI-TIERED HIERARCHICAL SWITCH MATRIX AND OPTIMIZED FLIXIBLE LOGIC ALLOCATION
20
Patent #:
Issue Dt:
12/17/1996
Application #:
08461196
Filing Dt:
06/05/1995
Title:
ARRAY OF CONFIGURABLE LOGIC BLOCKS INCLUDING CASCADABLE LOOKUP TABLES
21
Patent #:
Issue Dt:
11/21/1995
Application #:
08462934
Filing Dt:
06/05/1995
Title:
ARRAY OF CONFIGURABLE LOGIC BLOCKS EACH INCLUDING A FIRST LOOKUP TABLE OUTPUT COUPLED TO SELECTIVELY REPLACE AN OUTPUT OF SECOND LOOKUP WITH AN ALTERNATE FUNCTION OUTPUT
22
Patent #:
Issue Dt:
05/19/1998
Application #:
08466438
Filing Dt:
06/06/1995
Title:
LOW POWER CMOS ARRAY CELL FOR A PLD WITH PROGRAM AND ERASE USING CONTROLLED AVALANCHE INJECTION
23
Patent #:
Issue Dt:
01/14/1997
Application #:
08473620
Filing Dt:
06/07/1995
Title:
SYSTEM FOR SYNTHESIZING FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS FROM HIGH LEVEL CIRCUIT DESCRIPTIONS
24
Patent #:
Issue Dt:
03/18/1997
Application #:
08474629
Filing Dt:
06/06/1995
Title:
AN I/O MACROCELL FOR A PROGRAMMABLE LOGIC DEVICE
25
Patent #:
Issue Dt:
09/22/1998
Application #:
08474635
Filing Dt:
06/06/1995
Title:
FLEXIBLE SYNCHRONOUS/ASYNCHRONOUS CELL STRUCTURE FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
26
Patent #:
Issue Dt:
02/09/1999
Application #:
08479872
Filing Dt:
06/06/1995
Title:
A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
27
Patent #:
Issue Dt:
04/01/1997
Application #:
08483623
Filing Dt:
06/07/1995
Title:
MULTIPLE ARRAY PROGRAMMABLE LOGIC DEVICE WITH A PLURALITY OF PROGRAMMABLE SWITCH MATRICES
28
Patent #:
Issue Dt:
01/14/1997
Application #:
08486174
Filing Dt:
06/06/1995
Title:
A FLEXIBLE BLOCK CLOCK GENERATION CIRCUIT FOR PROVIDING CLOCK SIGNALS TO CLOCKED ELEMENTS IN A MULTIPLE ARRAY HIGH DENSITY PROGRAMMABLE LOGIC DIVICE
29
Patent #:
Issue Dt:
06/09/1998
Application #:
08486178
Filing Dt:
06/06/1995
Title:
FAMILY OF MULTIPLE SEGMENTED PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED CENTRALIZED SWITCH MATRIX
30
Patent #:
Issue Dt:
06/11/1996
Application #:
08492604
Filing Dt:
06/20/1995
Title:
METHOD AND APPARATUS FOR CONVERTING FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS INTO MAS-PROGRAMMABLE LOGIC CELL IMPLEMENTATIONS
31
Patent #:
Issue Dt:
10/21/1997
Application #:
08493640
Filing Dt:
06/22/1995
Title:
ISOLATION USING SELF-ALIGNED TRENCH FORMATION AND CONVENTIONAL LOCOS
32
Patent #:
Issue Dt:
10/15/1996
Application #:
08494271
Filing Dt:
06/23/1995
Title:
VOLTAGE RANGE TOLERANT CMOS OUTPUT BUFFER WITH REDUCED INPUT CAPACITANCE
33
Patent #:
Issue Dt:
04/21/1998
Application #:
08497992
Filing Dt:
07/03/1995
Title:
NON-VOLATILE MEMORY CELLS USING ONLY POSITIVE CHARGE TO STORE DATA
34
Patent #:
Issue Dt:
12/23/1997
Application #:
08500295
Filing Dt:
07/10/1995
Title:
METHOD FOR SCREENING NON-VOLATILE MEMORY AND PROGRAMMABLE LOGIC DEVICES
35
Patent #:
Issue Dt:
02/18/1997
Application #:
08501230
Filing Dt:
07/11/1995
Title:
FIELD IMPLANT FOR SEMICONDUCTOR DEVICE
36
Patent #:
Issue Dt:
06/03/1997
Application #:
08505837
Filing Dt:
07/21/1995
Title:
METHOD FOR SIMULTANEOUS PROGRAMMING OF IN-SYSTEM PROGRAMMABLE INTEGRATED CIRCUITS
37
Patent #:
Issue Dt:
10/29/1996
Application #:
08507893
Filing Dt:
07/27/1995
Title:
PROGRAMMABLE FUNCTION UNIT AS PARALLEL MULTIPLIER CELL
38
Patent #:
Issue Dt:
09/24/1996
Application #:
08507957
Filing Dt:
07/27/1995
Title:
FIELD PROGRAMMABLE GATE ARRAY WITH MULTI-PORT RAM
39
Patent #:
Issue Dt:
12/03/1996
Application #:
08528030
Filing Dt:
09/14/1995
Title:
INTERLACED LAYOUT CONFIGURATION FOR DIFFERENTIAL PAIRS OF INTERCONNECT LINES
40
Patent #:
Issue Dt:
06/18/1996
Application #:
08535362
Filing Dt:
09/28/1995
Title:
LOW-SKEW SIGNAL ROUTING IN A PROGRAMMABLE ARRAY
41
Patent #:
Issue Dt:
03/25/1997
Application #:
08551974
Filing Dt:
11/02/1995
Title:
CONTROL GATE-ADDRESSED CMOS NON-VOLATILE CELL THAT PROGRAMS THROUGH GATES OF CMOS TRANSISTORS
42
Patent #:
Issue Dt:
12/24/1996
Application #:
08554092
Filing Dt:
11/06/1995
Title:
CMOS EEPROM CELL WITH TUNNELING WINDOW IN THE READ PATH
43
Patent #:
Issue Dt:
09/09/1997
Application #:
08560038
Filing Dt:
11/17/1995
Title:
MEMORY CELL FOR A PROGRAMMABLE LOGIC DEVICE (PLD) AVOIDING PUMPING PROGRAMMING VOLTAGE ABOVE AN NMOS THRESHOLD
44
Patent #:
Issue Dt:
12/24/1996
Application #:
08560933
Filing Dt:
11/20/1995
Title:
ARRAY OF CONFIGURABLE LOGIC BLOCKS EACH INCLUDING A LOOKUP TABLE HAVING INPUTS COUPLED TOA FIRST MULTIPLEXER AND HAVING OUTPUTS TO A SECOND MULTIPLEXER
45
Patent #:
Issue Dt:
09/30/1997
Application #:
08561306
Filing Dt:
11/21/1995
Title:
METHOD OF FORMING MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE
46
Patent #:
Issue Dt:
09/15/1998
Application #:
08573622
Filing Dt:
12/18/1995
Title:
MICROPPROCESSOR SYSTEM WITH PROCESS IDENTIFICATION TAG ENTRIES TO REDUCE CACHE FLUSHING AFTER A CONTEXT SWITCH
47
Patent #:
Issue Dt:
04/14/1998
Application #:
08574776
Filing Dt:
12/19/1995
Title:
DECONVOLUTION INPUT BUFFER COMPENSATING FOR CAPACITANCE OF A SWITCH MATRIX OF A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
48
Patent #:
Issue Dt:
02/17/1998
Application #:
08575852
Filing Dt:
12/20/1995
Title:
LOCK GENERATOR CIRCUIT FOR USE WITH A DUAL EDGE REGISTER THAT PROVIDES A SEPARATE ENABLE FOR EACH EDGE OF AN INPUT CLOCK SIGNAL
49
Patent #:
Issue Dt:
04/07/1998
Application #:
08575898
Filing Dt:
12/20/1995
Title:
CAPACITANCE ELIMINATION CIRCUIT WHICH PROVIDES CURRENT TO A NODE IN A CIRCUIT TO ELIMINATE THE EFFECT OF PARASITIC CAPACITANCE AT THE NODE
50
Patent #:
Issue Dt:
01/28/1997
Application #:
08596679
Filing Dt:
02/05/1996
Title:
ARRAY OF CONFIGURABLE LOGIC BLOCKS INCLUDING NETWORK MEANS FOR BROADCASTING CLOCK SIGNALS TO DIFFERENT PLURALITIES OF LOGIC BLOCKS
51
Patent #:
Issue Dt:
04/22/1997
Application #:
08606702
Filing Dt:
02/26/1996
Title:
FIELD PROGRAMMABLE GATE ARRAY WITH WRITE-PORT ENABLED MEMORY
52
Patent #:
Issue Dt:
07/20/1999
Application #:
08614728
Filing Dt:
03/13/1996
Title:
SEGMENT DESCRIPTOR CACHE FOR A PROCESSOR
53
Patent #:
Issue Dt:
07/08/1997
Application #:
08625403
Filing Dt:
03/26/1996
Title:
CMOS MEMORY CELL WITH TUNNELING DURING PROGRAM AND ERASE THROUGH THE NMOS AND PMOS TRANSISTORS AND A PASS GATE SEPARATING THE NMOS AND PMOS TRANSISTORS
54
Patent #:
Issue Dt:
05/12/1998
Application #:
08632811
Filing Dt:
04/16/1996
Title:
PARALLEL PROGRAMMING OF IN-SYSTEM (ISP) PROGRAMMABLE DEVICES USING AN AUTOMATIC TESTER
55
Patent #:
Issue Dt:
09/09/1997
Application #:
08635184
Filing Dt:
04/25/1996
Title:
ACTIVE RESISTOR FOR STABILITY COMPENSATION
56
Patent #:
Issue Dt:
01/26/1999
Application #:
08643291
Filing Dt:
05/08/1996
Title:
METHOD AND APPARATUS FOR IN-SYSTEM PROGRAMMING OF A PROGRAMMABLE LOGIC DEVICE USING A TWO-WIRE INTERFACE
57
Patent #:
Issue Dt:
05/05/1998
Application #:
08643807
Filing Dt:
05/06/1996
Title:
ARRAY CELL CIRCUIT WITH SPLIT READ/WRITE LINE
58
Patent #:
Issue Dt:
08/04/1998
Application #:
08653186
Filing Dt:
05/24/1996
Title:
A METHOD FOR PROVIDING A PLURALITY OF HIERARCHICAL SIGNAL PATHS IN A VERY HIGH-DENSITY PROGRAMMABLE LOGIC DEVICE
59
Patent #:
Issue Dt:
03/03/1998
Application #:
08659279
Filing Dt:
06/06/1996
Title:
FIELD PROGRAMMABLE GATE ARRAY (FPGA) WITH INTERCONNECT ENCODING
60
Patent #:
Issue Dt:
09/15/1998
Application #:
08659941
Filing Dt:
06/07/1996
Title:
FIELD PROGRAMMABLE GATE ARRAY (FPGA) HAVING AN IMPROVED CONFIGURATION MEMORY AND LOOK UP TABLE
61
Patent #:
Issue Dt:
11/03/1998
Application #:
08664190
Filing Dt:
06/10/1996
Title:
SIMPLIFIED MASKING PROCESS FOR PROGRAMMABLE LOGIC DEVICE MANUFACTURE
62
Patent #:
Issue Dt:
06/02/1998
Application #:
08666193
Filing Dt:
06/19/1996
Title:
A CLOCK SIGNAL PROVIDING CIRCUIT WITH ENABLE AND A PULSE GENERATOR WITH ENABLE FOR USE IN A BLOCK CLOCK CIRCUIT OF A PROGRAMMABLE LOGIC DEVICE
63
Patent #:
Issue Dt:
08/18/1998
Application #:
08668141
Filing Dt:
06/21/1996
Title:
REFERENCE FOR CMOS MEMORY CELL HAVING PMOS AND NMOS TRANSISTORS WITH A COMMON FLOATING GATE
64
Patent #:
Issue Dt:
05/12/1998
Application #:
08668896
Filing Dt:
06/24/1996
Title:
PROGRAMMABLE LOGIC DEVICE WITH MULTI-LEVEL POWER CONTROL
65
Patent #:
Issue Dt:
10/06/1998
Application #:
08683373
Filing Dt:
07/18/1996
Title:
TEMPERATURE INSENSITIVE CURRENT SOURCE
66
Patent #:
Issue Dt:
03/31/1998
Application #:
08683685
Filing Dt:
07/18/1996
Title:
PROGRAMMABLE LOGIC DEVICE HAVING A SENSE AMPLIFIER WITH VIRTUAL GROUND
67
Patent #:
Issue Dt:
08/24/1999
Application #:
08689523
Filing Dt:
08/09/1996
Title:
AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE
68
Patent #:
Issue Dt:
09/01/1998
Application #:
08690768
Filing Dt:
08/01/1996
Title:
DEPLETION MODE PASS GATES WITH CONTROLLING DECODER AND NEGATIVE POWER SUPPLY FOR A PROGRAMMABLE LOGIC DEVICE
69
Patent #:
Issue Dt:
08/18/1998
Application #:
08696444
Filing Dt:
08/13/1996
Title:
METHOD FOR PROGRAMMING A PROGRAMMABLE LOGIC DEVICE IN AN AUTOMATIC TESTER
70
Patent #:
Issue Dt:
09/28/1999
Application #:
08699401
Filing Dt:
08/19/1996
Title:
OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE
71
Patent #:
Issue Dt:
04/14/1998
Application #:
08700616
Filing Dt:
08/16/1996
Title:
PROGRAMMABLE LOGIC DEVICE (PLD) HAVING DIRECT CONNECTIONS BETWEEN CONFIGURABLE LOGIC BLOCKS (CLBS) AND CONFIGURABLE INPUT/OUTPUT BLOCKS (IOBS)
72
Patent #:
Issue Dt:
09/28/1999
Application #:
08702846
Filing Dt:
08/26/1996
Title:
DECODER CIRCUIT WITH SHORT CHANNEL DEPLETION TRANSISTORS
73
Patent #:
Issue Dt:
01/19/1999
Application #:
08710445
Filing Dt:
09/17/1996
Title:
CONFIGURATION PIN EMULATION CIRCUIT FOR A FIELD PROGRAMMABLE GATE ARRAY
74
Patent #:
Issue Dt:
06/02/1998
Application #:
08723082
Filing Dt:
09/30/1996
Title:
PROGRAMMABLE HIGH SPEED ROUTING SWITCH
75
Patent #:
Issue Dt:
06/02/1998
Application #:
08726512
Filing Dt:
10/07/1996
Title:
A VPP ONLY SCALABLE EEPROM MEMORY CELL HAVING TRANSISTORS WITH THIN TUNNEL GATE OXIDE
76
Patent #:
Issue Dt:
11/23/1999
Application #:
08729117
Filing Dt:
10/11/1996
Title:
METHOD FOR TESTING FIELD PROGRAMMABLE GATE ARRAYS
77
Patent #:
Issue Dt:
09/08/1998
Application #:
08734888
Filing Dt:
10/22/1996
Title:
METHOD FOR USER-CONTROLLED I/O SWITCHING DURING IN-CIRCUIT PROGRAMMING OF CPLDS THROUGH THE IEEE 1149.1 TEST ACCESS PORT
78
Patent #:
Issue Dt:
09/22/1998
Application #:
08740948
Filing Dt:
11/05/1996
Title:
BLOCK CLOCK AND INITIALIZATION CIRCUIT FOR A COMPLEX HIGH DENSITY PLD
79
Patent #:
Issue Dt:
02/10/1998
Application #:
08745410
Filing Dt:
11/22/1996
Title:
OUTPUT BUFFER INCORPORATING SHARED INTERMEDIATE NODES
80
Patent #:
Issue Dt:
04/06/1999
Application #:
08748041
Filing Dt:
11/12/1996
Title:
FPGA-BASED PROCESSOR
81
Patent #:
Issue Dt:
02/22/2000
Application #:
08781882
Filing Dt:
01/10/1997
Title:
TIMED CIRCUIT SIMULATION IN HARDWARE USING FPGA'S
82
Patent #:
Issue Dt:
11/24/1998
Application #:
08785096
Filing Dt:
01/21/1997
Title:
METHOD OF CHARGING AND DISCHARGING FLOATING GATE TRANSISTORS TO REDUCE LEAKAGE CURRENT
83
Patent #:
Issue Dt:
05/18/1999
Application #:
08799153
Filing Dt:
02/14/1997
Title:
METHOD AND APPARATUS INCORPORATING NITROGEN SELECTIVELY FOR DIFFERENTIAL OXIDE GROWTH
84
Patent #:
Issue Dt:
03/23/1999
Application #:
08799235
Filing Dt:
02/14/1997
Title:
METHOD TO INCORPORATE, AND A DEVICE HAVING, OXIDE ENHANCEMENT DOPANTS USING GAS IMMERSION LASER DOPING (GILD) FOR SELECTIVELY GROWING AN OXIDE LAYER
85
Patent #:
Issue Dt:
02/20/2001
Application #:
08823953
Filing Dt:
03/25/1997
Title:
PROCESS FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE WITH HIGH DATA RETENTION INCLUDING SILICON NITRIDE ETCH STOP LAYER FORMED AT HIGH TEMPERATURE WITH LOW HYDROGEN ION CONCENTRATION
86
Patent #:
Issue Dt:
11/10/1998
Application #:
08827671
Filing Dt:
04/10/1997
Title:
APPLICATION SPECIFIC MODULES IN A PROGRAMMABLE LOGIC DEVICE
87
Patent #:
Issue Dt:
05/18/1999
Application #:
08828520
Filing Dt:
04/01/1997
Title:
MEMORY BITS USED TO COUPLE LOOK UP TABLE INPUTS TO FACILITATE INCREASED AVAILABILITY TO ROUTING RESOURCES PARTICULARLY FOR VARIABLE SIZED LOOK UP TABLES FOR A FIELD PROGRAMMABLE GATE ARRAY (FPGA)
88
Patent #:
Issue Dt:
12/01/1998
Application #:
08831372
Filing Dt:
04/23/2019
Title:
FAST VERIFY FOR CMOS MEMORY CELLS
89
Patent #:
Issue Dt:
03/07/2000
Application #:
08838487
Filing Dt:
04/07/1997
Title:
IN-SYSTEM PROGRAMMABLE INTERCONNECT CIRCUIT
90
Patent #:
Issue Dt:
07/11/2000
Application #:
08843150
Filing Dt:
04/26/1997
Title:
REDUCTION OF N-CHANNEL PARASITIC TRANSISTOR LEAKAGE BY USING LOW POWER/LOW PRESSURE PHOSPHOSILICATE GLASS
91
Patent #:
Issue Dt:
09/07/1999
Application #:
08856926
Filing Dt:
05/15/1997
Title:
DEVICES FOR SOURCING CONSTANT SUPPLY CURRENT FROM POWER SUPPLY IN SYSTEM WITH INTEGRATED CIRCUIT HAVING VARIABLE SUPPLY CURRENT REQUIREMENT
92
Patent #:
Issue Dt:
11/23/1999
Application #:
08859761
Filing Dt:
05/21/1997
Title:
PROCESS FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE WITH HIGH DATA RETENTION INCLUDING SILICON OXYNITRIDE ETCH STOP LAYER FORMED AT HIGH TEMPERATURE WITH LOW HYDROGEN ION CONCENTRATION
93
Patent #:
Issue Dt:
11/02/1999
Application #:
08871589
Filing Dt:
06/06/1997
Title:
NONVOLATILE MEMORY STRUCTURE FOR PROGRAMMABLE LOGIC DEVICES
94
Patent #:
Issue Dt:
02/22/2000
Application #:
08899428
Filing Dt:
07/24/1997
Title:
FPGA HAVING PREDICTABLE OPEN-DRAIN DRIVE MODE
95
Patent #:
Issue Dt:
06/06/2000
Application #:
08912763
Filing Dt:
08/18/1997
Title:
OUTPUT BUFFER FOR MAKING A 5.0 VOLT COMPATIBLE INPUT/OUTPUT IN A 2.5 VOLT SEMICONDUCTOR PROCESS
96
Patent #:
Issue Dt:
03/19/2002
Application #:
08931798
Filing Dt:
09/16/1997
Title:
CIRCUITRY TO PROVIDE FAST CARRY
97
Patent #:
Issue Dt:
02/01/2000
Application #:
08938550
Filing Dt:
09/26/1997
Title:
HYBRID PROGRAMMABLE GATE ARRAYS
98
Patent #:
Issue Dt:
12/29/1998
Application #:
08947888
Filing Dt:
10/09/1997
Title:
DATA RETENTION OF EEPROM CELL WITH SHALLOW TRENCH ISOLATION USING THICKER LINER OXIDE
99
Patent #:
Issue Dt:
08/01/2000
Application #:
08948306
Filing Dt:
10/09/1997
Title:
VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS
100
Patent #:
Issue Dt:
02/22/2000
Application #:
08949992
Filing Dt:
10/15/1997
Title:
PROGRAMMABLE CLOCK MANAGER FOR A PROGRAMMABLE LOGIC DEVICE THAT CAN GENERATE AT LEAST TWO DIFFERENT OUTPUT CLOCKS
Assignors
1
Exec Dt:
03/10/2015
2
Exec Dt:
03/10/2015
3
Exec Dt:
03/10/2015
4
Exec Dt:
03/10/2015
Assignee
1
520 MADISON AVENUE
NEW YORK, NEW YORK 10022
Correspondence name and address
PROSKAUER ROSE LLP
ONE INTERNATIONAL PLACE
BOSTON, MA 02110

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