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Patent #:
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Issue Dt:
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11/12/1996
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Application #:
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08396994
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Filing Dt:
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03/01/1995
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Title:
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CONTINUOUS TIME PROGRAMMABLE ANALOG BLOCK ARCHITECTURE
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Patent #:
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Issue Dt:
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04/01/1997
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Application #:
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08403352
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Filing Dt:
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03/14/1995
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Title:
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ACTIVE RESISTOR FOR STABILITY COMPENSATION
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Patent #:
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Issue Dt:
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02/20/1996
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Application #:
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08403354
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Filing Dt:
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03/14/1995
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Title:
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LOW DISTORTION DIFFERENTIAL TRANSCONDUCTOR OUTPUT CURRENT MIRROR
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Patent #:
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Issue Dt:
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04/23/1996
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Application #:
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08403359
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Filing Dt:
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03/14/1995
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Title:
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CMOS PROGRAMMABLE RESISTOR-BASED TRANSCONDUCTOR
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Patent #:
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Issue Dt:
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09/23/1997
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Application #:
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08403595
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Filing Dt:
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03/14/1995
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Title:
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VBB REFERENCE FOR PUMPED SUBSTRATES
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Patent #:
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Issue Dt:
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02/06/1996
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Application #:
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08423303
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Filing Dt:
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04/18/1995
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Title:
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CONSTANT DELAY INTERCONNECT FOR COUPLING CONFIGURABLE LOGIC BLOCKS
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Patent #:
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Issue Dt:
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01/21/1997
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Application #:
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08427117
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Filing Dt:
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04/21/1995
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Title:
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CMOS MEMORY CELL WITH GATE OXIDE OF BOTH NMOS AND PMOS TRANSISTORS AS TUNNELING WINDOW FOR PROGRAM AND ERASE
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Patent #:
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Issue Dt:
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02/13/1996
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Application #:
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08444306
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Filing Dt:
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05/18/1995
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Title:
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CASCODE ARRAY CELL PARTITIONING FOR A SENSE AMPLIFIER OF A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08447991
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Filing Dt:
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05/23/1995
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Title:
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COMPLETELY COMPLEMENTARY MOS MEMORY CELL WITH TUNNELING THROUGH THE NMOS AND PMOS TRANSISTORS DURING PROGRAM AND ERASE
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Patent #:
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Issue Dt:
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05/26/1998
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Application #:
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08449384
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Filing Dt:
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05/23/1995
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Title:
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METHOD OF MAKING A SPACER BASED ANTIFUSE STRUCTURE FOR LOW CAPACITANCE AND HIGH RELIABILITY
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Patent #:
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Issue Dt:
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10/29/1996
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Application #:
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08453184
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Filing Dt:
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05/30/1995
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Title:
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LEAD FRAME WITH NOISY AND QUIET V AND V LEADS SS DD
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Patent #:
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Issue Dt:
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12/10/1996
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Application #:
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08453479
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Filing Dt:
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05/30/1995
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Title:
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GROUND BOUNCE ISOLATED OUTPUT BUFFER POLARITY CONTROL CIRCUIT WHICH MAY BE USED W3ITH A GROUND BOUNCE LIMITING BUFFER
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Patent #:
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Issue Dt:
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04/15/1997
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Application #:
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08456946
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Filing Dt:
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06/01/1995
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES
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Patent #:
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Issue Dt:
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12/31/1996
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Application #:
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08458865
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Filing Dt:
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06/02/1995
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Title:
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MACROCELL AND CLOCK SIGNAL ALLOCATION CIRCUIT FOR A PROGRAMMABLE LOGIC DEVICE (PLD) ENABLING PLD RESOURCES TO PROVIDE MULTIPLE FUNCTIONS
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Patent #:
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Issue Dt:
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10/06/1998
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Application #:
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08459230
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Filing Dt:
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06/02/1995
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Title:
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MULTI-TIERED HIERARCHICAL HIGH SPEED SWITCH MATRIX STRUCTURE FOR VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08459234
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Filing Dt:
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06/02/1995
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Title:
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PROGRAMMABLE UNIFORM SYMMETRICAL DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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08459570
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Filing Dt:
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06/02/1995
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Title:
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PROGRAMMABLE OPTIMIZED-DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD
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Patent #:
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Issue Dt:
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06/10/1997
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Application #:
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08459786
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Filing Dt:
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06/02/1995
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Title:
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P-TYPE FLIP-FLOP
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Patent #:
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Issue Dt:
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05/28/1996
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Application #:
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08459960
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Filing Dt:
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06/02/1995
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Title:
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VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES WITH A MULTI-TIERED HIERARCHICAL SWITCH MATRIX AND OPTIMIZED FLIXIBLE LOGIC ALLOCATION
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Patent #:
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Issue Dt:
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12/17/1996
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Application #:
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08461196
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Filing Dt:
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06/05/1995
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Title:
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ARRAY OF CONFIGURABLE LOGIC BLOCKS INCLUDING CASCADABLE LOOKUP TABLES
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Patent #:
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Issue Dt:
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11/21/1995
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Application #:
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08462934
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Filing Dt:
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06/05/1995
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Title:
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ARRAY OF CONFIGURABLE LOGIC BLOCKS EACH INCLUDING A FIRST LOOKUP TABLE OUTPUT COUPLED TO SELECTIVELY REPLACE AN OUTPUT OF SECOND LOOKUP WITH AN ALTERNATE FUNCTION OUTPUT
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Patent #:
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Issue Dt:
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05/19/1998
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Application #:
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08466438
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Filing Dt:
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06/06/1995
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Title:
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LOW POWER CMOS ARRAY CELL FOR A PLD WITH PROGRAM AND ERASE USING CONTROLLED AVALANCHE INJECTION
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08473620
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Filing Dt:
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06/07/1995
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Title:
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SYSTEM FOR SYNTHESIZING FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS FROM HIGH LEVEL CIRCUIT DESCRIPTIONS
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Patent #:
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Issue Dt:
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03/18/1997
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Application #:
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08474629
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Filing Dt:
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06/06/1995
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Title:
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AN I/O MACROCELL FOR A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08474635
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Filing Dt:
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06/06/1995
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Title:
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FLEXIBLE SYNCHRONOUS/ASYNCHRONOUS CELL STRUCTURE FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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02/09/1999
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Application #:
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08479872
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Filing Dt:
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06/06/1995
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Title:
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A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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04/01/1997
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Application #:
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08483623
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Filing Dt:
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06/07/1995
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Title:
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MULTIPLE ARRAY PROGRAMMABLE LOGIC DEVICE WITH A PLURALITY OF PROGRAMMABLE SWITCH MATRICES
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08486174
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Filing Dt:
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06/06/1995
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Title:
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A FLEXIBLE BLOCK CLOCK GENERATION CIRCUIT FOR PROVIDING CLOCK SIGNALS TO CLOCKED ELEMENTS IN A MULTIPLE ARRAY HIGH DENSITY PROGRAMMABLE LOGIC DIVICE
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Patent #:
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Issue Dt:
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06/09/1998
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Application #:
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08486178
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Filing Dt:
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06/06/1995
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Title:
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FAMILY OF MULTIPLE SEGMENTED PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED CENTRALIZED SWITCH MATRIX
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Patent #:
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Issue Dt:
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06/11/1996
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Application #:
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08492604
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Filing Dt:
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06/20/1995
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Title:
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METHOD AND APPARATUS FOR CONVERTING FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS INTO MAS-PROGRAMMABLE LOGIC CELL IMPLEMENTATIONS
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Patent #:
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Issue Dt:
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10/21/1997
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Application #:
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08493640
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Filing Dt:
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06/22/1995
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Title:
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ISOLATION USING SELF-ALIGNED TRENCH FORMATION AND CONVENTIONAL LOCOS
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Patent #:
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Issue Dt:
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10/15/1996
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Application #:
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08494271
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Filing Dt:
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06/23/1995
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Title:
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VOLTAGE RANGE TOLERANT CMOS OUTPUT BUFFER WITH REDUCED INPUT CAPACITANCE
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08497992
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Filing Dt:
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07/03/1995
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Title:
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NON-VOLATILE MEMORY CELLS USING ONLY POSITIVE CHARGE TO STORE DATA
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Patent #:
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Issue Dt:
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12/23/1997
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Application #:
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08500295
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Filing Dt:
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07/10/1995
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Title:
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METHOD FOR SCREENING NON-VOLATILE MEMORY AND PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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02/18/1997
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Application #:
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08501230
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Filing Dt:
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07/11/1995
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Title:
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FIELD IMPLANT FOR SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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06/03/1997
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Application #:
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08505837
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Filing Dt:
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07/21/1995
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Title:
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METHOD FOR SIMULTANEOUS PROGRAMMING OF IN-SYSTEM PROGRAMMABLE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/29/1996
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Application #:
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08507893
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Filing Dt:
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07/27/1995
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Title:
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PROGRAMMABLE FUNCTION UNIT AS PARALLEL MULTIPLIER CELL
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08507957
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Filing Dt:
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07/27/1995
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Title:
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FIELD PROGRAMMABLE GATE ARRAY WITH MULTI-PORT RAM
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Patent #:
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|
Issue Dt:
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12/03/1996
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Application #:
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08528030
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Filing Dt:
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09/14/1995
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Title:
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INTERLACED LAYOUT CONFIGURATION FOR DIFFERENTIAL PAIRS OF INTERCONNECT LINES
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Patent #:
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|
Issue Dt:
|
06/18/1996
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Application #:
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08535362
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Filing Dt:
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09/28/1995
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Title:
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LOW-SKEW SIGNAL ROUTING IN A PROGRAMMABLE ARRAY
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Patent #:
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|
Issue Dt:
|
03/25/1997
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Application #:
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08551974
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Filing Dt:
|
11/02/1995
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Title:
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CONTROL GATE-ADDRESSED CMOS NON-VOLATILE CELL THAT PROGRAMS THROUGH GATES OF CMOS TRANSISTORS
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Patent #:
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|
Issue Dt:
|
12/24/1996
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Application #:
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08554092
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Filing Dt:
|
11/06/1995
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Title:
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CMOS EEPROM CELL WITH TUNNELING WINDOW IN THE READ PATH
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|
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Patent #:
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|
Issue Dt:
|
09/09/1997
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Application #:
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08560038
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Filing Dt:
|
11/17/1995
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Title:
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MEMORY CELL FOR A PROGRAMMABLE LOGIC DEVICE (PLD) AVOIDING PUMPING PROGRAMMING VOLTAGE ABOVE AN NMOS THRESHOLD
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|
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Patent #:
|
|
Issue Dt:
|
12/24/1996
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Application #:
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08560933
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Filing Dt:
|
11/20/1995
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Title:
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ARRAY OF CONFIGURABLE LOGIC BLOCKS EACH INCLUDING A LOOKUP TABLE HAVING INPUTS COUPLED TOA FIRST MULTIPLEXER AND HAVING OUTPUTS TO A SECOND MULTIPLEXER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/1997
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Application #:
|
08561306
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Filing Dt:
|
11/21/1995
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Title:
|
METHOD OF FORMING MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE
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|
|
Patent #:
|
|
Issue Dt:
|
09/15/1998
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Application #:
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08573622
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Filing Dt:
|
12/18/1995
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Title:
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MICROPPROCESSOR SYSTEM WITH PROCESS IDENTIFICATION TAG ENTRIES TO REDUCE CACHE FLUSHING AFTER A CONTEXT SWITCH
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Patent #:
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|
Issue Dt:
|
04/14/1998
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Application #:
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08574776
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Filing Dt:
|
12/19/1995
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Title:
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DECONVOLUTION INPUT BUFFER COMPENSATING FOR CAPACITANCE OF A SWITCH MATRIX OF A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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|
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Patent #:
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|
Issue Dt:
|
02/17/1998
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Application #:
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08575852
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Filing Dt:
|
12/20/1995
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Title:
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LOCK GENERATOR CIRCUIT FOR USE WITH A DUAL EDGE REGISTER THAT PROVIDES A SEPARATE ENABLE FOR EACH EDGE OF AN INPUT CLOCK SIGNAL
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Patent #:
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|
Issue Dt:
|
04/07/1998
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Application #:
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08575898
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Filing Dt:
|
12/20/1995
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Title:
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CAPACITANCE ELIMINATION CIRCUIT WHICH PROVIDES CURRENT TO A NODE IN A CIRCUIT TO ELIMINATE THE EFFECT OF PARASITIC CAPACITANCE AT THE NODE
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|
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Patent #:
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|
Issue Dt:
|
01/28/1997
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Application #:
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08596679
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Filing Dt:
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02/05/1996
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Title:
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ARRAY OF CONFIGURABLE LOGIC BLOCKS INCLUDING NETWORK MEANS FOR BROADCASTING CLOCK SIGNALS TO DIFFERENT PLURALITIES OF LOGIC BLOCKS
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|
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Patent #:
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|
Issue Dt:
|
04/22/1997
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Application #:
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08606702
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Filing Dt:
|
02/26/1996
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Title:
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FIELD PROGRAMMABLE GATE ARRAY WITH WRITE-PORT ENABLED MEMORY
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Patent #:
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|
Issue Dt:
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07/20/1999
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Application #:
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08614728
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Filing Dt:
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03/13/1996
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Title:
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SEGMENT DESCRIPTOR CACHE FOR A PROCESSOR
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Patent #:
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|
Issue Dt:
|
07/08/1997
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Application #:
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08625403
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Filing Dt:
|
03/26/1996
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Title:
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CMOS MEMORY CELL WITH TUNNELING DURING PROGRAM AND ERASE THROUGH THE NMOS AND PMOS TRANSISTORS AND A PASS GATE SEPARATING THE NMOS AND PMOS TRANSISTORS
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Patent #:
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|
Issue Dt:
|
05/12/1998
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Application #:
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08632811
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Filing Dt:
|
04/16/1996
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Title:
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PARALLEL PROGRAMMING OF IN-SYSTEM (ISP) PROGRAMMABLE DEVICES USING AN AUTOMATIC TESTER
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Patent #:
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|
Issue Dt:
|
09/09/1997
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Application #:
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08635184
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Filing Dt:
|
04/25/1996
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Title:
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ACTIVE RESISTOR FOR STABILITY COMPENSATION
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|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
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Application #:
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08643291
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Filing Dt:
|
05/08/1996
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Title:
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METHOD AND APPARATUS FOR IN-SYSTEM PROGRAMMING OF A PROGRAMMABLE LOGIC DEVICE USING A TWO-WIRE INTERFACE
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Patent #:
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Issue Dt:
|
05/05/1998
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Application #:
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08643807
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Filing Dt:
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05/06/1996
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Title:
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ARRAY CELL CIRCUIT WITH SPLIT READ/WRITE LINE
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Patent #:
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|
Issue Dt:
|
08/04/1998
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Application #:
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08653186
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Filing Dt:
|
05/24/1996
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Title:
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A METHOD FOR PROVIDING A PLURALITY OF HIERARCHICAL SIGNAL PATHS IN A VERY HIGH-DENSITY PROGRAMMABLE LOGIC DEVICE
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Patent #:
|
|
Issue Dt:
|
03/03/1998
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Application #:
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08659279
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Filing Dt:
|
06/06/1996
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Title:
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FIELD PROGRAMMABLE GATE ARRAY (FPGA) WITH INTERCONNECT ENCODING
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|
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Patent #:
|
|
Issue Dt:
|
09/15/1998
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Application #:
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08659941
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Filing Dt:
|
06/07/1996
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Title:
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FIELD PROGRAMMABLE GATE ARRAY (FPGA) HAVING AN IMPROVED CONFIGURATION MEMORY AND LOOK UP TABLE
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|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
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Application #:
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08664190
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Filing Dt:
|
06/10/1996
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Title:
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SIMPLIFIED MASKING PROCESS FOR PROGRAMMABLE LOGIC DEVICE MANUFACTURE
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Patent #:
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|
Issue Dt:
|
06/02/1998
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Application #:
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08666193
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Filing Dt:
|
06/19/1996
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Title:
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A CLOCK SIGNAL PROVIDING CIRCUIT WITH ENABLE AND A PULSE GENERATOR WITH ENABLE FOR USE IN A BLOCK CLOCK CIRCUIT OF A PROGRAMMABLE LOGIC DEVICE
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|
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Patent #:
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|
Issue Dt:
|
08/18/1998
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Application #:
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08668141
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Filing Dt:
|
06/21/1996
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Title:
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REFERENCE FOR CMOS MEMORY CELL HAVING PMOS AND NMOS TRANSISTORS WITH A COMMON FLOATING GATE
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|
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Patent #:
|
|
Issue Dt:
|
05/12/1998
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Application #:
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08668896
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Filing Dt:
|
06/24/1996
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH MULTI-LEVEL POWER CONTROL
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|
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Patent #:
|
|
Issue Dt:
|
10/06/1998
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Application #:
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08683373
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Filing Dt:
|
07/18/1996
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Title:
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TEMPERATURE INSENSITIVE CURRENT SOURCE
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|
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Patent #:
|
|
Issue Dt:
|
03/31/1998
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Application #:
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08683685
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Filing Dt:
|
07/18/1996
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Title:
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PROGRAMMABLE LOGIC DEVICE HAVING A SENSE AMPLIFIER WITH VIRTUAL GROUND
|
|
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Patent #:
|
|
Issue Dt:
|
08/24/1999
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Application #:
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08689523
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Filing Dt:
|
08/09/1996
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Title:
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AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE
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Patent #:
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Issue Dt:
|
09/01/1998
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Application #:
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08690768
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Filing Dt:
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08/01/1996
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Title:
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DEPLETION MODE PASS GATES WITH CONTROLLING DECODER AND NEGATIVE POWER SUPPLY FOR A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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08/18/1998
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Application #:
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08696444
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Filing Dt:
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08/13/1996
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Title:
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METHOD FOR PROGRAMMING A PROGRAMMABLE LOGIC DEVICE IN AN AUTOMATIC TESTER
|
|
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Patent #:
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Issue Dt:
|
09/28/1999
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Application #:
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08699401
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Filing Dt:
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08/19/1996
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Title:
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OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE
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Patent #:
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|
Issue Dt:
|
04/14/1998
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Application #:
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08700616
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Filing Dt:
|
08/16/1996
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Title:
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PROGRAMMABLE LOGIC DEVICE (PLD) HAVING DIRECT CONNECTIONS BETWEEN CONFIGURABLE LOGIC BLOCKS (CLBS) AND CONFIGURABLE INPUT/OUTPUT BLOCKS (IOBS)
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Patent #:
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Issue Dt:
|
09/28/1999
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Application #:
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08702846
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Filing Dt:
|
08/26/1996
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Title:
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DECODER CIRCUIT WITH SHORT CHANNEL DEPLETION TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
01/19/1999
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Application #:
|
08710445
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Filing Dt:
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09/17/1996
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Title:
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CONFIGURATION PIN EMULATION CIRCUIT FOR A FIELD PROGRAMMABLE GATE ARRAY
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Patent #:
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Issue Dt:
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06/02/1998
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Application #:
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08723082
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Filing Dt:
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09/30/1996
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Title:
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PROGRAMMABLE HIGH SPEED ROUTING SWITCH
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Patent #:
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Issue Dt:
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06/02/1998
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Application #:
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08726512
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Filing Dt:
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10/07/1996
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Title:
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A VPP ONLY SCALABLE EEPROM MEMORY CELL HAVING TRANSISTORS WITH THIN TUNNEL GATE OXIDE
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08729117
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Filing Dt:
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10/11/1996
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Title:
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METHOD FOR TESTING FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
|
09/08/1998
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Application #:
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08734888
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Filing Dt:
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10/22/1996
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Title:
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METHOD FOR USER-CONTROLLED I/O SWITCHING DURING IN-CIRCUIT PROGRAMMING OF CPLDS THROUGH THE IEEE 1149.1 TEST ACCESS PORT
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08740948
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Filing Dt:
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11/05/1996
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Title:
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BLOCK CLOCK AND INITIALIZATION CIRCUIT FOR A COMPLEX HIGH DENSITY PLD
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Patent #:
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Issue Dt:
|
02/10/1998
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Application #:
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08745410
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Filing Dt:
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11/22/1996
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Title:
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OUTPUT BUFFER INCORPORATING SHARED INTERMEDIATE NODES
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Patent #:
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Issue Dt:
|
04/06/1999
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Application #:
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08748041
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Filing Dt:
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11/12/1996
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Title:
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FPGA-BASED PROCESSOR
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08781882
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Filing Dt:
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01/10/1997
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Title:
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TIMED CIRCUIT SIMULATION IN HARDWARE USING FPGA'S
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Patent #:
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Issue Dt:
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11/24/1998
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Application #:
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08785096
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Filing Dt:
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01/21/1997
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Title:
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METHOD OF CHARGING AND DISCHARGING FLOATING GATE TRANSISTORS TO REDUCE LEAKAGE CURRENT
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Patent #:
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Issue Dt:
|
05/18/1999
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Application #:
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08799153
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Filing Dt:
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02/14/1997
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Title:
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METHOD AND APPARATUS INCORPORATING NITROGEN SELECTIVELY FOR DIFFERENTIAL OXIDE GROWTH
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Patent #:
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Issue Dt:
|
03/23/1999
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Application #:
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08799235
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Filing Dt:
|
02/14/1997
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Title:
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METHOD TO INCORPORATE, AND A DEVICE HAVING, OXIDE ENHANCEMENT DOPANTS USING GAS IMMERSION LASER DOPING (GILD) FOR SELECTIVELY GROWING AN OXIDE LAYER
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Patent #:
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Issue Dt:
|
02/20/2001
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Application #:
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08823953
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Filing Dt:
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03/25/1997
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Title:
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PROCESS FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE WITH HIGH DATA RETENTION INCLUDING SILICON NITRIDE ETCH STOP LAYER FORMED AT HIGH TEMPERATURE WITH LOW HYDROGEN ION CONCENTRATION
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08827671
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Filing Dt:
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04/10/1997
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Title:
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APPLICATION SPECIFIC MODULES IN A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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05/18/1999
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Application #:
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08828520
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Filing Dt:
|
04/01/1997
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Title:
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MEMORY BITS USED TO COUPLE LOOK UP TABLE INPUTS TO FACILITATE INCREASED AVAILABILITY TO ROUTING RESOURCES PARTICULARLY FOR VARIABLE SIZED LOOK UP TABLES FOR A FIELD PROGRAMMABLE GATE ARRAY (FPGA)
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Patent #:
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Issue Dt:
|
12/01/1998
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Application #:
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08831372
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Filing Dt:
|
04/23/2019
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Title:
|
FAST VERIFY FOR CMOS MEMORY CELLS
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Patent #:
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Issue Dt:
|
03/07/2000
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Application #:
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08838487
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Filing Dt:
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04/07/1997
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Title:
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IN-SYSTEM PROGRAMMABLE INTERCONNECT CIRCUIT
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Patent #:
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Issue Dt:
|
07/11/2000
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Application #:
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08843150
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Filing Dt:
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04/26/1997
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Title:
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REDUCTION OF N-CHANNEL PARASITIC TRANSISTOR LEAKAGE BY USING LOW POWER/LOW PRESSURE PHOSPHOSILICATE GLASS
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Patent #:
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Issue Dt:
|
09/07/1999
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Application #:
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08856926
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Filing Dt:
|
05/15/1997
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Title:
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DEVICES FOR SOURCING CONSTANT SUPPLY CURRENT FROM POWER SUPPLY IN SYSTEM WITH INTEGRATED CIRCUIT HAVING VARIABLE SUPPLY CURRENT REQUIREMENT
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Patent #:
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Issue Dt:
|
11/23/1999
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Application #:
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08859761
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Filing Dt:
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05/21/1997
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Title:
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PROCESS FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE WITH HIGH DATA RETENTION INCLUDING SILICON OXYNITRIDE ETCH STOP LAYER FORMED AT HIGH TEMPERATURE WITH LOW HYDROGEN ION CONCENTRATION
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Patent #:
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Issue Dt:
|
11/02/1999
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Application #:
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08871589
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Filing Dt:
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06/06/1997
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Title:
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NONVOLATILE MEMORY STRUCTURE FOR PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
|
02/22/2000
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Application #:
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08899428
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Filing Dt:
|
07/24/1997
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Title:
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FPGA HAVING PREDICTABLE OPEN-DRAIN DRIVE MODE
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Patent #:
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Issue Dt:
|
06/06/2000
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Application #:
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08912763
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Filing Dt:
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08/18/1997
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Title:
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OUTPUT BUFFER FOR MAKING A 5.0 VOLT COMPATIBLE INPUT/OUTPUT IN A 2.5 VOLT SEMICONDUCTOR PROCESS
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Patent #:
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Issue Dt:
|
03/19/2002
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Application #:
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08931798
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Filing Dt:
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09/16/1997
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Title:
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CIRCUITRY TO PROVIDE FAST CARRY
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Patent #:
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Issue Dt:
|
02/01/2000
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Application #:
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08938550
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Filing Dt:
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09/26/1997
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Title:
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HYBRID PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
|
12/29/1998
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Application #:
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08947888
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Filing Dt:
|
10/09/1997
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Title:
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DATA RETENTION OF EEPROM CELL WITH SHALLOW TRENCH ISOLATION USING THICKER LINER OXIDE
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Patent #:
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Issue Dt:
|
08/01/2000
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Application #:
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08948306
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Filing Dt:
|
10/09/1997
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Title:
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VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
|
02/22/2000
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Application #:
|
08949992
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Filing Dt:
|
10/15/1997
|
Title:
|
PROGRAMMABLE CLOCK MANAGER FOR A PROGRAMMABLE LOGIC DEVICE THAT CAN GENERATE AT LEAST TWO DIFFERENT OUTPUT CLOCKS
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