Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 037051/0053 | |
| Pages: | 2 |
| | Recorded: | 11/16/2015 | | |
| Attorney Dkt #: | 95-IMS-021; 96-IMS-025 |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08960750
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Filing Dt:
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10/29/1997
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Title:
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ON-CHIP PARALLEL-SERIAL DATA PACKET CONVERTER TO INTERCONNECT PARALLEL BUS OF INTEGRATED CIRCUIT CHIP WITH EXTERNAL DEVICE
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09033134
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Filing Dt:
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03/02/1998
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Publication #:
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Pub Dt:
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01/17/2002
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Title:
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CACHE COHERENCY MECHANISM USING AN OPERATION TO BE EXECUTED ON THE CONTENTS OF A LOCATION IN A CACHE SPECIFYING AN ADDRESS IN MAIN MEMORY
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Assignee
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| ATLAS HOUSE, THIRD AVENUE |
| GLOBE PARK |
| MARLOW BUCKS., UNITED KINGDOM SL7 1EY |
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Correspondence name and address
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STMICROELECTRONICS, INC.
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750 CANYON DRIVE, SUITE 300
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COPPELL, TX 75019
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