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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	014186/0058			Pages:	4
		Recorded:	12/10/2003
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 12

Patent #:	6574788	Issue Dt:	06/03/2003	Application #:	09712418	Filing Dt:	11/13/2000
Title:	METHOD AND SYSTEM FOR AUTOMATICALLY GENERATING LOW LEVEL PROGRAM COMMANDS AS DEPENDENCY GRAPHS FROM HIGH LEVEL PHYSICAL DESIGN STAGES

Patent #:	6557153	Issue Dt:	04/29/2003	Application #:	09714296	Filing Dt:	11/15/2000
Title:	METHOD AND SYSTEM FOR IMPLEMENTING A USER INTERFACE FOR PERFORMING PHYSICAL DESIGN OPERATIONS ON AN INTEGRATED CIRCUIT NETLIST

Patent #:	6857116	Issue Dt:	02/15/2005	Application #:	09714722	Filing Dt:	11/15/2000
Title:	OPTIMIZATION OF ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN

Patent #:	6553554	Issue Dt:	04/22/2003	Application #:	09908957	Filing Dt:	07/18/2001
Title:	METHOD AND SYSTEM FOR IMPLEMENTING A GRAPHICAL USER INTERFACE FOR DEPICTING LOOSE FLY LINE INTERCONNECTIONS BETWEEN MULTIPLE BLOCKS OF AN INTEGRATED CIRCUIT NETLIST

Patent #:	6564363	Issue Dt:	05/13/2003	Application #:	09909050	Filing Dt:	07/18/2001
Title:	METHOD AND SYSTEM FOR IMPLEMENTING A GRAPHICAL USER INTERFACE FOR DEFINING AND LINKING MULTIPLE ATTACH POINTS FOR MULTIPLE BLOCKS OF AN INTEGRATED CIRCUIT NETLIST

Patent #:	6564364	Issue Dt:	05/13/2003	Application #:	09909354	Filing Dt:	07/18/2001
Title:	METHOD AND SYSTEM FOR MAINTAINING ELEMENT ABSTRACTS OF AN INTEGRATED CIRCUIT NETLIST USING A MASTER LIBRARY FILE AND MODIFIABLE MASTER LIBRARY FILE

Patent #:	6757874	Issue Dt:	06/29/2004	Application #:	10104786	Filing Dt:	03/22/2002
Title:	FACILITATING VERIFICATION IN ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN

Patent #:	6854093	Issue Dt:	02/08/2005	Application #:	10104813	Filing Dt:	03/22/2002
Title:	FACILITATING PRESS OPERATION IN ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN

Patent #:	6865721	Issue Dt:	03/08/2005	Application #:	10104960	Filing Dt:	03/22/2002
Title:	OPTIMIZATION OF THE TOP LEVEL IN ABUTTED-PIN HEIRARCHICAL PHYSICAL DESIGN

Patent #:	6734046	Issue Dt:	05/11/2004	Application #:	10264679	Filing Dt:	10/03/2002
Title:	METHOD OF CUSTOMIZING AND USING MAPS IN GENERATING THE PADRING LAYOUT DESIGN

Patent #:	6823501	Issue Dt:	11/23/2004	Application #:	10264680	Filing Dt:	10/03/2002
Title:	METHOD OF GENERATING THE PADRING LAYOUT DESIGN USING AUTOMATION

Patent #:	7117469	Issue Dt:	10/03/2006	Application #:	10264691	Filing Dt:	10/03/2002
Title:	METHOD OF OPTIMIZING PLACEMENT AND ROUTING OF EDGE LOGIC IN PADRING LAYOUT DESIGN

Assignor

Exec Dt:

12/09/2003

Assignee

700 E. MIDDLEFIELD ROAD

MT. VIEW, CALIFORNIA 94043

Correspondence name and address
	DIANA SANCHEZ BENTZ
	COOLEY GODWARD LLP
	3000 EL CAMINO REAL
	5 PALO ALTO SQUARE
	PALO ALTO, CA 94306

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