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Reel/Frame:027545/0060   Pages: 14
Recorded: 01/10/2012
Attorney Dkt #:TIPI 5.2-030
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 26
1
Patent #:
Issue Dt:
04/25/1995
Application #:
08221740
Filing Dt:
03/31/1994
Title:
ANGLED LATERAL POCKET IMPLANTS ON P-TYPE SEMICONDUCTOR DEVICES
2
Patent #:
Issue Dt:
03/11/1997
Application #:
08258180
Filing Dt:
06/10/1994
Title:
DENSIFICATION IN AN INTERMETAL DIELECTRIC FILM
3
Patent #:
Issue Dt:
04/02/1996
Application #:
08447597
Filing Dt:
05/23/1995
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WITH SEMICONDUCTOR ELEMENTS FORMED IN A LAYER OF SEMICONDUCTOR MATERIAL PROVIDED ON A SUPPORT SLICE
4
Patent #:
Issue Dt:
11/18/1997
Application #:
08548932
Filing Dt:
10/26/1995
Title:
INTEGRATED MICROWAVE SEMICONDUCTOR DEVICE WITH ACTIVE AND PASSIVE COMPONENTS
5
Patent #:
Issue Dt:
07/14/1998
Application #:
08576538
Filing Dt:
12/21/1995
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WITH SEMICONDUCTOR ELEMENTS FORMED IN A LAYER OF SEMICONDUCTOR MATERIAL GLUED ON A SUPPORT WAFER
6
Patent #:
Issue Dt:
08/04/1998
Application #:
08579824
Filing Dt:
12/28/1995
Title:
METHODS AND APPARATUS FOR FABRICATING ANTI-FUSE DEVICES
7
Patent #:
Issue Dt:
03/24/1998
Application #:
08625742
Filing Dt:
03/29/1996
Title:
FLUORINE RESIDUE REMOVAL AFTER TUNGSTEN ETCHBACK
8
Patent #:
Issue Dt:
06/23/1998
Application #:
08641058
Filing Dt:
04/29/1996
Title:
METHOD OF MANUFACTURING A DEVICE, BY WHICH METHOD A SUBSTRATE WITH SEMICONDUCTOR ELEMENT AND CONDUCTOR TRACKS IS GLUED TO A SUPPORT BODY WITH METALLIZATION
9
Patent #:
Issue Dt:
04/07/1998
Application #:
08815245
Filing Dt:
03/12/1997
Title:
METHOD OF MANUFACTURING A HYBRID INTEGRATED CIRCUIT
10
Patent #:
Issue Dt:
10/27/1998
Application #:
08815253
Filing Dt:
03/12/1997
Title:
SEMICONDUCTOR BODY WITH A SUBSTRATE GLUED TO A SUPPORT BODY
11
Patent #:
Issue Dt:
04/14/1998
Application #:
08889716
Filing Dt:
07/08/1997
Title:
SEMICONDUCTOR DEVICE WITH A CARRIER BODY ON WHICH A SUBSTRATE WITH A SEMICONDUCTOR ELEMENT IS FASTENED BY MEANS OF A GLUE LAYER AND ON WHICH A PATTERN OF CONDUCTOR TRACKS IS FASTENED
12
Patent #:
Issue Dt:
08/15/2000
Application #:
09080784
Filing Dt:
05/18/1998
Title:
SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR ELEMENTS FORMED IN A LAYER OF SEMICONDUCTOR MATERIAL ON A SUPPORT WAFER
13
Patent #:
Issue Dt:
04/25/2000
Application #:
09085085
Filing Dt:
05/26/1998
Title:
METHOD OF MANUFACTURING AN ELECTRONIC DEVICE
14
Patent #:
Issue Dt:
09/18/2001
Application #:
09167819
Filing Dt:
10/07/1998
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
15
Patent #:
Issue Dt:
03/13/2001
Application #:
09209063
Filing Dt:
12/10/1998
Title:
SEMICONDUCTOR DEVICE WITH DIFFUSION BARRIER INCLUDED IN ELECTRICAL INSULATING LAYER
16
Patent #:
Issue Dt:
01/23/2001
Application #:
09258430
Filing Dt:
02/26/1999
Title:
SEMICONDUCTOR DEVICE COMPRISING A GLASS SUPPORTING BODY ONTO WHICH A SUBSTRATE WITH SEMICONDUCTOR ELEMENTS AND A METALIZATION IS ATTACHED BY MEANS OF AN ADHESIVE
17
Patent #:
Issue Dt:
01/23/2001
Application #:
09268259
Filing Dt:
03/15/1999
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WITH "CHIP SIZE PACKAGE"
18
Patent #:
Issue Dt:
10/30/2001
Application #:
09303830
Filing Dt:
05/03/1999
Title:
METHOD OF MAKING SHALLOW JUNCTION SEMICONDUCTOR DEVICES
19
Patent #:
Issue Dt:
06/25/2002
Application #:
09315596
Filing Dt:
05/20/1999
Title:
SEMICONDUCTOR BLOCKING LAYER FOR PREVENTING UV RADIATION DAMAGE TO MOS GATE OXIDES
20
Patent #:
Issue Dt:
04/24/2001
Application #:
09504991
Filing Dt:
02/15/2000
Title:
Method for eliminating stress induced dislocations in cmos devices
21
Patent #:
Issue Dt:
07/20/2004
Application #:
09520060
Filing Dt:
03/07/2000
Publication #:
Pub Dt:
01/09/2003
Title:
SEMICONDUCTOR DEVICE COMPRISING A NON-VOLATILE MEMORY
22
Patent #:
Issue Dt:
11/05/2002
Application #:
09557383
Filing Dt:
04/25/2000
Title:
HARD MASK PROCESS TO CONTROL ETCH PROFILES IN A GATE STACK
23
Patent #:
Issue Dt:
09/30/2003
Application #:
09795680
Filing Dt:
02/27/2001
Title:
SEMICONDUCTOR BLOCKING LAYER FOR PREVENTING UV RADIATION DAMAGE TO MOS GATE OXIDES
24
Patent #:
Issue Dt:
03/09/2004
Application #:
09906602
Filing Dt:
07/17/2001
Publication #:
Pub Dt:
01/31/2002
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
25
Patent #:
Issue Dt:
04/27/2010
Application #:
12092605
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
11/13/2008
Title:
PRODUCING A COVERED THROUGH SUBSTRATE VIA USING A TEMPORARY CAP LAYER
26
Patent #:
Issue Dt:
09/07/2010
Application #:
12444677
Filing Dt:
04/07/2009
Publication #:
Pub Dt:
04/29/2010
Title:
METHOD OF FORMING AN INTERCONNECT STRUCTURE
Assignor
1
Exec Dt:
12/17/2011
Assignee
1
2702 ORCHARD PARKWAY
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
DARYL K. NEFF
LERNER, DAVID, LITTENBERG, KRUMHOLZ &
MENTLIK, LLP
600 SOUTH AVENUE WEST
WESTFIELD, NJ 07090

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