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Reel/Frame:029715/0068   Pages: 3
Recorded: 01/29/2013
Attorney Dkt #:PAT 6997-2
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
12/17/2013
Application #:
13671124
Filing Dt:
11/07/2012
Publication #:
Pub Dt:
05/09/2013
Title:
METHOD AND SYSTEM FOR VERIFICATION OF ELECTRICAL CIRCUIT DESIGNS AT PROCESS, VOLTAGE, AND TEMPERATURE CORNERS
Assignor
1
Exec Dt:
01/07/2013
Assignee
1
101-116 RESEARCH DRIVE
SASKATOON, CANADA S7N 3R3
Correspondence name and address
BORDEN LADNER GERVAIS LLP
100 QUEEN STREET
SUITE 1100
OTTAWA, K1P 1J9 CANADA

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