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04/25/2000
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09/29/1997
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05/02/2000
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01/02/2001
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09/04/2001
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06/05/2001
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12/30/1998
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05/14/2002
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06/26/2001
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12/28/1999
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04/02/2002
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02/18/2000
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Title:
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03/18/2003
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04/20/2000
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05/29/2001
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04/28/2000
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Title:
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06/19/2001
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06/29/2000
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Title:
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06/28/2005
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07/28/2000
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Title:
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02/19/2002
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11/20/2000
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02/08/2005
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11/21/2000
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07/16/2002
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12/05/2000
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08/23/2001
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Title:
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02/03/2004
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03/02/2001
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12/06/2001
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09/17/2002
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09858335
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05/15/2001
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01/24/2002
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MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR CHIP OF AN INTEGRATED CIRCUIT INCLUDING A HIGH-DENSITY INTEGRATED CIRCUIT COMPONENTS PORTION AND A HIGH-PERFORMANCE LOGIC INTEGRATED CIRCUIT COMPONENTS PORTION
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01/14/2003
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05/30/2001
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02/07/2002
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02/11/2003
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07/18/2001
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02/14/2002
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11/12/2002
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07/19/2001
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02/14/2002
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01/28/2003
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09912638
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07/24/2001
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11/29/2001
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03/11/2003
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09919789
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07/31/2001
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04/11/2002
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NONVOLATILE SEMICONDUCTOR MEMORY CAPABLE OF SELECTIVELY ERASING A PLURALITY OF ELEMENTAL MEMORY UNITS
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12/31/2002
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10/09/2001
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05/09/2002
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07/15/2003
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10158554
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05/30/2002
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12/26/2002
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SEMICONDUCTOR MEMORY SYSTEM
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11/09/2004
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11/07/2002
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06/12/2003
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10/26/2004
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12/27/2002
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08/14/2003
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08/08/2006
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12/26/2002
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08/21/2003
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PROGRAMMING METHOD FOR A MULTILEVEL MEMORY CELL
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12/07/2004
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12/30/2002
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08/07/2003
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08/01/2006
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10356351
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01/30/2003
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10/02/2003
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07/19/2005
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02/26/2004
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08/31/2004
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04/15/2004
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01/16/2007
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07/08/2004
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02/27/2007
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10/21/2004
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12/19/2006
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09/29/2005
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05/17/2005
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08/19/2004
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04/04/2006
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12/24/2003
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09/30/2004
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10/28/2004
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11/25/2004
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02/05/2008
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03/03/2005
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02/24/2005
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02/03/2005
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05/26/2005
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08/25/2005
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08/25/2005
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12/07/2006
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02/06/2006
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Publication #:
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Pub Dt:
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09/14/2006
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Title:
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METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE THE LATERAL COUPLING EFFECTS BETWEEN MEMORY CELLS
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Patent #:
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Issue Dt:
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03/09/2010
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Application #:
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11401521
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Filing Dt:
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04/11/2006
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Publication #:
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Pub Dt:
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11/09/2006
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Title:
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ELECTRONIC NON-VOLATILE MEMORY DEVICE HAVING A CNAND STRUCTURE AND BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
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Patent #:
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Issue Dt:
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11/10/2009
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Application #:
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11401523
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Filing Dt:
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04/11/2006
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Publication #:
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Pub Dt:
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01/25/2007
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Title:
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INTEGRATED ELECTRONIC DEVICE HAVING A LOW VOLTAGE ELECTRIC SUPPLY
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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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11411010
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Filing Dt:
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04/25/2006
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Publication #:
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Pub Dt:
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11/16/2006
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Title:
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DATA STORING METHOD FOR A NON-VOLATILE MEMORY CELL ARRAY HAVING AN ERROR CORRECTION CODE
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11434564
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Filing Dt:
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05/15/2006
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Publication #:
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Pub Dt:
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11/30/2006
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Title:
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ROW DECODER CIRCUIT AND RELATED SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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08/12/2008
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Application #:
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11457966
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Filing Dt:
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07/17/2006
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Publication #:
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Pub Dt:
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02/01/2007
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Title:
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SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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11463260
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Filing Dt:
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08/08/2006
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Publication #:
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Pub Dt:
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02/14/2008
| | | | |
Title:
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HIGH VOLTAGE GENERATOR OF THE DAC-CONTROLLED TYPE
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Patent #:
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Issue Dt:
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07/28/2009
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Application #:
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11469754
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Filing Dt:
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09/01/2006
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Publication #:
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Pub Dt:
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05/10/2007
| | | | |
Title:
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MEMORY ARCHITECTURE
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|
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Patent #:
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Issue Dt:
|
09/07/2010
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Application #:
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11530199
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Filing Dt:
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09/08/2006
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Publication #:
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Pub Dt:
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05/24/2007
| | | | |
Title:
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MEMORY ARCHITECTURE WITH SERIAL PERIPHERAL INTERFACE
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Patent #:
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Issue Dt:
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05/05/2009
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Application #:
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11561799
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Filing Dt:
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11/20/2006
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Publication #:
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Pub Dt:
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07/05/2007
| | | | |
Title:
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METHOD FOR ACCESSING IN READING, WRITING AND PROGRAMMING TO A NAND NON-VOLATILE MEMORY ELECTRONIC DEVICE MONOLITHICALLY INTEGRATED ON SEMICONCTOR
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Patent #:
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Issue Dt:
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10/20/2009
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Application #:
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11636382
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Filing Dt:
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12/08/2006
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Publication #:
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Pub Dt:
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06/28/2007
| | | | |
Title:
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METHOD FOR PROGRAMMING OF MEMORY CELLS, IN PARTICULAR OF THE FLASH TYPE, AND CORRESPONDING PROGRAMMING ARCHITECTURE
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Patent #:
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|
Issue Dt:
|
12/09/2008
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Application #:
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11638321
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Filing Dt:
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12/13/2006
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Publication #:
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Pub Dt:
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07/12/2007
| | | | |
Title:
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OUTPUT BUFFER
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Patent #:
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Issue Dt:
|
03/31/2009
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Application #:
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11713074
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Filing Dt:
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02/28/2007
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Publication #:
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Pub Dt:
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01/10/2008
| | | | |
Title:
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ELECTRONIC DEVICE COMPRISING NON VOLATILE MEMORY CELLS WITH OPTIMIZED PROGRAMMING AND CORRESPONDING PROGRAMMING METHOD
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Patent #:
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Issue Dt:
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01/19/2010
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Application #:
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11713081
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Filing Dt:
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02/28/2007
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Publication #:
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Pub Dt:
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11/29/2007
| | | | |
Title:
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NON VOLATILE MEMORY DEVICE ARCHITECTURE AND CORRESPONDING PROGRAMMING METHOD
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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11732486
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Filing Dt:
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04/02/2007
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Publication #:
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Pub Dt:
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10/25/2007
| | | | |
Title:
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METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE FLOATING GATE COUPLING AND MEMORY DEVICE
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Patent #:
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Issue Dt:
|
06/23/2009
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Application #:
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11741462
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Filing Dt:
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04/27/2007
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Publication #:
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Pub Dt:
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10/30/2008
| | | | |
Title:
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REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY
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Patent #:
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Issue Dt:
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07/28/2009
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Application #:
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11771677
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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01/17/2008
| | | | |
Title:
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AUTOMATIC REGULATION METHOD FOR THE REFERENCE SOURCES IN A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING MEMORY DEVICE
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Patent #:
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Issue Dt:
|
09/06/2011
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Application #:
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11787101
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Filing Dt:
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04/13/2007
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Publication #:
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Pub Dt:
|
12/06/2007
| | | | |
Title:
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OPTIMIZED FLASH MEMORY ACCESS METHOD AND DEVICE
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Patent #:
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Issue Dt:
|
02/02/2010
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Application #:
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12104118
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Filing Dt:
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04/16/2008
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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METHOD AND CIRCUIT FOR PROGRAMMING A MEMORY CELL, IN PARTICULAR OF THE NOR FLASH TYPE
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|