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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:032148/0068   Pages: 9
Recorded: 01/31/2014
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 77
1
Patent #:
Issue Dt:
04/25/2000
Application #:
08940856
Filing Dt:
09/29/1997
Title:
FLOATING GATE NON-VOLATILE MEMORY CELL WITH LOW ERASING VOLTAGE AND MANUFACTURING METHOD
2
Patent #:
Issue Dt:
05/02/2000
Application #:
09014437
Filing Dt:
01/27/1998
Title:
PROCESS FOR FORMING AN EDGE STRUCTURE TO SEAL INTEGRATED ELECTRONIC DEVICES, AND CORRESPONDING DEVICE
3
Patent #:
Issue Dt:
01/02/2001
Application #:
09186496
Filing Dt:
11/04/1998
Title:
METHOD AND CIRCUIT FOR REGULATING THE LENGTH OF AN ATD PULSE SIGNAL
4
Patent #:
Issue Dt:
02/06/2001
Application #:
09186498
Filing Dt:
11/04/1998
Title:
MEMORY CELL VOLTAGE REGULATOR WITH TEMPERATURE CORRELATED VOLTAGE GENERATOR CIRCUIT
5
Patent #:
Issue Dt:
09/04/2001
Application #:
09220127
Filing Dt:
12/23/1998
Title:
DATA PROTECTION METHOD FOR A SEMICONDUCTOR MEMORY AND CORRESPONDING PROTECTED MEMORY DEVICE
6
Patent #:
Issue Dt:
06/05/2001
Application #:
09231129
Filing Dt:
12/30/1998
Title:
METHOD AND A CIRCUIT FOR IMPROVING THE EFFECTIVENESS OF ESD PROTECTION IN CIRCUIT STRUCTURES FORMED IN A SEMICONDUCTOR
7
Patent #:
Issue Dt:
05/14/2002
Application #:
09442834
Filing Dt:
11/18/1999
Title:
IMPROVED FIELD-EFFECT TRANSISTOR AND CORRESPONDING MANUFACTURING METHOD
8
Patent #:
Issue Dt:
06/26/2001
Application #:
09473368
Filing Dt:
12/28/1999
Title:
METHOD FOR FORMING CONTACTLESS MOS TRANSISTORS AND RESULTING DEVICES, ESPECIALLY FOR USE IN NON-VOLATILE MEMORY ARRAYS
9
Patent #:
Issue Dt:
04/02/2002
Application #:
09507777
Filing Dt:
02/18/2000
Title:
Process for manufacturing semicondutor integrated memory devices with cells matrix having virtual ground
10
Patent #:
Issue Dt:
03/18/2003
Application #:
09552933
Filing Dt:
04/20/2000
Title:
METHOD OF ADJUSTING PROGRAM VOLTAGE IN NON-VOLATILE MEMORIES, AND PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
11
Patent #:
Issue Dt:
05/29/2001
Application #:
09561271
Filing Dt:
04/28/2000
Title:
Content addressable memory protection circuit and method
12
Patent #:
Issue Dt:
06/19/2001
Application #:
09608445
Filing Dt:
06/29/2000
Title:
Voltage regulating circuit for a capacitive load
13
Patent #:
Issue Dt:
06/28/2005
Application #:
09627703
Filing Dt:
07/28/2000
Title:
NON-VOLATILE MEMORY WITH FUNCTIONAL CAPABILITY OF SIMULTANEOUS MODIFICATION OF THE CONTENT AND BURST MODE READ OR PAGE MODE READ
14
Patent #:
Issue Dt:
02/19/2002
Application #:
09716746
Filing Dt:
11/20/2000
Title:
Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit
15
Patent #:
Issue Dt:
02/08/2005
Application #:
09717938
Filing Dt:
11/21/2000
Title:
NON-VOLATILE MEMORY DEVICE WITH BURST MODE READING AND CORRESPONDING READING METHOD
16
Patent #:
Issue Dt:
07/16/2002
Application #:
09730518
Filing Dt:
12/05/2000
Publication #:
Pub Dt:
08/23/2001
Title:
MANUFACTURING PROCESS FOR NON-VOLATILE FLOATING GATE MEMORY CELLS INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND COMPRISED IN A CELL MATRIX WITH AN ASSOCIATED CONTROL CIRCUITRY
17
Patent #:
Issue Dt:
02/03/2004
Application #:
09798778
Filing Dt:
03/02/2001
Publication #:
Pub Dt:
12/06/2001
Title:
METHOD OF FORMING LOW-RESISTIVITY CONNECTIONS IN NON-VOLATILE MEMORIES
18
Patent #:
Issue Dt:
09/17/2002
Application #:
09858335
Filing Dt:
05/15/2001
Publication #:
Pub Dt:
01/24/2002
Title:
MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR CHIP OF AN INTEGRATED CIRCUIT INCLUDING A HIGH-DENSITY INTEGRATED CIRCUIT COMPONENTS PORTION AND A HIGH-PERFORMANCE LOGIC INTEGRATED CIRCUIT COMPONENTS PORTION
19
Patent #:
Issue Dt:
01/14/2003
Application #:
09871235
Filing Dt:
05/30/2001
Publication #:
Pub Dt:
02/07/2002
Title:
CIRCUITAL STRUCTURE FOR PROGRAMMING DATA IN A NON-VOLATILE MEMORY DEVICE
20
Patent #:
Issue Dt:
02/11/2003
Application #:
09908986
Filing Dt:
07/18/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHOD AND A CIRCUIT STRUCTURE FOR MODIFYING THE THRESHOLD VOLTAGES OF NON-VOLATILE MEMORY CELLS
21
Patent #:
Issue Dt:
11/12/2002
Application #:
09909467
Filing Dt:
07/19/2001
Publication #:
Pub Dt:
02/14/2002
Title:
NON-VOLATILE MEMORY WITH A CHARGE PUMP WITH REGULATED VOLTAGE
22
Patent #:
Issue Dt:
01/28/2003
Application #:
09912638
Filing Dt:
07/24/2001
Publication #:
Pub Dt:
11/29/2001
Title:
INTEGRATED CIRCUIT STRUCTURE COMPRISING CAPACITOR ELEMENT AND CORRESPONDING MANUFACTURING PROCESS
23
Patent #:
Issue Dt:
03/11/2003
Application #:
09919789
Filing Dt:
07/31/2001
Publication #:
Pub Dt:
04/11/2002
Title:
NONVOLATILE SEMICONDUCTOR MEMORY CAPABLE OF SELECTIVELY ERASING A PLURALITY OF ELEMENTAL MEMORY UNITS
24
Patent #:
Issue Dt:
12/31/2002
Application #:
09974737
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
05/09/2002
Title:
INTERNAL ADDRESSING STRUCTURE OF A SEMICONDUCTOR MEMORY
25
Patent #:
Issue Dt:
07/15/2003
Application #:
10158554
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
12/26/2002
Title:
SEMICONDUCTOR MEMORY SYSTEM
26
Patent #:
Issue Dt:
11/09/2004
Application #:
10290030
Filing Dt:
11/07/2002
Publication #:
Pub Dt:
06/12/2003
Title:
LOW POWER CHARGE PUMP CIRCUIT
27
Patent #:
Issue Dt:
10/26/2004
Application #:
10331116
Filing Dt:
12/27/2002
Publication #:
Pub Dt:
08/14/2003
Title:
REGULATION METHOD FOR THE DRAIN, BODY AND SOURCE TERMINALS VOLTAGES IN A NON-VOLATILE MEMORY CELL DURING A PROGRAM PHASE AND CORRESPONDING PROGRAM CIRCUIT
28
Patent #:
Issue Dt:
08/08/2006
Application #:
10331161
Filing Dt:
12/26/2002
Publication #:
Pub Dt:
08/21/2003
Title:
PROGRAMMING METHOD FOR A MULTILEVEL MEMORY CELL
29
Patent #:
Issue Dt:
12/07/2004
Application #:
10334126
Filing Dt:
12/30/2002
Publication #:
Pub Dt:
08/07/2003
Title:
POWER SUPPLY CIRCUIT STRUCTURE FOR A ROW DECODER OF A MULTILEVEL NON-VOLATILE MEMORY DEVICE
30
Patent #:
Issue Dt:
08/01/2006
Application #:
10356351
Filing Dt:
01/30/2003
Publication #:
Pub Dt:
10/02/2003
Title:
MANUFACTURING PROCESS OF AN INTERPOLY DIELECTRIC STRUCTURE FOR NON-VOLATILE SEMICONDUCTOR INTEGRATED MEMORIES
31
Patent #:
Issue Dt:
07/19/2005
Application #:
10438175
Filing Dt:
05/13/2003
Publication #:
Pub Dt:
02/26/2004
Title:
PROGRAMMING METHOD OF THE MEMORY CELLS IN A MULTILEVEL NON-VOLATILE MEMORY DEVICE
32
Patent #:
Issue Dt:
08/31/2004
Application #:
10447293
Filing Dt:
05/28/2003
Publication #:
Pub Dt:
04/15/2004
Title:
TESTING METHOD AND DEVICE FOR NON-VOLATILE MEMORIES HAVING A LPC (LOW PIN COUNT) COMMUNICATION SERIAL INTERFACE
33
Patent #:
Issue Dt:
01/16/2007
Application #:
10631463
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
07/08/2004
Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURES
34
Patent #:
Issue Dt:
02/27/2007
Application #:
10675221
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
10/21/2004
Title:
METHOD FOR ERASING NON-VOLATILE MEMORY CELLS AND CORRESPONDING MEMORY DEVICE
35
Patent #:
Issue Dt:
12/19/2006
Application #:
10727341
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
09/29/2005
Title:
NON-VOLATILE MEMORY DEVICE ARCHITECTURE, FOR INSTANCE A FLASH KIND, HAVING A SERIAL COMMUNICATION INTERFACE
36
Patent #:
Issue Dt:
05/17/2005
Application #:
10728372
Filing Dt:
12/04/2003
Publication #:
Pub Dt:
08/19/2004
Title:
NON-VOLATILE MEMORY CELL SENSING CIRCUIT, PARTICULARLY FOR LOW POWER SUPPLY VOLTAGES AND HIGH CAPACITIVE LOAD VALUES
37
Patent #:
Issue Dt:
04/04/2006
Application #:
10746555
Filing Dt:
12/24/2003
Publication #:
Pub Dt:
09/30/2004
Title:
SEMICONDUCTOR MEMORY SYSTEM INCLUDING SELECTION TRANSISTORS
38
Patent #:
Issue Dt:
04/18/2006
Application #:
10748701
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
10/28/2004
Title:
STABILIZATION METHOD FOR DRAIN VOLTAGE IN NON-VOLATILE MULTI-LEVEL MEMORY CELLS AND RELATED MEMORY DEVICE
39
Patent #:
Issue Dt:
11/21/2006
Application #:
10789351
Filing Dt:
02/26/2004
Publication #:
Pub Dt:
11/25/2004
Title:
VOLTAGE REGULATION SYSTEM FOR A MULTIWORD PROGRAMMING OF A LOW INTEGRATION AREA NON VOLATILE MEMORY
40
Patent #:
Issue Dt:
02/05/2008
Application #:
10805168
Filing Dt:
03/19/2004
Publication #:
Pub Dt:
03/03/2005
Title:
METHOD FOR PERFORMING ERROR CORRECTIONS OF DIGITAL INFORMATION CODIFIED AS A SYMBOL SEQUENCE
41
Patent #:
Issue Dt:
06/01/2010
Application #:
10805182
Filing Dt:
03/19/2004
Publication #:
Pub Dt:
11/18/2004
Title:
INTEGRATED MEMORY SYSTEM
42
Patent #:
Issue Dt:
10/26/2010
Application #:
10890529
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
02/24/2005
Title:
METHOD FOR MANUFACTURING DIFFERENTIAL ISOLATION STRUCTURES IN A SEMICONDUCTOR ELECTRONIC DEVICE AND CORRESPONDING STRUCTURE
43
Patent #:
Issue Dt:
05/08/2007
Application #:
10909749
Filing Dt:
08/02/2004
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD FOR THE FABRICATION OF ISOLATION STRUCTURES
44
Patent #:
Issue Dt:
07/18/2006
Application #:
10971774
Filing Dt:
10/22/2004
Publication #:
Pub Dt:
05/26/2005
Title:
SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE
45
Patent #:
Issue Dt:
10/30/2007
Application #:
11009687
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
08/25/2005
Title:
METHOD FOR REDUCING DEFECTS AFTER A METAL ETCHING IN SEMICONDUCTOR DEVICES
46
Patent #:
Issue Dt:
03/20/2007
Application #:
11059294
Filing Dt:
02/16/2005
Publication #:
Pub Dt:
08/25/2005
Title:
METHOD FOR REDUCING NON-UNIFORMITY OR TOPOGRAPHY VARIATION BETWEEN AN ARRAY AND CIRCUITRY IN A PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED NON-VOLATILE MEMORY DEVICES
47
Patent #:
Issue Dt:
11/25/2008
Application #:
11258675
Filing Dt:
10/25/2005
Publication #:
Pub Dt:
03/02/2006
Title:
PROCESS FOR MANUFACTURING A BYTE SELECTION TRANSISTOR FOR A MATRIX OF NON VOLATILE MEMORY CELLS AND CORRESPONDING STRUCTURE
48
Patent #:
Issue Dt:
04/16/2013
Application #:
11261131
Filing Dt:
10/28/2005
Publication #:
Pub Dt:
05/04/2006
Title:
Flash memory device with a low pin count (LPC) communication interface
49
Patent #:
Issue Dt:
01/08/2008
Application #:
11261903
Filing Dt:
10/27/2005
Publication #:
Pub Dt:
06/08/2006
Title:
PROGRAMMING METHOD OF MULTILEVEL MEMORIES AND CORRESPONDING CIRCUIT
50
Patent #:
Issue Dt:
07/08/2008
Application #:
11279381
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
12/07/2006
Title:
NON-VOLATILE MEMORY ELECTRONIC DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
51
Patent #:
Issue Dt:
11/13/2007
Application #:
11279384
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
10/12/2006
Title:
INTEGRATED ELECTRONIC NON-VOLATILE MEMORY DEVICE HAVING NAND STRUCTURE
52
Patent #:
Issue Dt:
09/02/2014
Application #:
11279385
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
10/26/2006
Title:
NON-VOLATILE ELECTRONIC MEMORY DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
53
Patent #:
Issue Dt:
06/17/2008
Application #:
11280803
Filing Dt:
11/16/2005
Publication #:
Pub Dt:
06/22/2006
Title:
METHOD FOR CONFIGURING A VOLTAGE REGULATOR
54
Patent #:
Issue Dt:
01/15/2008
Application #:
11300053
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
07/20/2006
Title:
ELECTRONIC MEMORY DEVICE HAVING HIGH DENSITY NON-VOLATILE MEMORY CELLS AND A REDUCED CAPACITIVE INTERFERENCE CELL-TO-CELL
55
Patent #:
Issue Dt:
09/22/2009
Application #:
11300145
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
07/20/2006
Title:
ELECTRONIC MEMORY DEVICE HAVING HIGH INTEGRATION DENSITY NON-VOLATILE MEMORY CELLS AND A REDUCED CAPACITIVE COUPLING
56
Patent #:
Issue Dt:
02/05/2008
Application #:
11319750
Filing Dt:
12/27/2005
Publication #:
Pub Dt:
07/27/2006
Title:
METHOD FOR MANUFACTURING ELECTRONIC NON-VOLATILE MEMORY DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE
57
Patent #:
Issue Dt:
09/02/2008
Application #:
11319798
Filing Dt:
12/27/2005
Publication #:
Pub Dt:
08/17/2006
Title:
METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE
58
Patent #:
Issue Dt:
02/02/2010
Application #:
11344519
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
08/10/2006
Title:
REMOVABLE DATA STORAGE DEVICE AND RELATED ASSEMBLING METHOD
59
Patent #:
Issue Dt:
12/30/2008
Application #:
11348513
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
09/14/2006
Title:
METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE THE LATERAL COUPLING EFFECTS BETWEEN MEMORY CELLS
60
Patent #:
Issue Dt:
03/09/2010
Application #:
11401521
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
11/09/2006
Title:
ELECTRONIC NON-VOLATILE MEMORY DEVICE HAVING A CNAND STRUCTURE AND BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
61
Patent #:
Issue Dt:
11/10/2009
Application #:
11401523
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
01/25/2007
Title:
INTEGRATED ELECTRONIC DEVICE HAVING A LOW VOLTAGE ELECTRIC SUPPLY
62
Patent #:
Issue Dt:
01/26/2010
Application #:
11411010
Filing Dt:
04/25/2006
Publication #:
Pub Dt:
11/16/2006
Title:
DATA STORING METHOD FOR A NON-VOLATILE MEMORY CELL ARRAY HAVING AN ERROR CORRECTION CODE
63
Patent #:
Issue Dt:
04/28/2009
Application #:
11434564
Filing Dt:
05/15/2006
Publication #:
Pub Dt:
11/30/2006
Title:
ROW DECODER CIRCUIT AND RELATED SYSTEM AND METHOD
64
Patent #:
Issue Dt:
08/12/2008
Application #:
11457966
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
02/01/2007
Title:
SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE
65
Patent #:
Issue Dt:
04/27/2010
Application #:
11463260
Filing Dt:
08/08/2006
Publication #:
Pub Dt:
02/14/2008
Title:
HIGH VOLTAGE GENERATOR OF THE DAC-CONTROLLED TYPE
66
Patent #:
Issue Dt:
07/28/2009
Application #:
11469754
Filing Dt:
09/01/2006
Publication #:
Pub Dt:
05/10/2007
Title:
MEMORY ARCHITECTURE
67
Patent #:
Issue Dt:
09/07/2010
Application #:
11530199
Filing Dt:
09/08/2006
Publication #:
Pub Dt:
05/24/2007
Title:
MEMORY ARCHITECTURE WITH SERIAL PERIPHERAL INTERFACE
68
Patent #:
Issue Dt:
05/05/2009
Application #:
11561799
Filing Dt:
11/20/2006
Publication #:
Pub Dt:
07/05/2007
Title:
METHOD FOR ACCESSING IN READING, WRITING AND PROGRAMMING TO A NAND NON-VOLATILE MEMORY ELECTRONIC DEVICE MONOLITHICALLY INTEGRATED ON SEMICONCTOR
69
Patent #:
Issue Dt:
10/20/2009
Application #:
11636382
Filing Dt:
12/08/2006
Publication #:
Pub Dt:
06/28/2007
Title:
METHOD FOR PROGRAMMING OF MEMORY CELLS, IN PARTICULAR OF THE FLASH TYPE, AND CORRESPONDING PROGRAMMING ARCHITECTURE
70
Patent #:
Issue Dt:
12/09/2008
Application #:
11638321
Filing Dt:
12/13/2006
Publication #:
Pub Dt:
07/12/2007
Title:
OUTPUT BUFFER
71
Patent #:
Issue Dt:
03/31/2009
Application #:
11713074
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
01/10/2008
Title:
ELECTRONIC DEVICE COMPRISING NON VOLATILE MEMORY CELLS WITH OPTIMIZED PROGRAMMING AND CORRESPONDING PROGRAMMING METHOD
72
Patent #:
Issue Dt:
01/19/2010
Application #:
11713081
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
11/29/2007
Title:
NON VOLATILE MEMORY DEVICE ARCHITECTURE AND CORRESPONDING PROGRAMMING METHOD
73
Patent #:
Issue Dt:
03/30/2010
Application #:
11732486
Filing Dt:
04/02/2007
Publication #:
Pub Dt:
10/25/2007
Title:
METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE FLOATING GATE COUPLING AND MEMORY DEVICE
74
Patent #:
Issue Dt:
06/23/2009
Application #:
11741462
Filing Dt:
04/27/2007
Publication #:
Pub Dt:
10/30/2008
Title:
REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY
75
Patent #:
Issue Dt:
07/28/2009
Application #:
11771677
Filing Dt:
06/29/2007
Publication #:
Pub Dt:
01/17/2008
Title:
AUTOMATIC REGULATION METHOD FOR THE REFERENCE SOURCES IN A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING MEMORY DEVICE
76
Patent #:
Issue Dt:
09/06/2011
Application #:
11787101
Filing Dt:
04/13/2007
Publication #:
Pub Dt:
12/06/2007
Title:
OPTIMIZED FLASH MEMORY ACCESS METHOD AND DEVICE
77
Patent #:
Issue Dt:
02/02/2010
Application #:
12104118
Filing Dt:
04/16/2008
Publication #:
Pub Dt:
10/23/2008
Title:
METHOD AND CIRCUIT FOR PROGRAMMING A MEMORY CELL, IN PARTICULAR OF THE NOR FLASH TYPE
Assignor
1
Exec Dt:
04/25/2012
Assignee
1
A-ONE BIZ CENTER, Z.A. VERS LA PIECE
RTE DE L'ETRAZ
1180 ROLLE, SWITZERLAND
Correspondence name and address
DORSEY & WHITNEY LLP
701 5TH AVENUE, SUITE 6100
SEATTLE, WA 98104

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